From 1b0bb2543b3d38a4a87da6fe28d9754469200768 Mon Sep 17 00:00:00 2001
From: Sean Cross <sean@xobs.io>
Date: Sun, 21 Jul 2019 17:10:05 +0800
Subject: [PATCH] hw: foboot-bitstream: use 12-bit reset counter

It doesn't need to be 13 bits, and it saves us a few LCs.

Signed-off-by: Sean Cross <sean@xobs.io>
---
 hw/foboot-bitstream.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/foboot-bitstream.py b/hw/foboot-bitstream.py
index 268ab21..cdbc1a9 100755
--- a/hw/foboot-bitstream.py
+++ b/hw/foboot-bitstream.py
@@ -172,7 +172,7 @@ class _CRG(Module):
         clk48_raw = platform.request("clk48")
         clk12 = Signal()
 
-        reset_delay = Signal(13, reset=8191)
+        reset_delay = Signal(12, reset=4095)
         self.clock_domains.cd_por = ClockDomain()
         self.reset = Signal()