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Flash mapping address fixes

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- too many bits were allocated causing problems addressing 128Mbit devices
- the shift operator in python generates a signed shift in verilog which potentilly trashes the upper address bit, switch to padding
This commit is contained in:
Tom Keddie 2019-07-03 02:59:20 -07:00
parent 1033016932
commit 1c8c1f3bc1
1 changed files with 4 additions and 2 deletions
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6
hw/foboot-bitstream.py
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@ -478,8 +478,10 @@ class PicoRVSpi(Module, AutoCSR):
] ]
flash_addr = Signal(24) flash_addr = Signal(24)
mem_bits = bits_for(size) # size/4 because data bus is 32 bits wide, -1 for base 0
self.comb += flash_addr.eq(bus.adr[0:mem_bits-2] << 2), mem_bits = bits_for(int(size/4)-1)
pad = Signal(2)
self.comb += flash_addr.eq(Cat(pad, bus.adr[0:mem_bits-1]))
read_active = Signal() read_active = Signal()
spi_ready = Signal() spi_ready = Signal()