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Flash mapping address fixes
- too many bits were allocated causing problems addressing 128Mbit devices - the shift operator in python generates a signed shift in verilog which potentilly trashes the upper address bit, switch to padding
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@ -478,8 +478,10 @@ class PicoRVSpi(Module, AutoCSR):
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flash_addr = Signal(24)
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mem_bits = bits_for(size)
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self.comb += flash_addr.eq(bus.adr[0:mem_bits-2] << 2),
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# size/4 because data bus is 32 bits wide, -1 for base 0
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mem_bits = bits_for(int(size/4)-1)
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pad = Signal(2)
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self.comb += flash_addr.eq(Cat(pad, bus.adr[0:mem_bits-1]))
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read_active = Signal()
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spi_ready = Signal()
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