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foboot-bitstream: fix conflict with spibone

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Previously, we had two different spibone implementations due to a failed
merge.  This removes the second one.

Signed-off-by: Sean Cross <sean@xobs.io>
This commit is contained in:
Sean Cross 2019-11-22 11:33:22 +08:00
parent d4b1a64dca
commit 2d8b8cb047
1 changed files with 2 additions and 17 deletions
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19
hw/foboot-bitstream.py
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@ -674,7 +674,7 @@ class BaseSoC(SoCCore):
("spidebug", 0,
Subsignal("mosi", Pins("dbg:0")),
Subsignal("miso", Pins("dbg:1")),
Subsignal("clk", Pins("dbg:2")),
Subsignal("clk", Pins("dbg:2")),
Subsignal("cs_n", Pins("dbg:3")),
)
]
@ -683,28 +683,13 @@ class BaseSoC(SoCCore):
self.submodules.spibone = ClockDomainsRenamer("usb_12")(spibone.SpiWishboneBridge(spi_pads, wires=4))
self.add_wb_master(self.spibone.wishbone)
if hasattr(self, "cpu"):
# self.cpu.use_external_variant("rtl/VexRiscv_Fomu_Debug.v")
self.cpu.use_external_variant("rtl/VexRiscv_Fomu_Debug.v")
os.path.join(output_dir, "gateware")
self.register_mem("vexriscv_debug", 0xf00f0000, self.cpu.debug_bus, 0x100)
else:
if hasattr(self, "cpu"):
self.cpu.use_external_variant("rtl/VexRiscv_Fomu.v")
# Add SPI Wishbone bridge
if debug == "spi":
spibone_device = [
("spibone_pins", 0,
Subsignal("mosi", Pins("dbg:0")),
Subsignal("miso", Pins("dbg:1")),
Subsignal("clk", Pins("dbg:2")),
Subsignal("cs_n", Pins("dbg:3")),
)
]
platform.add_extension(spibone_device)
spi_pads = platform.request("spibone_pins")
self.submodules.spibone = ClockDomainsRenamer("usb_12")(spibone.SpiWishboneBridge(spi_pads, wires=4))
self.add_wb_master(self.spibone.wishbone)
# SPRAM- UP5K has single port RAM, might as well use it as SRAM to
# free up scarce block RAM.
spram_size = 128*1024