From 11f2fa87960a0143c759cd9fdec223aea668c0f3 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 2 Jan 2020 10:02:27 +0100 Subject: [PATCH 1/2] hw/foboot-bitstream: keep up to date with LiteX's iCE40 backend Arachne-pnr support removed, use yosys/build_template insead of nextpnr_yosys/build_template --- hw/foboot-bitstream.py | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/hw/foboot-bitstream.py b/hw/foboot-bitstream.py index 8b48290..62e3f99 100755 --- a/hw/foboot-bitstream.py +++ b/hw/foboot-bitstream.py @@ -256,20 +256,19 @@ class BaseSoC(SoCCore, AutoDoc): # and the "-dffe_min_ce_use 4" flag prevents Yosys from generating a # Clock Enable signal for a LUT that has fewer than 4 flip-flops. # This increases density, and lets us use the FPGA more efficiently. - platform.toolchain.nextpnr_yosys_template[2] += " -relut -abc2 -dffe_min_ce_use 4 -relut" + platform.toolchain.yosys_template[2] += " -relut -abc2 -dffe_min_ce_use 4 -relut" if use_dsp: - platform.toolchain.nextpnr_yosys_template[2] += " -dsp" + platform.toolchain.yosys_template[2] += " -dsp" # Disable final deep-sleep power down so firmware words are loaded # onto softcore's address bus. - platform.toolchain.build_template[3] = "icepack -s {build_name}.txt {build_name}.bin" - platform.toolchain.nextpnr_build_template[2] = "icepack -s {build_name}.txt {build_name}.bin" + platform.toolchain.build_template[2] = "icepack -s {build_name}.txt {build_name}.bin" # Allow us to set the nextpnr seed - platform.toolchain.nextpnr_build_template[1] += " --seed " + str(pnr_seed) + platform.toolchain.build_template[1] += " --seed " + str(pnr_seed) if placer is not None: - platform.toolchain.nextpnr_build_template[1] += " --placer {}".format(placer) + platform.toolchain.build_template[1] += " --placer {}".format(placer) def copy_memory_file(self, src): import os From 0c2b05cbe6d65837af1d06711ff960aa3be3492b Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 2 Jan 2020 10:33:46 +0100 Subject: [PATCH 2/2] hw/foboot-bitstream: provide yosys/build_template before override. Since overridesof the template are done at precise locations (ex: yosys_template[2] += ...), it's probably better to provide the template in foboot-bitstream. This allow more flexibility for LiteX's default templates to change/evolve, while also easing foboot-bitstream code understanding. The override code could also be simplified with the templates provided. --- hw/foboot-bitstream.py | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/hw/foboot-bitstream.py b/hw/foboot-bitstream.py index 62e3f99..5900204 100755 --- a/hw/foboot-bitstream.py +++ b/hw/foboot-bitstream.py @@ -251,6 +251,21 @@ class BaseSoC(SoCCore, AutoDoc): ("0x3f", "?", "Unknown model"), ]) + # Override default LiteX's yosys/build templates + assert hasattr(platform.toolchain, "yosys_template") + assert hasattr(platform.toolchain, "build_template") + platform.toolchain.yosys_template = [ + "{read_files}", + "attrmap -tocase keep -imap keep=\"true\" keep=1 -imap keep=\"false\" keep=0 -remove keep=0", + "synth_ice40 -json {build_name}.json -top {build_name}", + ] + platform.toolchain.build_template = [ + "yosys -q -l {build_name}.rpt {build_name}.ys", + "nextpnr-ice40 --json {build_name}.json --pcf {build_name}.pcf --asc {build_name}.txt \ + --pre-pack {build_name}_pre_pack.py --{architecture} --package {package}", + "icepack {build_name}.txt {build_name}.bin" + ] + # Add "-relut -dffe_min_ce_use 4" to the synth_ice40 command. # The "-reult" adds an additional LUT pass to pack more stuff in, # and the "-dffe_min_ce_use 4" flag prevents Yosys from generating a