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hw: foboot-bitstream: once again, update dff

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Now that we're not so constrained, we can correct this again.

Signed-off-by: Sean Cross <sean@xobs.io>
This commit is contained in:
Sean Cross 2019-07-22 08:56:14 +08:00
parent 6c1f63344c
commit 63d73db50f
1 changed files with 1 additions and 1 deletions
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hw/foboot-bitstream.py
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@ -771,7 +771,7 @@ class BaseSoC(SoCCore):
# and the "-dffe_min_ce_use 4" flag prevents Yosys from generating a
# Clock Enable signal for a LUT that has fewer than 4 flip-flops.
# This increases density, and lets us use the FPGA more efficiently.
platform.toolchain.nextpnr_yosys_template[2] += " -relut -dffe_min_ce_use 5"
platform.toolchain.nextpnr_yosys_template[2] += " -relut -dffe_min_ce_use 4"
if use_dsp:
platform.toolchain.nextpnr_yosys_template[2] += " -dsp"