From d147af1e6a8f47185a6241c5bc5adbe87e220919 Mon Sep 17 00:00:00 2001 From: Sean Cross Date: Thu, 25 Apr 2019 23:23:54 +0800 Subject: [PATCH] hw: add some vexriscv experiments We're trying to improve performance and reduce core size. This uses a newer version of the vexriscv core. It has a shorter pipeline, with better exception handling. It also properly initializes registers. Signed-off-by: Sean Cross --- hw/2-stage-1024-cache.yaml | 4 - hw/foboot-bitstream.py | 28 +- hw/rtl/2-stage-1024-cache-debug.v | 3606 ++++++++++++++++ ...debug.v_toplevel_RegFilePlugin_regFile.bin | Bin 0 -> 1056 bytes hw/{ => rtl}/2-stage-1024-cache-debug.yaml | 2 +- hw/{ => rtl}/2-stage-1024-cache.v | 3671 ++++++++--------- hw/rtl/2-stage-1024-cache.yaml | 4 + hw/rtl/2-stage-2048-cache-debug.v | 3606 ++++++++++++++++ ...debug.v_toplevel_RegFilePlugin_regFile.bin | Bin 0 -> 1056 bytes hw/rtl/2-stage-2048-cache-debug.yaml | 5 + hw/rtl/2-stage-2048-cache.v | 3289 +++++++++++++++ ...cache.v_toplevel_RegFilePlugin_regFile.bin | Bin 0 -> 1056 bytes hw/rtl/2-stage-2048-cache.yaml | 4 + .../2-stage-512-cache-debug.v} | 58 +- hw/rtl/2-stage-512-cache-debug.yaml | 5 + hw/{ => rtl}/2-stage-no-cache-debug.v | 0 ...debug.v_toplevel_RegFilePlugin_regFile.bin | Bin 0 -> 1056 bytes hw/{ => rtl}/2-stage-no-cache-debug.yaml | 0 hw/{ => rtl}/4-stage-1024-cache-debug.v | 0 ...debug.v_toplevel_RegFilePlugin_regFile.bin | Bin 0 -> 1056 bytes hw/{ => rtl}/4-stage-1024-cache-debug.yaml | 0 hw/{ => rtl}/4-stage-no-cache-debug.v | 0 ...debug.v_toplevel_RegFilePlugin_regFile.bin | Bin 0 -> 1056 bytes hw/{ => rtl}/4-stage-no-cache-debug.yaml | 0 .../5-stage-pipelined-no-cache-debug.v | 0 .../5-stage-pipelined-no-cache-debug.yaml | 0 hw/{ => rtl}/spimemio.v | 0 27 files changed, 12354 insertions(+), 1928 deletions(-) delete mode 100644 hw/2-stage-1024-cache.yaml create mode 100644 hw/rtl/2-stage-1024-cache-debug.v create mode 100644 hw/rtl/2-stage-1024-cache-debug.v_toplevel_RegFilePlugin_regFile.bin rename hw/{ => rtl}/2-stage-1024-cache-debug.yaml (79%) rename hw/{ => rtl}/2-stage-1024-cache.v (51%) create mode 100644 hw/rtl/2-stage-1024-cache.yaml create mode 100644 hw/rtl/2-stage-2048-cache-debug.v create mode 100644 hw/rtl/2-stage-2048-cache-debug.v_toplevel_RegFilePlugin_regFile.bin create mode 100644 hw/rtl/2-stage-2048-cache-debug.yaml create mode 100644 hw/rtl/2-stage-2048-cache.v create mode 100644 hw/rtl/2-stage-2048-cache.v_toplevel_RegFilePlugin_regFile.bin create mode 100644 hw/rtl/2-stage-2048-cache.yaml rename hw/{2-stage-1024-cache-debug.v => rtl/2-stage-512-cache-debug.v} (99%) create mode 100644 hw/rtl/2-stage-512-cache-debug.yaml rename hw/{ => rtl}/2-stage-no-cache-debug.v (100%) create mode 100644 hw/rtl/2-stage-no-cache-debug.v_toplevel_RegFilePlugin_regFile.bin rename hw/{ => rtl}/2-stage-no-cache-debug.yaml (100%) rename hw/{ => rtl}/4-stage-1024-cache-debug.v (100%) create mode 100644 hw/rtl/4-stage-1024-cache-debug.v_toplevel_RegFilePlugin_regFile.bin rename hw/{ => rtl}/4-stage-1024-cache-debug.yaml (100%) rename hw/{ => rtl}/4-stage-no-cache-debug.v (100%) create mode 100644 hw/rtl/4-stage-no-cache-debug.v_toplevel_RegFilePlugin_regFile.bin rename hw/{ => rtl}/4-stage-no-cache-debug.yaml (100%) rename hw/{ => rtl}/5-stage-pipelined-no-cache-debug.v (100%) rename hw/{ => rtl}/5-stage-pipelined-no-cache-debug.yaml (100%) rename hw/{ => rtl}/spimemio.v (100%) diff --git a/hw/2-stage-1024-cache.yaml b/hw/2-stage-1024-cache.yaml deleted file mode 100644 index 88e2fc4..0000000 --- a/hw/2-stage-1024-cache.yaml +++ /dev/null @@ -1,4 +0,0 @@ -iBus: !!vexriscv.BusReport - flushInstructions: [16399, 19, 19, 19] - info: !!vexriscv.CacheReport {bytePerLine: 32, size: 1024} - kind: cached diff --git a/hw/foboot-bitstream.py b/hw/foboot-bitstream.py index 882450f..30db185 100755 --- a/hw/foboot-bitstream.py +++ b/hw/foboot-bitstream.py @@ -195,7 +195,7 @@ class _CRG(Module): # POR reset logic- POR generated from sys clk, POR logic feeds sys clk # reset. self.clock_domains.cd_por = ClockDomain() - reset_delay = Signal(14, reset=4095) + reset_delay = Signal(10, reset=1023) self.comb += [ self.cd_por.clk.eq(self.cd_sys.clk), self.cd_sys.rst.eq(reset_delay != 0), @@ -546,7 +546,7 @@ class PicoRVSpi(Module, AutoCSR): i_cfgreg_di = cfg, o_cfgreg_do = cfg_out, ) - platform.add_source("spimemio.v") + platform.add_source("rtl/spimemio.v") class BBSpi(Module, AutoCSR): def __init__(self, platform, pads): @@ -617,10 +617,13 @@ class BaseSoC(SoCCore): def __init__(self, platform, boot_source="rand", debug=None, bios_file=None, use_pll=True, - use_dsp=False, placer=None, **kwargs): + use_dsp=False, placer=None, output_dir="build", + **kwargs): # Disable integrated RAM as we'll add it later self.integrated_sram_size = 0 + self.output_dir = output_dir + clk_freq = int(12e6) self.submodules.crg = _CRG(platform, use_pll=use_pll) @@ -635,11 +638,14 @@ class BaseSoC(SoCCore): elif debug == "usb": usb_debug = True if hasattr(self, "cpu"): - self.cpu.use_external_variant("2-stage-1024-cache-debug.v") + self.cpu.use_external_variant("rtl/2-stage-1024-cache-debug.v") + self.copy_memory_file("2-stage-1024-cache-debug.v_toplevel_RegFilePlugin_regFile.bin") + os.path.join(output_dir, "gateware") self.register_mem("vexriscv_debug", 0xf00f0000, self.cpu.debug_bus, 0x10) else: if hasattr(self, "cpu"): - self.cpu.use_external_variant("2-stage-1024-cache.v") + self.cpu.use_external_variant("rtl/2-stage-1024-cache.v") + self.copy_memory_file("2-stage-1024-cache.v_toplevel_RegFilePlugin_regFile.bin") # SPRAM- UP5K has single port RAM, might as well use it as SRAM to # free up scarce block RAM. @@ -721,6 +727,15 @@ class BaseSoC(SoCCore): if placer is not None: platform.toolchain.nextpnr_build_template[1] += " --placer {}".format(placer) + def copy_memory_file(self, src): + import os + from shutil import copyfile + if not os.path.exists(self.output_dir): + os.mkdir(self.output_dir) + if not os.path.exists(os.path.join(self.output_dir, "gateware")): + os.mkdir(os.path.join(self.output_dir, "gateware")) + copyfile(os.path.join("rtl", src), os.path.join(self.output_dir, "gateware", src)) + def make_multiboot_header(filename, boot_offsets=[160]): """ ICE40 allows you to program the SB_WARMBOOT state machine by adding the following @@ -846,7 +861,8 @@ def main(): soc = BaseSoC(platform, cpu_type=cpu_type, cpu_variant=cpu_variant, debug=args.with_debug, boot_source=args.boot_source, bios_file=args.bios, use_pll=not args.no_pll, - use_dsp=args.with_dsp, placer=args.placer) + use_dsp=args.with_dsp, placer=args.placer, + output_dir=output_dir) builder = Builder(soc, output_dir=output_dir, csr_csv="test/csr.csv", compile_software=compile_software) if compile_software: builder.software_packages = [ diff --git a/hw/rtl/2-stage-1024-cache-debug.v b/hw/rtl/2-stage-1024-cache-debug.v new file mode 100644 index 0000000..01e9da9 --- /dev/null +++ b/hw/rtl/2-stage-1024-cache-debug.v @@ -0,0 +1,3606 @@ +// Generator : SpinalHDL v1.3.3 git head : 8b8cd335eecbea3b5f1f970f218a982dbdb12d99 +// Date : 25/04/2019, 14:50:43 +// Component : VexRiscv + + +`define AluCtrlEnum_defaultEncoding_type [1:0] +`define AluCtrlEnum_defaultEncoding_ADD_SUB 2'b00 +`define AluCtrlEnum_defaultEncoding_SLT_SLTU 2'b01 +`define AluCtrlEnum_defaultEncoding_BITWISE 2'b10 + +`define Src2CtrlEnum_defaultEncoding_type [1:0] +`define Src2CtrlEnum_defaultEncoding_RS 2'b00 +`define Src2CtrlEnum_defaultEncoding_IMI 2'b01 +`define Src2CtrlEnum_defaultEncoding_IMS 2'b10 +`define Src2CtrlEnum_defaultEncoding_PC 2'b11 + +`define Src1CtrlEnum_defaultEncoding_type [1:0] +`define Src1CtrlEnum_defaultEncoding_RS 2'b00 +`define Src1CtrlEnum_defaultEncoding_IMU 2'b01 +`define Src1CtrlEnum_defaultEncoding_PC_INCREMENT 2'b10 +`define Src1CtrlEnum_defaultEncoding_URS1 2'b11 + +`define BranchCtrlEnum_defaultEncoding_type [1:0] +`define BranchCtrlEnum_defaultEncoding_INC 2'b00 +`define BranchCtrlEnum_defaultEncoding_B 2'b01 +`define BranchCtrlEnum_defaultEncoding_JAL 2'b10 +`define BranchCtrlEnum_defaultEncoding_JALR 2'b11 + +`define ShiftCtrlEnum_defaultEncoding_type [1:0] +`define ShiftCtrlEnum_defaultEncoding_DISABLE_1 2'b00 +`define ShiftCtrlEnum_defaultEncoding_SLL_1 2'b01 +`define ShiftCtrlEnum_defaultEncoding_SRL_1 2'b10 +`define ShiftCtrlEnum_defaultEncoding_SRA_1 2'b11 + +`define EnvCtrlEnum_defaultEncoding_type [1:0] +`define EnvCtrlEnum_defaultEncoding_NONE 2'b00 +`define EnvCtrlEnum_defaultEncoding_XRET 2'b01 +`define EnvCtrlEnum_defaultEncoding_ECALL 2'b10 +`define EnvCtrlEnum_defaultEncoding_EBREAK 2'b11 + +`define AluBitwiseCtrlEnum_defaultEncoding_type [1:0] +`define AluBitwiseCtrlEnum_defaultEncoding_XOR_1 2'b00 +`define AluBitwiseCtrlEnum_defaultEncoding_OR_1 2'b01 +`define AluBitwiseCtrlEnum_defaultEncoding_AND_1 2'b10 + +module InstructionCache ( + input io_flush, + input io_cpu_prefetch_isValid, + output reg io_cpu_prefetch_haltIt, + input [31:0] io_cpu_prefetch_pc, + input io_cpu_fetch_isValid, + input io_cpu_fetch_isStuck, + input io_cpu_fetch_isRemoved, + input [31:0] io_cpu_fetch_pc, + output [31:0] io_cpu_fetch_data, + input io_cpu_fetch_dataBypassValid, + input [31:0] io_cpu_fetch_dataBypass, + output io_cpu_fetch_mmuBus_cmd_isValid, + output [31:0] io_cpu_fetch_mmuBus_cmd_virtualAddress, + output io_cpu_fetch_mmuBus_cmd_bypassTranslation, + input [31:0] io_cpu_fetch_mmuBus_rsp_physicalAddress, + input io_cpu_fetch_mmuBus_rsp_isIoAccess, + input io_cpu_fetch_mmuBus_rsp_allowRead, + input io_cpu_fetch_mmuBus_rsp_allowWrite, + input io_cpu_fetch_mmuBus_rsp_allowExecute, + input io_cpu_fetch_mmuBus_rsp_exception, + input io_cpu_fetch_mmuBus_rsp_refilling, + output io_cpu_fetch_mmuBus_end, + input io_cpu_fetch_mmuBus_busy, + output [31:0] io_cpu_fetch_physicalAddress, + output io_cpu_fetch_cacheMiss, + output io_cpu_fetch_error, + output io_cpu_fetch_mmuRefilling, + output io_cpu_fetch_mmuException, + input io_cpu_fetch_isUser, + output io_cpu_fetch_haltIt, + input io_cpu_decode_isValid, + input io_cpu_decode_isStuck, + input [31:0] io_cpu_decode_pc, + output [31:0] io_cpu_decode_physicalAddress, + output [31:0] io_cpu_decode_data, + input io_cpu_fill_valid, + input [31:0] io_cpu_fill_payload, + output io_mem_cmd_valid, + input io_mem_cmd_ready, + output [31:0] io_mem_cmd_payload_address, + output [2:0] io_mem_cmd_payload_size, + input io_mem_rsp_valid, + input [31:0] io_mem_rsp_payload_data, + input io_mem_rsp_payload_error, + input clk, + input reset); + reg [23:0] _zz_10_; + reg [31:0] _zz_11_; + wire _zz_12_; + wire _zz_13_; + wire [0:0] _zz_14_; + wire [0:0] _zz_15_; + wire [23:0] _zz_16_; + reg _zz_1_; + reg _zz_2_; + reg lineLoader_fire; + reg lineLoader_valid; + reg [31:0] lineLoader_address; + reg lineLoader_hadError; + reg lineLoader_flushPending; + reg [5:0] lineLoader_flushCounter; + reg _zz_3_; + reg lineLoader_cmdSent; + reg lineLoader_wayToAllocate_willIncrement; + wire lineLoader_wayToAllocate_willClear; + wire lineLoader_wayToAllocate_willOverflowIfInc; + wire lineLoader_wayToAllocate_willOverflow; + reg [2:0] lineLoader_wordIndex; + wire lineLoader_write_tag_0_valid; + wire [4:0] lineLoader_write_tag_0_payload_address; + wire lineLoader_write_tag_0_payload_data_valid; + wire lineLoader_write_tag_0_payload_data_error; + wire [21:0] lineLoader_write_tag_0_payload_data_address; + wire lineLoader_write_data_0_valid; + wire [7:0] lineLoader_write_data_0_payload_address; + wire [31:0] lineLoader_write_data_0_payload_data; + wire _zz_4_; + wire [4:0] _zz_5_; + wire _zz_6_; + wire fetchStage_read_waysValues_0_tag_valid; + wire fetchStage_read_waysValues_0_tag_error; + wire [21:0] fetchStage_read_waysValues_0_tag_address; + wire [23:0] _zz_7_; + wire [7:0] _zz_8_; + wire _zz_9_; + wire [31:0] fetchStage_read_waysValues_0_data; + wire fetchStage_hit_hits_0; + wire fetchStage_hit_valid; + wire fetchStage_hit_error; + wire [31:0] fetchStage_hit_data; + wire [31:0] fetchStage_hit_word; + reg [23:0] ways_0_tags [0:31]; + reg [31:0] ways_0_datas [0:255]; + assign _zz_12_ = (! lineLoader_flushCounter[5]); + assign _zz_13_ = (lineLoader_flushPending && (! (lineLoader_valid || io_cpu_fetch_isValid))); + assign _zz_14_ = _zz_7_[0 : 0]; + assign _zz_15_ = _zz_7_[1 : 1]; + assign _zz_16_ = {lineLoader_write_tag_0_payload_data_address,{lineLoader_write_tag_0_payload_data_error,lineLoader_write_tag_0_payload_data_valid}}; + always @ (posedge clk) begin + if(_zz_2_) begin + ways_0_tags[lineLoader_write_tag_0_payload_address] <= _zz_16_; + end + end + + always @ (posedge clk) begin + if(_zz_6_) begin + _zz_10_ <= ways_0_tags[_zz_5_]; + end + end + + always @ (posedge clk) begin + if(_zz_1_) begin + ways_0_datas[lineLoader_write_data_0_payload_address] <= lineLoader_write_data_0_payload_data; + end + end + + always @ (posedge clk) begin + if(_zz_9_) begin + _zz_11_ <= ways_0_datas[_zz_8_]; + end + end + + always @ (*) begin + _zz_1_ = 1'b0; + if(lineLoader_write_data_0_valid)begin + _zz_1_ = 1'b1; + end + end + + always @ (*) begin + _zz_2_ = 1'b0; + if(lineLoader_write_tag_0_valid)begin + _zz_2_ = 1'b1; + end + end + + assign io_cpu_fetch_haltIt = io_cpu_fetch_mmuBus_busy; + always @ (*) begin + lineLoader_fire = 1'b0; + if(io_mem_rsp_valid)begin + if((lineLoader_wordIndex == (3'b111)))begin + lineLoader_fire = 1'b1; + end + end + end + + always @ (*) begin + io_cpu_prefetch_haltIt = (lineLoader_valid || lineLoader_flushPending); + if(_zz_12_)begin + io_cpu_prefetch_haltIt = 1'b1; + end + if((! _zz_3_))begin + io_cpu_prefetch_haltIt = 1'b1; + end + if(io_flush)begin + io_cpu_prefetch_haltIt = 1'b1; + end + end + + assign io_mem_cmd_valid = (lineLoader_valid && (! lineLoader_cmdSent)); + assign io_mem_cmd_payload_address = {lineLoader_address[31 : 5],(5'b00000)}; + assign io_mem_cmd_payload_size = (3'b101); + always @ (*) begin + lineLoader_wayToAllocate_willIncrement = 1'b0; + if(lineLoader_fire)begin + lineLoader_wayToAllocate_willIncrement = 1'b1; + end + end + + assign lineLoader_wayToAllocate_willClear = 1'b0; + assign lineLoader_wayToAllocate_willOverflowIfInc = 1'b1; + assign lineLoader_wayToAllocate_willOverflow = (lineLoader_wayToAllocate_willOverflowIfInc && lineLoader_wayToAllocate_willIncrement); + assign _zz_4_ = 1'b1; + assign lineLoader_write_tag_0_valid = ((_zz_4_ && lineLoader_fire) || (! lineLoader_flushCounter[5])); + assign lineLoader_write_tag_0_payload_address = (lineLoader_flushCounter[5] ? lineLoader_address[9 : 5] : lineLoader_flushCounter[4 : 0]); + assign lineLoader_write_tag_0_payload_data_valid = lineLoader_flushCounter[5]; + assign lineLoader_write_tag_0_payload_data_error = (lineLoader_hadError || io_mem_rsp_payload_error); + assign lineLoader_write_tag_0_payload_data_address = lineLoader_address[31 : 10]; + assign lineLoader_write_data_0_valid = (io_mem_rsp_valid && _zz_4_); + assign lineLoader_write_data_0_payload_address = {lineLoader_address[9 : 5],lineLoader_wordIndex}; + assign lineLoader_write_data_0_payload_data = io_mem_rsp_payload_data; + assign _zz_5_ = io_cpu_prefetch_pc[9 : 5]; + assign _zz_6_ = (! io_cpu_fetch_isStuck); + assign _zz_7_ = _zz_10_; + assign fetchStage_read_waysValues_0_tag_valid = _zz_14_[0]; + assign fetchStage_read_waysValues_0_tag_error = _zz_15_[0]; + assign fetchStage_read_waysValues_0_tag_address = _zz_7_[23 : 2]; + assign _zz_8_ = io_cpu_prefetch_pc[9 : 2]; + assign _zz_9_ = (! io_cpu_fetch_isStuck); + assign fetchStage_read_waysValues_0_data = _zz_11_; + assign fetchStage_hit_hits_0 = (fetchStage_read_waysValues_0_tag_valid && (fetchStage_read_waysValues_0_tag_address == io_cpu_fetch_mmuBus_rsp_physicalAddress[31 : 10])); + assign fetchStage_hit_valid = (fetchStage_hit_hits_0 != (1'b0)); + assign fetchStage_hit_error = fetchStage_read_waysValues_0_tag_error; + assign fetchStage_hit_data = fetchStage_read_waysValues_0_data; + assign fetchStage_hit_word = fetchStage_hit_data[31 : 0]; + assign io_cpu_fetch_data = (io_cpu_fetch_dataBypassValid ? io_cpu_fetch_dataBypass : fetchStage_hit_word); + assign io_cpu_fetch_mmuBus_cmd_isValid = io_cpu_fetch_isValid; + assign io_cpu_fetch_mmuBus_cmd_virtualAddress = io_cpu_fetch_pc; + assign io_cpu_fetch_mmuBus_cmd_bypassTranslation = 1'b0; + assign io_cpu_fetch_mmuBus_end = ((! io_cpu_fetch_isStuck) || io_cpu_fetch_isRemoved); + assign io_cpu_fetch_physicalAddress = io_cpu_fetch_mmuBus_rsp_physicalAddress; + assign io_cpu_fetch_cacheMiss = (! fetchStage_hit_valid); + assign io_cpu_fetch_error = fetchStage_hit_error; + assign io_cpu_fetch_mmuRefilling = io_cpu_fetch_mmuBus_rsp_refilling; + assign io_cpu_fetch_mmuException = ((! io_cpu_fetch_mmuBus_rsp_refilling) && (io_cpu_fetch_mmuBus_rsp_exception || (! io_cpu_fetch_mmuBus_rsp_allowExecute))); + always @ (posedge clk) begin + if(reset) begin + lineLoader_valid <= 1'b0; + lineLoader_hadError <= 1'b0; + lineLoader_flushPending <= 1'b1; + lineLoader_cmdSent <= 1'b0; + lineLoader_wordIndex <= (3'b000); + end else begin + if(lineLoader_fire)begin + lineLoader_valid <= 1'b0; + end + if(lineLoader_fire)begin + lineLoader_hadError <= 1'b0; + end + if(io_cpu_fill_valid)begin + lineLoader_valid <= 1'b1; + end + if(io_flush)begin + lineLoader_flushPending <= 1'b1; + end + if(_zz_13_)begin + lineLoader_flushPending <= 1'b0; + end + if((io_mem_cmd_valid && io_mem_cmd_ready))begin + lineLoader_cmdSent <= 1'b1; + end + if(lineLoader_fire)begin + lineLoader_cmdSent <= 1'b0; + end + if(io_mem_rsp_valid)begin + lineLoader_wordIndex <= (lineLoader_wordIndex + (3'b001)); + if(io_mem_rsp_payload_error)begin + lineLoader_hadError <= 1'b1; + end + end + end + end + + always @ (posedge clk) begin + if(io_cpu_fill_valid)begin + lineLoader_address <= io_cpu_fill_payload; + end + if(_zz_12_)begin + lineLoader_flushCounter <= (lineLoader_flushCounter + (6'b000001)); + end + _zz_3_ <= lineLoader_flushCounter[5]; + if(_zz_13_)begin + lineLoader_flushCounter <= (6'b000000); + end + end + +endmodule + +module VexRiscv ( + input [31:0] externalResetVector, + input timerInterrupt, + input softwareInterrupt, + input [31:0] externalInterruptArray, + input debug_bus_cmd_valid, + output reg debug_bus_cmd_ready, + input debug_bus_cmd_payload_wr, + input [7:0] debug_bus_cmd_payload_address, + input [31:0] debug_bus_cmd_payload_data, + output reg [31:0] debug_bus_rsp_data, + output debug_resetOut, + output reg iBusWishbone_CYC, + output reg iBusWishbone_STB, + input iBusWishbone_ACK, + output iBusWishbone_WE, + output [29:0] iBusWishbone_ADR, + input [31:0] iBusWishbone_DAT_MISO, + output [31:0] iBusWishbone_DAT_MOSI, + output [3:0] iBusWishbone_SEL, + input iBusWishbone_ERR, + output [1:0] iBusWishbone_BTE, + output [2:0] iBusWishbone_CTI, + output dBusWishbone_CYC, + output dBusWishbone_STB, + input dBusWishbone_ACK, + output dBusWishbone_WE, + output [29:0] dBusWishbone_ADR, + input [31:0] dBusWishbone_DAT_MISO, + output [31:0] dBusWishbone_DAT_MOSI, + output reg [3:0] dBusWishbone_SEL, + input dBusWishbone_ERR, + output [1:0] dBusWishbone_BTE, + output [2:0] dBusWishbone_CTI, + input clk, + input reset, + input debugReset); + wire _zz_135_; + wire _zz_136_; + wire _zz_137_; + wire _zz_138_; + wire _zz_139_; + wire [31:0] _zz_140_; + wire _zz_141_; + wire _zz_142_; + wire _zz_143_; + wire _zz_144_; + wire _zz_145_; + wire _zz_146_; + wire _zz_147_; + wire _zz_148_; + wire _zz_149_; + wire _zz_150_; + wire [31:0] _zz_151_; + reg _zz_152_; + reg [31:0] _zz_153_; + reg [31:0] _zz_154_; + reg [31:0] _zz_155_; + reg [3:0] _zz_156_; + reg [31:0] _zz_157_; + wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt; + wire IBusCachedPlugin_cache_io_cpu_fetch_error; + wire IBusCachedPlugin_cache_io_cpu_fetch_mmuRefilling; + wire IBusCachedPlugin_cache_io_cpu_fetch_mmuException; + wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_data; + wire IBusCachedPlugin_cache_io_cpu_fetch_cacheMiss; + wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress; + wire IBusCachedPlugin_cache_io_cpu_fetch_haltIt; + wire IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_isValid; + wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_virtualAddress; + wire IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_bypassTranslation; + wire IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_end; + wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_data; + wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_physicalAddress; + wire IBusCachedPlugin_cache_io_mem_cmd_valid; + wire [31:0] IBusCachedPlugin_cache_io_mem_cmd_payload_address; + wire [2:0] IBusCachedPlugin_cache_io_mem_cmd_payload_size; + wire _zz_158_; + wire _zz_159_; + wire _zz_160_; + wire _zz_161_; + wire _zz_162_; + wire _zz_163_; + wire [1:0] _zz_164_; + wire _zz_165_; + wire _zz_166_; + wire _zz_167_; + wire _zz_168_; + wire [5:0] _zz_169_; + wire _zz_170_; + wire _zz_171_; + wire [1:0] _zz_172_; + wire _zz_173_; + wire [2:0] _zz_174_; + wire [2:0] _zz_175_; + wire [31:0] _zz_176_; + wire [2:0] _zz_177_; + wire [0:0] _zz_178_; + wire [0:0] _zz_179_; + wire [0:0] _zz_180_; + wire [0:0] _zz_181_; + wire [0:0] _zz_182_; + wire [0:0] _zz_183_; + wire [0:0] _zz_184_; + wire [0:0] _zz_185_; + wire [0:0] _zz_186_; + wire [0:0] _zz_187_; + wire [2:0] _zz_188_; + wire [4:0] _zz_189_; + wire [11:0] _zz_190_; + wire [11:0] _zz_191_; + wire [31:0] _zz_192_; + wire [31:0] _zz_193_; + wire [31:0] _zz_194_; + wire [31:0] _zz_195_; + wire [31:0] _zz_196_; + wire [31:0] _zz_197_; + wire [31:0] _zz_198_; + wire [31:0] _zz_199_; + wire [32:0] _zz_200_; + wire [19:0] _zz_201_; + wire [11:0] _zz_202_; + wire [11:0] _zz_203_; + wire [1:0] _zz_204_; + wire [1:0] _zz_205_; + wire [2:0] _zz_206_; + wire [0:0] _zz_207_; + wire [0:0] _zz_208_; + wire [0:0] _zz_209_; + wire [0:0] _zz_210_; + wire [30:0] _zz_211_; + wire [30:0] _zz_212_; + wire [30:0] _zz_213_; + wire [30:0] _zz_214_; + wire [0:0] _zz_215_; + wire [0:0] _zz_216_; + wire [0:0] _zz_217_; + wire [0:0] _zz_218_; + wire [0:0] _zz_219_; + wire [0:0] _zz_220_; + wire [26:0] _zz_221_; + wire [6:0] _zz_222_; + wire [1:0] _zz_223_; + wire [31:0] _zz_224_; + wire [31:0] _zz_225_; + wire [31:0] _zz_226_; + wire [31:0] _zz_227_; + wire _zz_228_; + wire [5:0] _zz_229_; + wire [5:0] _zz_230_; + wire _zz_231_; + wire [0:0] _zz_232_; + wire [21:0] _zz_233_; + wire [31:0] _zz_234_; + wire [31:0] _zz_235_; + wire _zz_236_; + wire [0:0] _zz_237_; + wire [1:0] _zz_238_; + wire [31:0] _zz_239_; + wire [31:0] _zz_240_; + wire [0:0] _zz_241_; + wire [0:0] _zz_242_; + wire [0:0] _zz_243_; + wire [0:0] _zz_244_; + wire _zz_245_; + wire [0:0] _zz_246_; + wire [17:0] _zz_247_; + wire [31:0] _zz_248_; + wire [31:0] _zz_249_; + wire [31:0] _zz_250_; + wire [31:0] _zz_251_; + wire [31:0] _zz_252_; + wire [31:0] _zz_253_; + wire [31:0] _zz_254_; + wire _zz_255_; + wire _zz_256_; + wire [0:0] _zz_257_; + wire [0:0] _zz_258_; + wire [0:0] _zz_259_; + wire [0:0] _zz_260_; + wire _zz_261_; + wire [0:0] _zz_262_; + wire [14:0] _zz_263_; + wire [31:0] _zz_264_; + wire [31:0] _zz_265_; + wire [31:0] _zz_266_; + wire [31:0] _zz_267_; + wire [31:0] _zz_268_; + wire [0:0] _zz_269_; + wire [0:0] _zz_270_; + wire [1:0] _zz_271_; + wire [1:0] _zz_272_; + wire _zz_273_; + wire [0:0] _zz_274_; + wire [11:0] _zz_275_; + wire [31:0] _zz_276_; + wire [31:0] _zz_277_; + wire [31:0] _zz_278_; + wire [31:0] _zz_279_; + wire [31:0] _zz_280_; + wire [0:0] _zz_281_; + wire [0:0] _zz_282_; + wire [0:0] _zz_283_; + wire [0:0] _zz_284_; + wire _zz_285_; + wire [0:0] _zz_286_; + wire [8:0] _zz_287_; + wire [31:0] _zz_288_; + wire [31:0] _zz_289_; + wire [31:0] _zz_290_; + wire _zz_291_; + wire _zz_292_; + wire [1:0] _zz_293_; + wire [1:0] _zz_294_; + wire _zz_295_; + wire [0:0] _zz_296_; + wire [5:0] _zz_297_; + wire [31:0] _zz_298_; + wire [31:0] _zz_299_; + wire [31:0] _zz_300_; + wire [31:0] _zz_301_; + wire [31:0] _zz_302_; + wire [31:0] _zz_303_; + wire _zz_304_; + wire [1:0] _zz_305_; + wire [1:0] _zz_306_; + wire _zz_307_; + wire [0:0] _zz_308_; + wire [2:0] _zz_309_; + wire [31:0] _zz_310_; + wire [31:0] _zz_311_; + wire _zz_312_; + wire [0:0] _zz_313_; + wire [1:0] _zz_314_; + wire [3:0] _zz_315_; + wire [3:0] _zz_316_; + wire _zz_317_; + wire _zz_318_; + wire [31:0] _zz_319_; + wire [31:0] _zz_320_; + wire [31:0] _zz_321_; + wire [31:0] _zz_322_; + wire [31:0] _zz_323_; + wire [31:0] _zz_324_; + wire [31:0] _zz_325_; + wire _zz_326_; + wire [0:0] _zz_327_; + wire [0:0] _zz_328_; + wire _zz_329_; + wire [31:0] _zz_330_; + wire [31:0] _zz_331_; + wire [31:0] _zz_332_; + wire [31:0] _zz_333_; + wire [31:0] _zz_334_; + wire _zz_335_; + wire [0:0] _zz_336_; + wire [12:0] _zz_337_; + wire [31:0] _zz_338_; + wire [31:0] _zz_339_; + wire [31:0] _zz_340_; + wire _zz_341_; + wire [0:0] _zz_342_; + wire [6:0] _zz_343_; + wire [31:0] _zz_344_; + wire [31:0] _zz_345_; + wire [31:0] _zz_346_; + wire _zz_347_; + wire [0:0] _zz_348_; + wire [0:0] _zz_349_; + wire `AluCtrlEnum_defaultEncoding_type decode_ALU_CTRL; + wire `AluCtrlEnum_defaultEncoding_type _zz_1_; + wire `AluCtrlEnum_defaultEncoding_type _zz_2_; + wire `AluCtrlEnum_defaultEncoding_type _zz_3_; + wire decode_DO_EBREAK; + wire execute_REGFILE_WRITE_VALID; + wire `Src2CtrlEnum_defaultEncoding_type decode_SRC2_CTRL; + wire `Src2CtrlEnum_defaultEncoding_type _zz_4_; + wire `Src2CtrlEnum_defaultEncoding_type _zz_5_; + wire `Src2CtrlEnum_defaultEncoding_type _zz_6_; + wire `Src1CtrlEnum_defaultEncoding_type decode_SRC1_CTRL; + wire `Src1CtrlEnum_defaultEncoding_type _zz_7_; + wire `Src1CtrlEnum_defaultEncoding_type _zz_8_; + wire `Src1CtrlEnum_defaultEncoding_type _zz_9_; + wire decode_SRC_LESS_UNSIGNED; + wire decode_CSR_WRITE_OPCODE; + wire decode_SRC2_FORCE_ZERO; + wire decode_IS_CSR; + wire `BranchCtrlEnum_defaultEncoding_type decode_BRANCH_CTRL; + wire `BranchCtrlEnum_defaultEncoding_type _zz_10_; + wire `BranchCtrlEnum_defaultEncoding_type _zz_11_; + wire `BranchCtrlEnum_defaultEncoding_type _zz_12_; + wire decode_MEMORY_STORE; + wire `ShiftCtrlEnum_defaultEncoding_type decode_SHIFT_CTRL; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_13_; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_14_; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_15_; + wire `EnvCtrlEnum_defaultEncoding_type decode_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_16_; + wire `EnvCtrlEnum_defaultEncoding_type _zz_17_; + wire `EnvCtrlEnum_defaultEncoding_type _zz_18_; + wire decode_MEMORY_ENABLE; + wire decode_CSR_READ_OPCODE; + wire `AluBitwiseCtrlEnum_defaultEncoding_type decode_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_19_; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_20_; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_21_; + wire [31:0] execute_FORMAL_PC_NEXT; + wire [31:0] decode_FORMAL_PC_NEXT; + wire execute_DO_EBREAK; + wire decode_IS_EBREAK; + wire _zz_22_; + wire execute_CSR_READ_OPCODE; + wire execute_CSR_WRITE_OPCODE; + wire execute_IS_CSR; + wire _zz_23_; + wire _zz_24_; + wire `EnvCtrlEnum_defaultEncoding_type execute_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_25_; + wire [31:0] execute_BRANCH_CALC; + wire execute_BRANCH_DO; + wire [31:0] _zz_26_; + wire [31:0] execute_PC; + wire [31:0] execute_RS1; + wire `BranchCtrlEnum_defaultEncoding_type execute_BRANCH_CTRL; + wire `BranchCtrlEnum_defaultEncoding_type _zz_27_; + wire _zz_28_; + wire `ShiftCtrlEnum_defaultEncoding_type execute_SHIFT_CTRL; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_29_; + wire _zz_30_; + wire [31:0] _zz_31_; + wire [31:0] _zz_32_; + wire execute_SRC_LESS_UNSIGNED; + wire execute_SRC2_FORCE_ZERO; + wire execute_SRC_USE_SUB_LESS; + wire `Src2CtrlEnum_defaultEncoding_type execute_SRC2_CTRL; + wire `Src2CtrlEnum_defaultEncoding_type _zz_33_; + wire [31:0] _zz_34_; + wire `Src1CtrlEnum_defaultEncoding_type execute_SRC1_CTRL; + wire `Src1CtrlEnum_defaultEncoding_type _zz_35_; + wire [31:0] _zz_36_; + wire decode_SRC_USE_SUB_LESS; + wire decode_SRC_ADD_ZERO; + wire _zz_37_; + wire [31:0] execute_SRC_ADD_SUB; + wire execute_SRC_LESS; + wire `AluCtrlEnum_defaultEncoding_type execute_ALU_CTRL; + wire `AluCtrlEnum_defaultEncoding_type _zz_38_; + wire [31:0] _zz_39_; + wire [31:0] execute_SRC2; + wire [31:0] execute_SRC1; + wire `AluBitwiseCtrlEnum_defaultEncoding_type execute_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_40_; + reg _zz_41_; + wire [31:0] _zz_42_; + wire [31:0] _zz_43_; + reg decode_REGFILE_WRITE_VALID; + wire decode_LEGAL_INSTRUCTION; + wire decode_INSTRUCTION_READY; + wire _zz_44_; + wire _zz_45_; + wire _zz_46_; + wire _zz_47_; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_48_; + wire _zz_49_; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_50_; + wire `Src1CtrlEnum_defaultEncoding_type _zz_51_; + wire _zz_52_; + wire _zz_53_; + wire `EnvCtrlEnum_defaultEncoding_type _zz_54_; + wire _zz_55_; + wire `AluCtrlEnum_defaultEncoding_type _zz_56_; + wire `Src2CtrlEnum_defaultEncoding_type _zz_57_; + wire _zz_58_; + wire `BranchCtrlEnum_defaultEncoding_type _zz_59_; + wire _zz_60_; + reg [31:0] _zz_61_; + wire [1:0] execute_MEMORY_ADDRESS_LOW; + wire [31:0] execute_MEMORY_READ_DATA; + wire [31:0] execute_REGFILE_WRITE_DATA; + wire [31:0] _zz_62_; + wire [31:0] execute_SRC_ADD; + wire [1:0] _zz_63_; + wire [31:0] execute_RS2; + wire [31:0] execute_INSTRUCTION; + wire execute_MEMORY_STORE; + wire execute_MEMORY_ENABLE; + wire execute_ALIGNEMENT_FAULT; + wire _zz_64_; + wire decode_FLUSH_ALL; + reg IBusCachedPlugin_rsp_issueDetected; + reg _zz_65_; + reg _zz_66_; + reg _zz_67_; + reg [31:0] _zz_68_; + wire [31:0] _zz_69_; + wire [31:0] _zz_70_; + wire [31:0] _zz_71_; + wire [31:0] decode_PC /* verilator public */ ; + reg [31:0] decode_INSTRUCTION /* verilator public */ ; + reg decode_arbitration_haltItself /* verilator public */ ; + reg decode_arbitration_haltByOther; + reg decode_arbitration_removeIt; + reg decode_arbitration_flushAll /* verilator public */ ; + reg decode_arbitration_isValid /* verilator public */ ; + wire decode_arbitration_isStuck; + wire decode_arbitration_isStuckByOthers; + wire decode_arbitration_isFlushed; + wire decode_arbitration_isMoving; + wire decode_arbitration_isFiring; + reg execute_arbitration_haltItself; + reg execute_arbitration_haltByOther; + reg execute_arbitration_removeIt; + reg execute_arbitration_flushAll; + reg execute_arbitration_isValid; + wire execute_arbitration_isStuck; + wire execute_arbitration_isStuckByOthers; + wire execute_arbitration_isFlushed; + wire execute_arbitration_isMoving; + wire execute_arbitration_isFiring; + reg IBusCachedPlugin_fetcherHalt; + reg IBusCachedPlugin_fetcherflushIt; + reg IBusCachedPlugin_incomingInstruction; + wire IBusCachedPlugin_pcValids_0; + wire IBusCachedPlugin_pcValids_1; + wire IBusCachedPlugin_redoBranch_valid; + wire [31:0] IBusCachedPlugin_redoBranch_payload; + reg IBusCachedPlugin_decodeExceptionPort_valid; + reg [3:0] IBusCachedPlugin_decodeExceptionPort_payload_code; + wire [31:0] IBusCachedPlugin_decodeExceptionPort_payload_badAddr; + reg DBusSimplePlugin_memoryExceptionPort_valid; + reg [3:0] DBusSimplePlugin_memoryExceptionPort_payload_code; + wire [31:0] DBusSimplePlugin_memoryExceptionPort_payload_badAddr; + wire decodeExceptionPort_valid; + wire [3:0] decodeExceptionPort_payload_code; + wire [31:0] decodeExceptionPort_payload_badAddr; + wire BranchPlugin_jumpInterface_valid; + wire [31:0] BranchPlugin_jumpInterface_payload; + reg BranchPlugin_branchExceptionPort_valid; + wire [3:0] BranchPlugin_branchExceptionPort_payload_code; + wire [31:0] BranchPlugin_branchExceptionPort_payload_badAddr; + reg CsrPlugin_jumpInterface_valid; + reg [31:0] CsrPlugin_jumpInterface_payload; + wire CsrPlugin_exceptionPendings_0; + wire CsrPlugin_exceptionPendings_1; + wire externalInterrupt; + wire contextSwitching; + reg [1:0] CsrPlugin_privilege; + reg CsrPlugin_forceMachineWire; + reg CsrPlugin_selfException_valid; + reg [3:0] CsrPlugin_selfException_payload_code; + wire [31:0] CsrPlugin_selfException_payload_badAddr; + reg CsrPlugin_allowInterrupts; + reg CsrPlugin_allowException; + reg IBusCachedPlugin_injectionPort_valid; + reg IBusCachedPlugin_injectionPort_ready; + wire [31:0] IBusCachedPlugin_injectionPort_payload; + wire IBusCachedPlugin_jump_pcLoad_valid; + wire [31:0] IBusCachedPlugin_jump_pcLoad_payload; + wire [2:0] _zz_72_; + wire [2:0] _zz_73_; + wire _zz_74_; + wire _zz_75_; + wire IBusCachedPlugin_fetchPc_preOutput_valid; + wire IBusCachedPlugin_fetchPc_preOutput_ready; + wire [31:0] IBusCachedPlugin_fetchPc_preOutput_payload; + wire _zz_76_; + wire IBusCachedPlugin_fetchPc_output_valid; + wire IBusCachedPlugin_fetchPc_output_ready; + wire [31:0] IBusCachedPlugin_fetchPc_output_payload; + reg [31:0] IBusCachedPlugin_fetchPc_pcReg /* verilator public */ ; + reg IBusCachedPlugin_fetchPc_inc; + reg IBusCachedPlugin_fetchPc_propagatePc; + reg [31:0] IBusCachedPlugin_fetchPc_pc; + reg IBusCachedPlugin_fetchPc_samplePcNext; + reg _zz_77_; + wire IBusCachedPlugin_iBusRsp_stages_0_input_valid; + wire IBusCachedPlugin_iBusRsp_stages_0_input_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_input_payload; + wire IBusCachedPlugin_iBusRsp_stages_0_output_valid; + wire IBusCachedPlugin_iBusRsp_stages_0_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_output_payload; + reg IBusCachedPlugin_iBusRsp_stages_0_halt; + wire IBusCachedPlugin_iBusRsp_stages_0_inputSample; + wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid; + wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload; + wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_valid; + wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_payload; + reg IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt; + wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_inputSample; + wire _zz_78_; + wire _zz_79_; + wire _zz_80_; + wire _zz_81_; + reg _zz_82_; + reg IBusCachedPlugin_iBusRsp_readyForError; + wire IBusCachedPlugin_iBusRsp_decodeInput_valid; + wire IBusCachedPlugin_iBusRsp_decodeInput_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_decodeInput_payload_pc; + wire IBusCachedPlugin_iBusRsp_decodeInput_payload_rsp_error; + wire [31:0] IBusCachedPlugin_iBusRsp_decodeInput_payload_rsp_inst; + wire IBusCachedPlugin_iBusRsp_decodeInput_payload_isRvc; + reg IBusCachedPlugin_injector_nextPcCalc_valids_0; + reg IBusCachedPlugin_injector_nextPcCalc_valids_1; + reg IBusCachedPlugin_injector_decodeRemoved; + wire iBus_cmd_valid; + wire iBus_cmd_ready; + reg [31:0] iBus_cmd_payload_address; + wire [2:0] iBus_cmd_payload_size; + wire iBus_rsp_valid; + wire [31:0] iBus_rsp_payload_data; + wire iBus_rsp_payload_error; + wire IBusCachedPlugin_s0_tightlyCoupledHit; + reg IBusCachedPlugin_s1_tightlyCoupledHit; + wire IBusCachedPlugin_rsp_iBusRspOutputHalt; + reg IBusCachedPlugin_rsp_redoFetch; + wire dBus_cmd_valid; + wire dBus_cmd_ready; + wire dBus_cmd_payload_wr; + wire [31:0] dBus_cmd_payload_address; + wire [31:0] dBus_cmd_payload_data; + wire [1:0] dBus_cmd_payload_size; + wire dBus_rsp_ready; + wire dBus_rsp_error; + wire [31:0] dBus_rsp_data; + reg execute_DBusSimplePlugin_cmdSent; + reg execute_DBusSimplePlugin_skipCmd; + reg [31:0] _zz_83_; + reg [3:0] _zz_84_; + wire [3:0] execute_DBusSimplePlugin_formalMask; + reg [31:0] execute_DBusSimplePlugin_rspShifted; + wire _zz_85_; + reg [31:0] _zz_86_; + wire _zz_87_; + reg [31:0] _zz_88_; + reg [31:0] execute_DBusSimplePlugin_rspFormated; + wire [27:0] _zz_89_; + wire _zz_90_; + wire _zz_91_; + wire _zz_92_; + wire _zz_93_; + wire _zz_94_; + wire `BranchCtrlEnum_defaultEncoding_type _zz_95_; + wire `Src2CtrlEnum_defaultEncoding_type _zz_96_; + wire `AluCtrlEnum_defaultEncoding_type _zz_97_; + wire `EnvCtrlEnum_defaultEncoding_type _zz_98_; + wire `Src1CtrlEnum_defaultEncoding_type _zz_99_; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_100_; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_101_; + wire [4:0] execute_RegFilePlugin_regFileReadAddress1; + wire [4:0] execute_RegFilePlugin_regFileReadAddress2; + wire _zz_102_; + wire [31:0] execute_RegFilePlugin_rs1Data; + wire [31:0] execute_RegFilePlugin_rs2Data; + wire execute_RegFilePlugin_regFileWrite_valid /* verilator public */ ; + wire [4:0] execute_RegFilePlugin_regFileWrite_payload_address /* verilator public */ ; + wire [31:0] execute_RegFilePlugin_regFileWrite_payload_data /* verilator public */ ; + reg [31:0] execute_IntAluPlugin_bitwise; + reg [31:0] _zz_103_; + reg [31:0] _zz_104_; + wire _zz_105_; + reg [19:0] _zz_106_; + wire _zz_107_; + reg [19:0] _zz_108_; + reg [31:0] _zz_109_; + reg [31:0] execute_SrcPlugin_addSub; + wire execute_SrcPlugin_less; + reg execute_LightShifterPlugin_isActive; + wire execute_LightShifterPlugin_isShift; + reg [4:0] execute_LightShifterPlugin_amplitudeReg; + wire [4:0] execute_LightShifterPlugin_amplitude; + reg [31:0] execute_LightShifterPlugin_shiftReg; + wire [31:0] execute_LightShifterPlugin_shiftInput; + wire execute_LightShifterPlugin_done; + reg [31:0] _zz_110_; + wire execute_BranchPlugin_eq; + wire [2:0] _zz_111_; + reg _zz_112_; + reg _zz_113_; + wire [31:0] execute_BranchPlugin_branch_src1; + wire _zz_114_; + reg [10:0] _zz_115_; + wire _zz_116_; + reg [19:0] _zz_117_; + wire _zz_118_; + reg [18:0] _zz_119_; + reg [31:0] _zz_120_; + wire [31:0] execute_BranchPlugin_branch_src2; + wire [31:0] execute_BranchPlugin_branchAdder; + wire [1:0] CsrPlugin_misa_base; + wire [25:0] CsrPlugin_misa_extensions; + reg [1:0] CsrPlugin_mtvec_mode; + reg [29:0] CsrPlugin_mtvec_base; + reg [31:0] CsrPlugin_mepc; + reg CsrPlugin_mstatus_MIE; + reg CsrPlugin_mstatus_MPIE; + reg [1:0] CsrPlugin_mstatus_MPP; + reg CsrPlugin_mip_MEIP; + reg CsrPlugin_mip_MTIP; + reg CsrPlugin_mip_MSIP; + reg CsrPlugin_mie_MEIE; + reg CsrPlugin_mie_MTIE; + reg CsrPlugin_mie_MSIE; + reg [31:0] CsrPlugin_mscratch; + reg CsrPlugin_mcause_interrupt; + reg [3:0] CsrPlugin_mcause_exceptionCode; + reg [31:0] CsrPlugin_mtval; + reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000; + reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; + reg [3:0] CsrPlugin_exceptionPortCtrl_exceptionContext_code; + reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; + wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped; + wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; + wire [1:0] _zz_121_; + wire _zz_122_; + wire [2:0] _zz_123_; + wire [2:0] _zz_124_; + wire _zz_125_; + wire _zz_126_; + wire [1:0] _zz_127_; + reg CsrPlugin_interrupt; + reg [3:0] CsrPlugin_interruptCode /* verilator public */ ; + reg [1:0] CsrPlugin_interruptTargetPrivilege; + wire CsrPlugin_exception; + wire CsrPlugin_lastStageWasWfi; + reg CsrPlugin_pipelineLiberator_done; + wire CsrPlugin_interruptJump /* verilator public */ ; + reg CsrPlugin_hadException; + reg [1:0] CsrPlugin_targetPrivilege; + reg [3:0] CsrPlugin_trapCause; + reg [1:0] CsrPlugin_xtvec_mode; + reg [29:0] CsrPlugin_xtvec_base; + wire execute_CsrPlugin_inWfi /* verilator public */ ; + wire execute_CsrPlugin_blockedBySideEffects; + reg execute_CsrPlugin_illegalAccess; + reg execute_CsrPlugin_illegalInstruction; + reg [31:0] execute_CsrPlugin_readData; + wire execute_CsrPlugin_writeInstruction; + wire execute_CsrPlugin_readInstruction; + wire execute_CsrPlugin_writeEnable; + wire execute_CsrPlugin_readEnable; + wire [31:0] execute_CsrPlugin_readToWriteData; + reg [31:0] execute_CsrPlugin_writeData; + wire [11:0] execute_CsrPlugin_csrAddress; + reg [31:0] _zz_128_; + reg [31:0] externalInterruptArray_regNext; + wire [31:0] _zz_129_; + reg DebugPlugin_firstCycle; + reg DebugPlugin_secondCycle; + reg DebugPlugin_resetIt; + reg DebugPlugin_haltIt; + reg DebugPlugin_stepIt; + reg DebugPlugin_isPipBusy; + reg DebugPlugin_godmode; + reg DebugPlugin_haltedByBreak; + reg DebugPlugin_hardwareBreakpoints_0_valid; + reg [30:0] DebugPlugin_hardwareBreakpoints_0_pc; + reg DebugPlugin_hardwareBreakpoints_1_valid; + reg [30:0] DebugPlugin_hardwareBreakpoints_1_pc; + reg DebugPlugin_hardwareBreakpoints_2_valid; + reg [30:0] DebugPlugin_hardwareBreakpoints_2_pc; + reg DebugPlugin_hardwareBreakpoints_3_valid; + reg [30:0] DebugPlugin_hardwareBreakpoints_3_pc; + reg [31:0] DebugPlugin_busReadDataReg; + reg _zz_130_; + reg DebugPlugin_resetIt_regNext; + reg [31:0] decode_to_execute_INSTRUCTION; + reg [31:0] decode_to_execute_PC; + reg [31:0] decode_to_execute_FORMAL_PC_NEXT; + reg `AluBitwiseCtrlEnum_defaultEncoding_type decode_to_execute_ALU_BITWISE_CTRL; + reg decode_to_execute_CSR_READ_OPCODE; + reg decode_to_execute_MEMORY_ENABLE; + reg `EnvCtrlEnum_defaultEncoding_type decode_to_execute_ENV_CTRL; + reg decode_to_execute_SRC_USE_SUB_LESS; + reg `ShiftCtrlEnum_defaultEncoding_type decode_to_execute_SHIFT_CTRL; + reg decode_to_execute_MEMORY_STORE; + reg `BranchCtrlEnum_defaultEncoding_type decode_to_execute_BRANCH_CTRL; + reg decode_to_execute_IS_CSR; + reg decode_to_execute_SRC2_FORCE_ZERO; + reg decode_to_execute_CSR_WRITE_OPCODE; + reg decode_to_execute_SRC_LESS_UNSIGNED; + reg `Src1CtrlEnum_defaultEncoding_type decode_to_execute_SRC1_CTRL; + reg `Src2CtrlEnum_defaultEncoding_type decode_to_execute_SRC2_CTRL; + reg decode_to_execute_REGFILE_WRITE_VALID; + reg decode_to_execute_DO_EBREAK; + reg `AluCtrlEnum_defaultEncoding_type decode_to_execute_ALU_CTRL; + reg [2:0] _zz_131_; + reg [31:0] IBusCachedPlugin_injectionPort_payload_regNext; + reg [2:0] _zz_132_; + reg _zz_133_; + reg [31:0] iBusWishbone_DAT_MISO_regNext; + wire dBus_cmd_halfPipe_valid; + wire dBus_cmd_halfPipe_ready; + wire dBus_cmd_halfPipe_payload_wr; + wire [31:0] dBus_cmd_halfPipe_payload_address; + wire [31:0] dBus_cmd_halfPipe_payload_data; + wire [1:0] dBus_cmd_halfPipe_payload_size; + reg dBus_cmd_halfPipe_regs_valid; + reg dBus_cmd_halfPipe_regs_ready; + reg dBus_cmd_halfPipe_regs_payload_wr; + reg [31:0] dBus_cmd_halfPipe_regs_payload_address; + reg [31:0] dBus_cmd_halfPipe_regs_payload_data; + reg [1:0] dBus_cmd_halfPipe_regs_payload_size; + reg [3:0] _zz_134_; + `ifndef SYNTHESIS + reg [63:0] decode_ALU_CTRL_string; + reg [63:0] _zz_1__string; + reg [63:0] _zz_2__string; + reg [63:0] _zz_3__string; + reg [23:0] decode_SRC2_CTRL_string; + reg [23:0] _zz_4__string; + reg [23:0] _zz_5__string; + reg [23:0] _zz_6__string; + reg [95:0] decode_SRC1_CTRL_string; + reg [95:0] _zz_7__string; + reg [95:0] _zz_8__string; + reg [95:0] _zz_9__string; + reg [31:0] decode_BRANCH_CTRL_string; + reg [31:0] _zz_10__string; + reg [31:0] _zz_11__string; + reg [31:0] _zz_12__string; + reg [71:0] decode_SHIFT_CTRL_string; + reg [71:0] _zz_13__string; + reg [71:0] _zz_14__string; + reg [71:0] _zz_15__string; + reg [47:0] decode_ENV_CTRL_string; + reg [47:0] _zz_16__string; + reg [47:0] _zz_17__string; + reg [47:0] _zz_18__string; + reg [39:0] decode_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_19__string; + reg [39:0] _zz_20__string; + reg [39:0] _zz_21__string; + reg [47:0] execute_ENV_CTRL_string; + reg [47:0] _zz_25__string; + reg [31:0] execute_BRANCH_CTRL_string; + reg [31:0] _zz_27__string; + reg [71:0] execute_SHIFT_CTRL_string; + reg [71:0] _zz_29__string; + reg [23:0] execute_SRC2_CTRL_string; + reg [23:0] _zz_33__string; + reg [95:0] execute_SRC1_CTRL_string; + reg [95:0] _zz_35__string; + reg [63:0] execute_ALU_CTRL_string; + reg [63:0] _zz_38__string; + reg [39:0] execute_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_40__string; + reg [71:0] _zz_48__string; + reg [39:0] _zz_50__string; + reg [95:0] _zz_51__string; + reg [47:0] _zz_54__string; + reg [63:0] _zz_56__string; + reg [23:0] _zz_57__string; + reg [31:0] _zz_59__string; + reg [31:0] _zz_95__string; + reg [23:0] _zz_96__string; + reg [63:0] _zz_97__string; + reg [47:0] _zz_98__string; + reg [95:0] _zz_99__string; + reg [39:0] _zz_100__string; + reg [71:0] _zz_101__string; + reg [39:0] decode_to_execute_ALU_BITWISE_CTRL_string; + reg [47:0] decode_to_execute_ENV_CTRL_string; + reg [71:0] decode_to_execute_SHIFT_CTRL_string; + reg [31:0] decode_to_execute_BRANCH_CTRL_string; + reg [95:0] decode_to_execute_SRC1_CTRL_string; + reg [23:0] decode_to_execute_SRC2_CTRL_string; + reg [63:0] decode_to_execute_ALU_CTRL_string; + `endif + + reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; + assign _zz_158_ = ((execute_arbitration_isValid && execute_LightShifterPlugin_isShift) && (execute_SRC2[4 : 0] != (5'b00000))); + assign _zz_159_ = (! execute_arbitration_isStuckByOthers); + assign _zz_160_ = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != (2'b00)); + assign _zz_161_ = ({CsrPlugin_selfException_valid,{BranchPlugin_branchExceptionPort_valid,DBusSimplePlugin_memoryExceptionPort_valid}} != (3'b000)); + assign _zz_162_ = (CsrPlugin_hadException || CsrPlugin_interruptJump); + assign _zz_163_ = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); + assign _zz_164_ = execute_INSTRUCTION[29 : 28]; + assign _zz_165_ = (execute_arbitration_isValid && execute_DO_EBREAK); + assign _zz_166_ = (1'b0 == 1'b0); + assign _zz_167_ = (DebugPlugin_stepIt && IBusCachedPlugin_incomingInstruction); + assign _zz_168_ = (IBusCachedPlugin_fetchPc_preOutput_valid && IBusCachedPlugin_fetchPc_preOutput_ready); + assign _zz_169_ = debug_bus_cmd_payload_address[7 : 2]; + assign _zz_170_ = (iBus_cmd_valid || (_zz_132_ != (3'b000))); + assign _zz_171_ = (! dBus_cmd_halfPipe_regs_valid); + assign _zz_172_ = execute_INSTRUCTION[13 : 12]; + assign _zz_173_ = execute_INSTRUCTION[13]; + assign _zz_174_ = (_zz_72_ - (3'b001)); + assign _zz_175_ = {IBusCachedPlugin_fetchPc_inc,(2'b00)}; + assign _zz_176_ = {29'd0, _zz_175_}; + assign _zz_177_ = (execute_MEMORY_STORE ? (3'b110) : (3'b100)); + assign _zz_178_ = _zz_89_[3 : 3]; + assign _zz_179_ = _zz_89_[9 : 9]; + assign _zz_180_ = _zz_89_[12 : 12]; + assign _zz_181_ = _zz_89_[13 : 13]; + assign _zz_182_ = _zz_89_[19 : 19]; + assign _zz_183_ = _zz_89_[23 : 23]; + assign _zz_184_ = _zz_89_[24 : 24]; + assign _zz_185_ = _zz_89_[25 : 25]; + assign _zz_186_ = _zz_89_[27 : 27]; + assign _zz_187_ = execute_SRC_LESS; + assign _zz_188_ = (3'b100); + assign _zz_189_ = execute_INSTRUCTION[19 : 15]; + assign _zz_190_ = execute_INSTRUCTION[31 : 20]; + assign _zz_191_ = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; + assign _zz_192_ = ($signed(_zz_193_) + $signed(_zz_196_)); + assign _zz_193_ = ($signed(_zz_194_) + $signed(_zz_195_)); + assign _zz_194_ = execute_SRC1; + assign _zz_195_ = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); + assign _zz_196_ = (execute_SRC_USE_SUB_LESS ? _zz_197_ : _zz_198_); + assign _zz_197_ = (32'b00000000000000000000000000000001); + assign _zz_198_ = (32'b00000000000000000000000000000000); + assign _zz_199_ = (_zz_200_ >>> 1); + assign _zz_200_ = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_LightShifterPlugin_shiftInput[31]),execute_LightShifterPlugin_shiftInput}; + assign _zz_201_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_202_ = execute_INSTRUCTION[31 : 20]; + assign _zz_203_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_204_ = (_zz_121_ & (~ _zz_205_)); + assign _zz_205_ = (_zz_121_ - (2'b01)); + assign _zz_206_ = (_zz_123_ - (3'b001)); + assign _zz_207_ = debug_bus_cmd_payload_data[0 : 0]; + assign _zz_208_ = debug_bus_cmd_payload_data[0 : 0]; + assign _zz_209_ = debug_bus_cmd_payload_data[0 : 0]; + assign _zz_210_ = debug_bus_cmd_payload_data[0 : 0]; + assign _zz_211_ = (decode_PC >>> 1); + assign _zz_212_ = (decode_PC >>> 1); + assign _zz_213_ = (decode_PC >>> 1); + assign _zz_214_ = (decode_PC >>> 1); + assign _zz_215_ = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_216_ = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_217_ = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_218_ = execute_CsrPlugin_writeData[11 : 11]; + assign _zz_219_ = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_220_ = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_221_ = (iBus_cmd_payload_address >>> 5); + assign _zz_222_ = ({3'd0,_zz_134_} <<< dBus_cmd_halfPipe_payload_address[1 : 0]); + assign _zz_223_ = {_zz_75_,_zz_74_}; + assign _zz_224_ = (decode_INSTRUCTION & (32'b00000000000000000001000001010000)); + assign _zz_225_ = (32'b00000000000000000001000001010000); + assign _zz_226_ = (decode_INSTRUCTION & (32'b00000000000000000010000001010000)); + assign _zz_227_ = (32'b00000000000000000010000001010000); + assign _zz_228_ = ((decode_INSTRUCTION & (32'b00000000000000000001000001001000)) == (32'b00000000000000000001000000001000)); + assign _zz_229_ = {_zz_90_,{(_zz_234_ == _zz_235_),{_zz_236_,{_zz_237_,_zz_238_}}}}; + assign _zz_230_ = (6'b000000); + assign _zz_231_ = (_zz_92_ != (1'b0)); + assign _zz_232_ = ((_zz_239_ == _zz_240_) != (1'b0)); + assign _zz_233_ = {({_zz_241_,_zz_242_} != (2'b00)),{(_zz_243_ != _zz_244_),{_zz_245_,{_zz_246_,_zz_247_}}}}; + assign _zz_234_ = (decode_INSTRUCTION & (32'b00000000000000000001000000010000)); + assign _zz_235_ = (32'b00000000000000000001000000010000); + assign _zz_236_ = ((decode_INSTRUCTION & (32'b00000000000000000010000000010000)) == (32'b00000000000000000010000000010000)); + assign _zz_237_ = _zz_94_; + assign _zz_238_ = {(_zz_248_ == _zz_249_),(_zz_250_ == _zz_251_)}; + assign _zz_239_ = (decode_INSTRUCTION & (32'b00000000000000000111000001010100)); + assign _zz_240_ = (32'b00000000000000000101000000010000); + assign _zz_241_ = ((decode_INSTRUCTION & _zz_252_) == (32'b01000000000000000001000000010000)); + assign _zz_242_ = ((decode_INSTRUCTION & _zz_253_) == (32'b00000000000000000001000000010000)); + assign _zz_243_ = ((decode_INSTRUCTION & _zz_254_) == (32'b00000000000000000000000000010000)); + assign _zz_244_ = (1'b0); + assign _zz_245_ = ({_zz_255_,_zz_256_} != (2'b00)); + assign _zz_246_ = ({_zz_257_,_zz_258_} != (2'b00)); + assign _zz_247_ = {(_zz_259_ != _zz_260_),{_zz_261_,{_zz_262_,_zz_263_}}}; + assign _zz_248_ = (decode_INSTRUCTION & (32'b00000000000000000000000000001100)); + assign _zz_249_ = (32'b00000000000000000000000000000100); + assign _zz_250_ = (decode_INSTRUCTION & (32'b00000000000000000000000000101000)); + assign _zz_251_ = (32'b00000000000000000000000000000000); + assign _zz_252_ = (32'b01000000000000000011000001010100); + assign _zz_253_ = (32'b00000000000000000111000001010100); + assign _zz_254_ = (32'b00000000000000000000000000010000); + assign _zz_255_ = ((decode_INSTRUCTION & (32'b00000000000000000010000000010000)) == (32'b00000000000000000010000000000000)); + assign _zz_256_ = ((decode_INSTRUCTION & (32'b00000000000000000101000000000000)) == (32'b00000000000000000001000000000000)); + assign _zz_257_ = ((decode_INSTRUCTION & _zz_264_) == (32'b00000000000000000000000000100000)); + assign _zz_258_ = ((decode_INSTRUCTION & _zz_265_) == (32'b00000000000000000000000000100000)); + assign _zz_259_ = ((decode_INSTRUCTION & _zz_266_) == (32'b00000000000000000001000000000000)); + assign _zz_260_ = (1'b0); + assign _zz_261_ = ((_zz_267_ == _zz_268_) != (1'b0)); + assign _zz_262_ = ({_zz_269_,_zz_270_} != (2'b00)); + assign _zz_263_ = {(_zz_271_ != _zz_272_),{_zz_273_,{_zz_274_,_zz_275_}}}; + assign _zz_264_ = (32'b00000000000000000000000000110100); + assign _zz_265_ = (32'b00000000000000000000000001100100); + assign _zz_266_ = (32'b00000000000000000001000000000000); + assign _zz_267_ = (decode_INSTRUCTION & (32'b00000000000000000011000000000000)); + assign _zz_268_ = (32'b00000000000000000010000000000000); + assign _zz_269_ = ((decode_INSTRUCTION & _zz_276_) == (32'b00000000000000000000000000000100)); + assign _zz_270_ = _zz_93_; + assign _zz_271_ = {(_zz_277_ == _zz_278_),_zz_93_}; + assign _zz_272_ = (2'b00); + assign _zz_273_ = ((_zz_279_ == _zz_280_) != (1'b0)); + assign _zz_274_ = ({_zz_281_,_zz_282_} != (2'b00)); + assign _zz_275_ = {(_zz_283_ != _zz_284_),{_zz_285_,{_zz_286_,_zz_287_}}}; + assign _zz_276_ = (32'b00000000000000000000000000010100); + assign _zz_277_ = (decode_INSTRUCTION & (32'b00000000000000000000000001000100)); + assign _zz_278_ = (32'b00000000000000000000000000000100); + assign _zz_279_ = (decode_INSTRUCTION & (32'b00000000000000000000000001011000)); + assign _zz_280_ = (32'b00000000000000000000000000000000); + assign _zz_281_ = ((decode_INSTRUCTION & _zz_288_) == (32'b00000000000000000000000000100100)); + assign _zz_282_ = ((decode_INSTRUCTION & _zz_289_) == (32'b00000000000000000001000000010000)); + assign _zz_283_ = ((decode_INSTRUCTION & _zz_290_) == (32'b00000000000000000000000001010000)); + assign _zz_284_ = (1'b0); + assign _zz_285_ = ({_zz_92_,_zz_291_} != (2'b00)); + assign _zz_286_ = (_zz_292_ != (1'b0)); + assign _zz_287_ = {(_zz_293_ != _zz_294_),{_zz_295_,{_zz_296_,_zz_297_}}}; + assign _zz_288_ = (32'b00000000000000000000000001100100); + assign _zz_289_ = (32'b00000000000000000011000001010100); + assign _zz_290_ = (32'b00010000000000000011000001010000); + assign _zz_291_ = ((decode_INSTRUCTION & (32'b00010000010000000011000001010000)) == (32'b00010000000000000000000001010000)); + assign _zz_292_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000100000)) == (32'b00000000000000000000000000100000)); + assign _zz_293_ = {(_zz_298_ == _zz_299_),(_zz_300_ == _zz_301_)}; + assign _zz_294_ = (2'b00); + assign _zz_295_ = ((_zz_302_ == _zz_303_) != (1'b0)); + assign _zz_296_ = (_zz_304_ != (1'b0)); + assign _zz_297_ = {(_zz_305_ != _zz_306_),{_zz_307_,{_zz_308_,_zz_309_}}}; + assign _zz_298_ = (decode_INSTRUCTION & (32'b00000000000000000110000000010100)); + assign _zz_299_ = (32'b00000000000000000110000000010000); + assign _zz_300_ = (decode_INSTRUCTION & (32'b00000000000000000101000000010100)); + assign _zz_301_ = (32'b00000000000000000100000000010000); + assign _zz_302_ = (decode_INSTRUCTION & (32'b00000000000000000110000000010100)); + assign _zz_303_ = (32'b00000000000000000010000000010000); + assign _zz_304_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000000000)) == (32'b00000000000000000000000000000000)); + assign _zz_305_ = {_zz_91_,(_zz_310_ == _zz_311_)}; + assign _zz_306_ = (2'b00); + assign _zz_307_ = ({_zz_91_,_zz_312_} != (2'b00)); + assign _zz_308_ = ({_zz_313_,_zz_314_} != (3'b000)); + assign _zz_309_ = {(_zz_315_ != _zz_316_),{_zz_317_,_zz_318_}}; + assign _zz_310_ = (decode_INSTRUCTION & (32'b00000000000000000000000001110000)); + assign _zz_311_ = (32'b00000000000000000000000000100000); + assign _zz_312_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000100000)) == (32'b00000000000000000000000000000000)); + assign _zz_313_ = ((decode_INSTRUCTION & _zz_319_) == (32'b00000000000000000000000001000000)); + assign _zz_314_ = {(_zz_320_ == _zz_321_),(_zz_322_ == _zz_323_)}; + assign _zz_315_ = {(_zz_324_ == _zz_325_),{_zz_326_,{_zz_327_,_zz_328_}}}; + assign _zz_316_ = (4'b0000); + assign _zz_317_ = ({_zz_90_,_zz_329_} != (2'b00)); + assign _zz_318_ = ((_zz_330_ == _zz_331_) != (1'b0)); + assign _zz_319_ = (32'b00000000000000000000000001000100); + assign _zz_320_ = (decode_INSTRUCTION & (32'b00000000000000000010000000010100)); + assign _zz_321_ = (32'b00000000000000000010000000010000); + assign _zz_322_ = (decode_INSTRUCTION & (32'b01000000000000000100000000110100)); + assign _zz_323_ = (32'b01000000000000000000000000110000); + assign _zz_324_ = (decode_INSTRUCTION & (32'b00000000000000000000000001000100)); + assign _zz_325_ = (32'b00000000000000000000000000000000); + assign _zz_326_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000011000)) == (32'b00000000000000000000000000000000)); + assign _zz_327_ = ((decode_INSTRUCTION & (32'b00000000000000000110000000000100)) == (32'b00000000000000000010000000000000)); + assign _zz_328_ = ((decode_INSTRUCTION & (32'b00000000000000000101000000000100)) == (32'b00000000000000000001000000000000)); + assign _zz_329_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000011100)) == (32'b00000000000000000000000000000100)); + assign _zz_330_ = (decode_INSTRUCTION & (32'b00000000000000000000000001011000)); + assign _zz_331_ = (32'b00000000000000000000000001000000); + assign _zz_332_ = (32'b00000000000000000001000001111111); + assign _zz_333_ = (decode_INSTRUCTION & (32'b00000000000000000010000001111111)); + assign _zz_334_ = (32'b00000000000000000010000001110011); + assign _zz_335_ = ((decode_INSTRUCTION & (32'b00000000000000000100000001111111)) == (32'b00000000000000000100000001100011)); + assign _zz_336_ = ((decode_INSTRUCTION & (32'b00000000000000000010000001111111)) == (32'b00000000000000000010000000010011)); + assign _zz_337_ = {((decode_INSTRUCTION & (32'b00000000000000000110000000111111)) == (32'b00000000000000000000000000100011)),{((decode_INSTRUCTION & (32'b00000000000000000010000001111111)) == (32'b00000000000000000000000000000011)),{((decode_INSTRUCTION & _zz_338_) == (32'b00000000000000000000000000000011)),{(_zz_339_ == _zz_340_),{_zz_341_,{_zz_342_,_zz_343_}}}}}}; + assign _zz_338_ = (32'b00000000000000000101000001011111); + assign _zz_339_ = (decode_INSTRUCTION & (32'b00000000000000000111000001111011)); + assign _zz_340_ = (32'b00000000000000000000000001100011); + assign _zz_341_ = ((decode_INSTRUCTION & (32'b00000000000000000110000001111111)) == (32'b00000000000000000000000000001111)); + assign _zz_342_ = ((decode_INSTRUCTION & (32'b11111110000000000000000001111111)) == (32'b00000000000000000000000000110011)); + assign _zz_343_ = {((decode_INSTRUCTION & (32'b10111100000000000111000001111111)) == (32'b00000000000000000101000000010011)),{((decode_INSTRUCTION & (32'b11111100000000000011000001111111)) == (32'b00000000000000000001000000010011)),{((decode_INSTRUCTION & _zz_344_) == (32'b00000000000000000101000000110011)),{(_zz_345_ == _zz_346_),{_zz_347_,{_zz_348_,_zz_349_}}}}}}; + assign _zz_344_ = (32'b10111110000000000111000001111111); + assign _zz_345_ = (decode_INSTRUCTION & (32'b10111110000000000111000001111111)); + assign _zz_346_ = (32'b00000000000000000000000000110011); + assign _zz_347_ = ((decode_INSTRUCTION & (32'b11011111111111111111111111111111)) == (32'b00010000001000000000000001110011)); + assign _zz_348_ = ((decode_INSTRUCTION & (32'b11111111111011111111111111111111)) == (32'b00000000000000000000000001110011)); + assign _zz_349_ = ((decode_INSTRUCTION & (32'b11111111111111111111111111111111)) == (32'b00010000010100000000000001110011)); + initial begin + $readmemb("2-stage-1024-cache-debug.v_toplevel_RegFilePlugin_regFile.bin",RegFilePlugin_regFile); + end + always @ (posedge clk) begin + if(_zz_41_) begin + RegFilePlugin_regFile[execute_RegFilePlugin_regFileWrite_payload_address] <= execute_RegFilePlugin_regFileWrite_payload_data; + end + end + + always @ (posedge clk) begin + if(_zz_102_) begin + _zz_153_ <= RegFilePlugin_regFile[execute_RegFilePlugin_regFileReadAddress1]; + end + end + + always @ (posedge clk) begin + if(_zz_102_) begin + _zz_154_ <= RegFilePlugin_regFile[execute_RegFilePlugin_regFileReadAddress2]; + end + end + + InstructionCache IBusCachedPlugin_cache ( + .io_flush(_zz_135_), + .io_cpu_prefetch_isValid(_zz_136_), + .io_cpu_prefetch_haltIt(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt), + .io_cpu_prefetch_pc(IBusCachedPlugin_iBusRsp_stages_0_input_payload), + .io_cpu_fetch_isValid(_zz_137_), + .io_cpu_fetch_isStuck(_zz_138_), + .io_cpu_fetch_isRemoved(_zz_139_), + .io_cpu_fetch_pc(IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload), + .io_cpu_fetch_data(IBusCachedPlugin_cache_io_cpu_fetch_data), + .io_cpu_fetch_dataBypassValid(IBusCachedPlugin_s1_tightlyCoupledHit), + .io_cpu_fetch_dataBypass(_zz_140_), + .io_cpu_fetch_mmuBus_cmd_isValid(IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_isValid), + .io_cpu_fetch_mmuBus_cmd_virtualAddress(IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_virtualAddress), + .io_cpu_fetch_mmuBus_cmd_bypassTranslation(IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_bypassTranslation), + .io_cpu_fetch_mmuBus_rsp_physicalAddress(IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_virtualAddress), + .io_cpu_fetch_mmuBus_rsp_isIoAccess(_zz_141_), + .io_cpu_fetch_mmuBus_rsp_allowRead(_zz_142_), + .io_cpu_fetch_mmuBus_rsp_allowWrite(_zz_143_), + .io_cpu_fetch_mmuBus_rsp_allowExecute(_zz_144_), + .io_cpu_fetch_mmuBus_rsp_exception(_zz_145_), + .io_cpu_fetch_mmuBus_rsp_refilling(_zz_146_), + .io_cpu_fetch_mmuBus_end(IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_end), + .io_cpu_fetch_mmuBus_busy(_zz_147_), + .io_cpu_fetch_physicalAddress(IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress), + .io_cpu_fetch_cacheMiss(IBusCachedPlugin_cache_io_cpu_fetch_cacheMiss), + .io_cpu_fetch_error(IBusCachedPlugin_cache_io_cpu_fetch_error), + .io_cpu_fetch_mmuRefilling(IBusCachedPlugin_cache_io_cpu_fetch_mmuRefilling), + .io_cpu_fetch_mmuException(IBusCachedPlugin_cache_io_cpu_fetch_mmuException), + .io_cpu_fetch_isUser(_zz_148_), + .io_cpu_fetch_haltIt(IBusCachedPlugin_cache_io_cpu_fetch_haltIt), + .io_cpu_decode_isValid(_zz_149_), + .io_cpu_decode_isStuck(_zz_150_), + .io_cpu_decode_pc(_zz_151_), + .io_cpu_decode_physicalAddress(IBusCachedPlugin_cache_io_cpu_decode_physicalAddress), + .io_cpu_decode_data(IBusCachedPlugin_cache_io_cpu_decode_data), + .io_cpu_fill_valid(_zz_152_), + .io_cpu_fill_payload(IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress), + .io_mem_cmd_valid(IBusCachedPlugin_cache_io_mem_cmd_valid), + .io_mem_cmd_ready(iBus_cmd_ready), + .io_mem_cmd_payload_address(IBusCachedPlugin_cache_io_mem_cmd_payload_address), + .io_mem_cmd_payload_size(IBusCachedPlugin_cache_io_mem_cmd_payload_size), + .io_mem_rsp_valid(iBus_rsp_valid), + .io_mem_rsp_payload_data(iBus_rsp_payload_data), + .io_mem_rsp_payload_error(iBus_rsp_payload_error), + .clk(clk), + .reset(reset) + ); + always @(*) begin + case(_zz_223_) + 2'b00 : begin + _zz_155_ = BranchPlugin_jumpInterface_payload; + end + 2'b01 : begin + _zz_155_ = CsrPlugin_jumpInterface_payload; + end + default : begin + _zz_155_ = IBusCachedPlugin_redoBranch_payload; + end + endcase + end + + always @(*) begin + case(_zz_127_) + 2'b00 : begin + _zz_156_ = DBusSimplePlugin_memoryExceptionPort_payload_code; + _zz_157_ = DBusSimplePlugin_memoryExceptionPort_payload_badAddr; + end + 2'b01 : begin + _zz_156_ = BranchPlugin_branchExceptionPort_payload_code; + _zz_157_ = BranchPlugin_branchExceptionPort_payload_badAddr; + end + default : begin + _zz_156_ = CsrPlugin_selfException_payload_code; + _zz_157_ = CsrPlugin_selfException_payload_badAddr; + end + endcase + end + + `ifndef SYNTHESIS + always @(*) begin + case(decode_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : decode_ALU_CTRL_string = "BITWISE "; + default : decode_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(_zz_1_) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_1__string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_1__string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_1__string = "BITWISE "; + default : _zz_1__string = "????????"; + endcase + end + always @(*) begin + case(_zz_2_) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_2__string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_2__string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_2__string = "BITWISE "; + default : _zz_2__string = "????????"; + endcase + end + always @(*) begin + case(_zz_3_) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_3__string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_3__string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_3__string = "BITWISE "; + default : _zz_3__string = "????????"; + endcase + end + always @(*) begin + case(decode_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : decode_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : decode_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : decode_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : decode_SRC2_CTRL_string = "PC "; + default : decode_SRC2_CTRL_string = "???"; + endcase + end + always @(*) begin + case(_zz_4_) + `Src2CtrlEnum_defaultEncoding_RS : _zz_4__string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_4__string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_4__string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_4__string = "PC "; + default : _zz_4__string = "???"; + endcase + end + always @(*) begin + case(_zz_5_) + `Src2CtrlEnum_defaultEncoding_RS : _zz_5__string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_5__string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_5__string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_5__string = "PC "; + default : _zz_5__string = "???"; + endcase + end + always @(*) begin + case(_zz_6_) + `Src2CtrlEnum_defaultEncoding_RS : _zz_6__string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_6__string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_6__string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_6__string = "PC "; + default : _zz_6__string = "???"; + endcase + end + always @(*) begin + case(decode_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : decode_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : decode_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : decode_SRC1_CTRL_string = "URS1 "; + default : decode_SRC1_CTRL_string = "????????????"; + endcase + end + always @(*) begin + case(_zz_7_) + `Src1CtrlEnum_defaultEncoding_RS : _zz_7__string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_7__string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_7__string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_7__string = "URS1 "; + default : _zz_7__string = "????????????"; + endcase + end + always @(*) begin + case(_zz_8_) + `Src1CtrlEnum_defaultEncoding_RS : _zz_8__string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_8__string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_8__string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_8__string = "URS1 "; + default : _zz_8__string = "????????????"; + endcase + end + always @(*) begin + case(_zz_9_) + `Src1CtrlEnum_defaultEncoding_RS : _zz_9__string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_9__string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_9__string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_9__string = "URS1 "; + default : _zz_9__string = "????????????"; + endcase + end + always @(*) begin + case(decode_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : decode_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : decode_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : decode_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : decode_BRANCH_CTRL_string = "JALR"; + default : decode_BRANCH_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_10_) + `BranchCtrlEnum_defaultEncoding_INC : _zz_10__string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_10__string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_10__string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_10__string = "JALR"; + default : _zz_10__string = "????"; + endcase + end + always @(*) begin + case(_zz_11_) + `BranchCtrlEnum_defaultEncoding_INC : _zz_11__string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_11__string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_11__string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_11__string = "JALR"; + default : _zz_11__string = "????"; + endcase + end + always @(*) begin + case(_zz_12_) + `BranchCtrlEnum_defaultEncoding_INC : _zz_12__string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_12__string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_12__string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_12__string = "JALR"; + default : _zz_12__string = "????"; + endcase + end + always @(*) begin + case(decode_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 "; + default : decode_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_13_) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_13__string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_13__string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_13__string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_13__string = "SRA_1 "; + default : _zz_13__string = "?????????"; + endcase + end + always @(*) begin + case(_zz_14_) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_14__string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_14__string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_14__string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_14__string = "SRA_1 "; + default : _zz_14__string = "?????????"; + endcase + end + always @(*) begin + case(_zz_15_) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_15__string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_15__string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_15__string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_15__string = "SRA_1 "; + default : _zz_15__string = "?????????"; + endcase + end + always @(*) begin + case(decode_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : decode_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : decode_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : decode_ENV_CTRL_string = "ECALL "; + `EnvCtrlEnum_defaultEncoding_EBREAK : decode_ENV_CTRL_string = "EBREAK"; + default : decode_ENV_CTRL_string = "??????"; + endcase + end + always @(*) begin + case(_zz_16_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_16__string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_16__string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_16__string = "ECALL "; + `EnvCtrlEnum_defaultEncoding_EBREAK : _zz_16__string = "EBREAK"; + default : _zz_16__string = "??????"; + endcase + end + always @(*) begin + case(_zz_17_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_17__string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_17__string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_17__string = "ECALL "; + `EnvCtrlEnum_defaultEncoding_EBREAK : _zz_17__string = "EBREAK"; + default : _zz_17__string = "??????"; + endcase + end + always @(*) begin + case(_zz_18_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_18__string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_18__string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_18__string = "ECALL "; + `EnvCtrlEnum_defaultEncoding_EBREAK : _zz_18__string = "EBREAK"; + default : _zz_18__string = "??????"; + endcase + end + always @(*) begin + case(decode_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1"; + default : decode_ALU_BITWISE_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_19_) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_19__string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_19__string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_19__string = "AND_1"; + default : _zz_19__string = "?????"; + endcase + end + always @(*) begin + case(_zz_20_) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_20__string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_20__string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_20__string = "AND_1"; + default : _zz_20__string = "?????"; + endcase + end + always @(*) begin + case(_zz_21_) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_21__string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_21__string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_21__string = "AND_1"; + default : _zz_21__string = "?????"; + endcase + end + always @(*) begin + case(execute_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : execute_ENV_CTRL_string = "ECALL "; + `EnvCtrlEnum_defaultEncoding_EBREAK : execute_ENV_CTRL_string = "EBREAK"; + default : execute_ENV_CTRL_string = "??????"; + endcase + end + always @(*) begin + case(_zz_25_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_25__string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_25__string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_25__string = "ECALL "; + `EnvCtrlEnum_defaultEncoding_EBREAK : _zz_25__string = "EBREAK"; + default : _zz_25__string = "??????"; + endcase + end + always @(*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : execute_BRANCH_CTRL_string = "JALR"; + default : execute_BRANCH_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_27_) + `BranchCtrlEnum_defaultEncoding_INC : _zz_27__string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_27__string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_27__string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_27__string = "JALR"; + default : _zz_27__string = "????"; + endcase + end + always @(*) begin + case(execute_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : execute_SHIFT_CTRL_string = "SRA_1 "; + default : execute_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_29_) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_29__string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_29__string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_29__string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_29__string = "SRA_1 "; + default : _zz_29__string = "?????????"; + endcase + end + always @(*) begin + case(execute_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : execute_SRC2_CTRL_string = "PC "; + default : execute_SRC2_CTRL_string = "???"; + endcase + end + always @(*) begin + case(_zz_33_) + `Src2CtrlEnum_defaultEncoding_RS : _zz_33__string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_33__string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_33__string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_33__string = "PC "; + default : _zz_33__string = "???"; + endcase + end + always @(*) begin + case(execute_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : execute_SRC1_CTRL_string = "URS1 "; + default : execute_SRC1_CTRL_string = "????????????"; + endcase + end + always @(*) begin + case(_zz_35_) + `Src1CtrlEnum_defaultEncoding_RS : _zz_35__string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_35__string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_35__string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_35__string = "URS1 "; + default : _zz_35__string = "????????????"; + endcase + end + always @(*) begin + case(execute_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : execute_ALU_CTRL_string = "BITWISE "; + default : execute_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(_zz_38_) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_38__string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_38__string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_38__string = "BITWISE "; + default : _zz_38__string = "????????"; + endcase + end + always @(*) begin + case(execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : execute_ALU_BITWISE_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_40_) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_40__string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_40__string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_40__string = "AND_1"; + default : _zz_40__string = "?????"; + endcase + end + always @(*) begin + case(_zz_48_) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_48__string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_48__string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_48__string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_48__string = "SRA_1 "; + default : _zz_48__string = "?????????"; + endcase + end + always @(*) begin + case(_zz_50_) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_50__string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_50__string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_50__string = "AND_1"; + default : _zz_50__string = "?????"; + endcase + end + always @(*) begin + case(_zz_51_) + `Src1CtrlEnum_defaultEncoding_RS : _zz_51__string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_51__string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_51__string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_51__string = "URS1 "; + default : _zz_51__string = "????????????"; + endcase + end + always @(*) begin + case(_zz_54_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_54__string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_54__string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_54__string = "ECALL "; + `EnvCtrlEnum_defaultEncoding_EBREAK : _zz_54__string = "EBREAK"; + default : _zz_54__string = "??????"; + endcase + end + always @(*) begin + case(_zz_56_) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_56__string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_56__string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_56__string = "BITWISE "; + default : _zz_56__string = "????????"; + endcase + end + always @(*) begin + case(_zz_57_) + `Src2CtrlEnum_defaultEncoding_RS : _zz_57__string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_57__string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_57__string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_57__string = "PC "; + default : _zz_57__string = "???"; + endcase + end + always @(*) begin + case(_zz_59_) + `BranchCtrlEnum_defaultEncoding_INC : _zz_59__string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_59__string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_59__string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_59__string = "JALR"; + default : _zz_59__string = "????"; + endcase + end + always @(*) begin + case(_zz_95_) + `BranchCtrlEnum_defaultEncoding_INC : _zz_95__string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_95__string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_95__string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_95__string = "JALR"; + default : _zz_95__string = "????"; + endcase + end + always @(*) begin + case(_zz_96_) + `Src2CtrlEnum_defaultEncoding_RS : _zz_96__string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_96__string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_96__string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_96__string = "PC "; + default : _zz_96__string = "???"; + endcase + end + always @(*) begin + case(_zz_97_) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_97__string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_97__string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_97__string = "BITWISE "; + default : _zz_97__string = "????????"; + endcase + end + always @(*) begin + case(_zz_98_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_98__string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_98__string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_98__string = "ECALL "; + `EnvCtrlEnum_defaultEncoding_EBREAK : _zz_98__string = "EBREAK"; + default : _zz_98__string = "??????"; + endcase + end + always @(*) begin + case(_zz_99_) + `Src1CtrlEnum_defaultEncoding_RS : _zz_99__string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_99__string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_99__string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_99__string = "URS1 "; + default : _zz_99__string = "????????????"; + endcase + end + always @(*) begin + case(_zz_100_) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_100__string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_100__string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_100__string = "AND_1"; + default : _zz_100__string = "?????"; + endcase + end + always @(*) begin + case(_zz_101_) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_101__string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_101__string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_101__string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_101__string = "SRA_1 "; + default : _zz_101__string = "?????????"; + endcase + end + always @(*) begin + case(decode_to_execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : decode_to_execute_ALU_BITWISE_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(decode_to_execute_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : decode_to_execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : decode_to_execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : decode_to_execute_ENV_CTRL_string = "ECALL "; + `EnvCtrlEnum_defaultEncoding_EBREAK : decode_to_execute_ENV_CTRL_string = "EBREAK"; + default : decode_to_execute_ENV_CTRL_string = "??????"; + endcase + end + always @(*) begin + case(decode_to_execute_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; + default : decode_to_execute_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(decode_to_execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : decode_to_execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : decode_to_execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR"; + default : decode_to_execute_BRANCH_CTRL_string = "????"; + endcase + end + always @(*) begin + case(decode_to_execute_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : decode_to_execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : decode_to_execute_SRC1_CTRL_string = "URS1 "; + default : decode_to_execute_SRC1_CTRL_string = "????????????"; + endcase + end + always @(*) begin + case(decode_to_execute_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : decode_to_execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : decode_to_execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : decode_to_execute_SRC2_CTRL_string = "PC "; + default : decode_to_execute_SRC2_CTRL_string = "???"; + endcase + end + always @(*) begin + case(decode_to_execute_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE "; + default : decode_to_execute_ALU_CTRL_string = "????????"; + endcase + end + `endif + + assign decode_ALU_CTRL = _zz_1_; + assign _zz_2_ = _zz_3_; + assign decode_DO_EBREAK = _zz_22_; + assign execute_REGFILE_WRITE_VALID = decode_to_execute_REGFILE_WRITE_VALID; + assign decode_SRC2_CTRL = _zz_4_; + assign _zz_5_ = _zz_6_; + assign decode_SRC1_CTRL = _zz_7_; + assign _zz_8_ = _zz_9_; + assign decode_SRC_LESS_UNSIGNED = _zz_49_; + assign decode_CSR_WRITE_OPCODE = _zz_24_; + assign decode_SRC2_FORCE_ZERO = _zz_37_; + assign decode_IS_CSR = _zz_44_; + assign decode_BRANCH_CTRL = _zz_10_; + assign _zz_11_ = _zz_12_; + assign decode_MEMORY_STORE = _zz_55_; + assign decode_SHIFT_CTRL = _zz_13_; + assign _zz_14_ = _zz_15_; + assign decode_ENV_CTRL = _zz_16_; + assign _zz_17_ = _zz_18_; + assign decode_MEMORY_ENABLE = _zz_52_; + assign decode_CSR_READ_OPCODE = _zz_23_; + assign decode_ALU_BITWISE_CTRL = _zz_19_; + assign _zz_20_ = _zz_21_; + assign execute_FORMAL_PC_NEXT = decode_to_execute_FORMAL_PC_NEXT; + assign decode_FORMAL_PC_NEXT = _zz_69_; + assign execute_DO_EBREAK = decode_to_execute_DO_EBREAK; + assign decode_IS_EBREAK = _zz_47_; + assign execute_CSR_READ_OPCODE = decode_to_execute_CSR_READ_OPCODE; + assign execute_CSR_WRITE_OPCODE = decode_to_execute_CSR_WRITE_OPCODE; + assign execute_IS_CSR = decode_to_execute_IS_CSR; + assign execute_ENV_CTRL = _zz_25_; + assign execute_BRANCH_CALC = _zz_26_; + assign execute_BRANCH_DO = _zz_28_; + assign execute_PC = decode_to_execute_PC; + assign execute_RS1 = _zz_43_; + assign execute_BRANCH_CTRL = _zz_27_; + assign execute_SHIFT_CTRL = _zz_29_; + assign execute_SRC_LESS_UNSIGNED = decode_to_execute_SRC_LESS_UNSIGNED; + assign execute_SRC2_FORCE_ZERO = decode_to_execute_SRC2_FORCE_ZERO; + assign execute_SRC_USE_SUB_LESS = decode_to_execute_SRC_USE_SUB_LESS; + assign execute_SRC2_CTRL = _zz_33_; + assign execute_SRC1_CTRL = _zz_35_; + assign decode_SRC_USE_SUB_LESS = _zz_58_; + assign decode_SRC_ADD_ZERO = _zz_53_; + assign execute_SRC_ADD_SUB = _zz_32_; + assign execute_SRC_LESS = _zz_30_; + assign execute_ALU_CTRL = _zz_38_; + assign execute_SRC2 = _zz_34_; + assign execute_SRC1 = _zz_36_; + assign execute_ALU_BITWISE_CTRL = _zz_40_; + always @ (*) begin + _zz_41_ = 1'b0; + if(execute_RegFilePlugin_regFileWrite_valid)begin + _zz_41_ = 1'b1; + end + end + + always @ (*) begin + decode_REGFILE_WRITE_VALID = _zz_46_; + if((decode_INSTRUCTION[11 : 7] == (5'b00000)))begin + decode_REGFILE_WRITE_VALID = 1'b0; + end + end + + assign decode_LEGAL_INSTRUCTION = _zz_60_; + assign decode_INSTRUCTION_READY = 1'b1; + always @ (*) begin + _zz_61_ = execute_REGFILE_WRITE_DATA; + execute_arbitration_haltItself = 1'b0; + if(((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! dBus_cmd_ready)) && (! execute_DBusSimplePlugin_skipCmd)) && (! execute_DBusSimplePlugin_cmdSent)))begin + execute_arbitration_haltItself = 1'b1; + end + if((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! execute_MEMORY_STORE)) && (! dBus_rsp_ready)))begin + execute_arbitration_haltItself = 1'b1; + end + if((execute_arbitration_isValid && execute_MEMORY_ENABLE))begin + _zz_61_ = execute_DBusSimplePlugin_rspFormated; + end + if(_zz_158_)begin + _zz_61_ = _zz_110_; + if(_zz_159_)begin + if(! execute_LightShifterPlugin_done) begin + execute_arbitration_haltItself = 1'b1; + end + end + end + if((execute_arbitration_isValid && execute_IS_CSR))begin + _zz_61_ = execute_CsrPlugin_readData; + if(execute_CsrPlugin_blockedBySideEffects)begin + execute_arbitration_haltItself = 1'b1; + end + end + end + + assign execute_MEMORY_ADDRESS_LOW = _zz_63_; + assign execute_MEMORY_READ_DATA = _zz_62_; + assign execute_REGFILE_WRITE_DATA = _zz_39_; + assign execute_SRC_ADD = _zz_31_; + assign execute_RS2 = _zz_42_; + assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION; + assign execute_MEMORY_STORE = decode_to_execute_MEMORY_STORE; + assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE; + assign execute_ALIGNEMENT_FAULT = _zz_64_; + assign decode_FLUSH_ALL = _zz_45_; + always @ (*) begin + IBusCachedPlugin_rsp_issueDetected = _zz_65_; + _zz_66_ = _zz_67_; + IBusCachedPlugin_decodeExceptionPort_valid = 1'b0; + IBusCachedPlugin_decodeExceptionPort_payload_code = (4'bxxxx); + if(((_zz_137_ && IBusCachedPlugin_cache_io_cpu_fetch_mmuException) && (! _zz_67_)))begin + _zz_66_ = 1'b1; + IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; + IBusCachedPlugin_decodeExceptionPort_payload_code = (4'b1100); + end + if(((_zz_137_ && IBusCachedPlugin_cache_io_cpu_fetch_error) && (! _zz_65_)))begin + IBusCachedPlugin_rsp_issueDetected = 1'b1; + IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; + IBusCachedPlugin_decodeExceptionPort_payload_code = (4'b0001); + end + if(IBusCachedPlugin_fetcherHalt)begin + IBusCachedPlugin_decodeExceptionPort_valid = 1'b0; + end + end + + always @ (*) begin + _zz_65_ = _zz_66_; + _zz_67_ = 1'b0; + IBusCachedPlugin_rsp_redoFetch = 1'b0; + _zz_152_ = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_fetch_mmuRefilling)); + if(((_zz_137_ && IBusCachedPlugin_cache_io_cpu_fetch_mmuRefilling) && (! 1'b0)))begin + _zz_67_ = 1'b1; + IBusCachedPlugin_rsp_redoFetch = 1'b1; + end + if(((_zz_137_ && IBusCachedPlugin_cache_io_cpu_fetch_cacheMiss) && (! _zz_66_)))begin + _zz_65_ = 1'b1; + _zz_152_ = 1'b1; + IBusCachedPlugin_rsp_redoFetch = 1'b1; + end + if((! IBusCachedPlugin_iBusRsp_readyForError))begin + IBusCachedPlugin_rsp_redoFetch = 1'b0; + end + if((! IBusCachedPlugin_iBusRsp_readyForError))begin + _zz_152_ = 1'b0; + end + end + + always @ (*) begin + _zz_68_ = decode_FORMAL_PC_NEXT; + if(IBusCachedPlugin_redoBranch_valid)begin + _zz_68_ = IBusCachedPlugin_redoBranch_payload; + end + end + + assign decode_PC = _zz_71_; + always @ (*) begin + decode_INSTRUCTION = _zz_70_; + if((_zz_131_ != (3'b000)))begin + decode_INSTRUCTION = IBusCachedPlugin_injectionPort_payload_regNext; + end + end + + always @ (*) begin + decode_arbitration_haltItself = 1'b0; + decode_arbitration_isValid = (IBusCachedPlugin_iBusRsp_decodeInput_valid && (! IBusCachedPlugin_injector_decodeRemoved)); + IBusCachedPlugin_injectionPort_ready = 1'b0; + case(_zz_131_) + 3'b000 : begin + end + 3'b001 : begin + end + 3'b010 : begin + decode_arbitration_isValid = 1'b1; + decode_arbitration_haltItself = 1'b1; + end + 3'b011 : begin + decode_arbitration_isValid = 1'b1; + end + 3'b100 : begin + IBusCachedPlugin_injectionPort_ready = 1'b1; + end + default : begin + end + endcase + end + + always @ (*) begin + decode_arbitration_haltByOther = 1'b0; + if(CsrPlugin_interrupt)begin + decode_arbitration_haltByOther = decode_arbitration_isValid; + end + if(((execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)) != (1'b0)))begin + decode_arbitration_haltByOther = 1'b1; + end + end + + always @ (*) begin + decode_arbitration_removeIt = 1'b0; + if(_zz_160_)begin + decode_arbitration_removeIt = 1'b1; + end + if(decode_arbitration_isFlushed)begin + decode_arbitration_removeIt = 1'b1; + end + end + + always @ (*) begin + decode_arbitration_flushAll = 1'b0; + execute_arbitration_haltByOther = 1'b0; + execute_arbitration_removeIt = 1'b0; + IBusCachedPlugin_fetcherHalt = 1'b0; + IBusCachedPlugin_fetcherflushIt = 1'b0; + CsrPlugin_jumpInterface_valid = 1'b0; + CsrPlugin_jumpInterface_payload = (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx); + if(BranchPlugin_jumpInterface_valid)begin + decode_arbitration_flushAll = 1'b1; + end + CsrPlugin_exceptionPortCtrl_exceptionValids_execute = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; + if(_zz_161_)begin + decode_arbitration_flushAll = 1'b1; + execute_arbitration_removeIt = 1'b1; + CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b1; + end + if(execute_arbitration_isFlushed)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b0; + end + if(({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode} != (2'b00)))begin + IBusCachedPlugin_fetcherHalt = 1'b1; + end + if(_zz_162_)begin + IBusCachedPlugin_fetcherHalt = 1'b1; + CsrPlugin_jumpInterface_valid = 1'b1; + CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,(2'b00)}; + decode_arbitration_flushAll = 1'b1; + end + if(_zz_163_)begin + IBusCachedPlugin_fetcherHalt = 1'b1; + CsrPlugin_jumpInterface_valid = 1'b1; + decode_arbitration_flushAll = 1'b1; + case(_zz_164_) + 2'b11 : begin + CsrPlugin_jumpInterface_payload = CsrPlugin_mepc; + end + default : begin + end + endcase + end + if(_zz_165_)begin + execute_arbitration_haltByOther = 1'b1; + if(_zz_166_)begin + IBusCachedPlugin_fetcherflushIt = 1'b1; + IBusCachedPlugin_fetcherHalt = 1'b1; + end + end + if(DebugPlugin_haltIt)begin + IBusCachedPlugin_fetcherHalt = 1'b1; + end + if(_zz_167_)begin + IBusCachedPlugin_fetcherHalt = 1'b1; + end + if(execute_arbitration_isFlushed)begin + execute_arbitration_removeIt = 1'b1; + end + end + + always @ (*) begin + execute_arbitration_flushAll = 1'b0; + if(_zz_165_)begin + if(_zz_166_)begin + execute_arbitration_flushAll = 1'b1; + end + end + end + + always @ (*) begin + IBusCachedPlugin_incomingInstruction = 1'b0; + if(IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid)begin + IBusCachedPlugin_incomingInstruction = 1'b1; + end + end + + always @ (*) begin + CsrPlugin_forceMachineWire = 1'b0; + CsrPlugin_allowException = 1'b1; + if(DebugPlugin_godmode)begin + CsrPlugin_allowException = 1'b0; + CsrPlugin_forceMachineWire = 1'b1; + end + end + + always @ (*) begin + CsrPlugin_allowInterrupts = 1'b1; + if((DebugPlugin_haltIt || DebugPlugin_stepIt))begin + CsrPlugin_allowInterrupts = 1'b0; + end + end + + assign IBusCachedPlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,IBusCachedPlugin_redoBranch_valid}} != (3'b000)); + assign _zz_72_ = {IBusCachedPlugin_redoBranch_valid,{CsrPlugin_jumpInterface_valid,BranchPlugin_jumpInterface_valid}}; + assign _zz_73_ = (_zz_72_ & (~ _zz_174_)); + assign _zz_74_ = _zz_73_[1]; + assign _zz_75_ = _zz_73_[2]; + assign IBusCachedPlugin_jump_pcLoad_payload = _zz_155_; + assign _zz_76_ = (! IBusCachedPlugin_fetcherHalt); + assign IBusCachedPlugin_fetchPc_output_valid = (IBusCachedPlugin_fetchPc_preOutput_valid && _zz_76_); + assign IBusCachedPlugin_fetchPc_preOutput_ready = (IBusCachedPlugin_fetchPc_output_ready && _zz_76_); + assign IBusCachedPlugin_fetchPc_output_payload = IBusCachedPlugin_fetchPc_preOutput_payload; + always @ (*) begin + IBusCachedPlugin_fetchPc_propagatePc = 1'b0; + if((IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid && IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready))begin + IBusCachedPlugin_fetchPc_propagatePc = 1'b1; + end + end + + always @ (*) begin + IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_176_); + IBusCachedPlugin_fetchPc_samplePcNext = 1'b0; + if(IBusCachedPlugin_fetchPc_propagatePc)begin + IBusCachedPlugin_fetchPc_samplePcNext = 1'b1; + end + if(IBusCachedPlugin_jump_pcLoad_valid)begin + IBusCachedPlugin_fetchPc_samplePcNext = 1'b1; + IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_jump_pcLoad_payload; + end + if(_zz_168_)begin + IBusCachedPlugin_fetchPc_samplePcNext = 1'b1; + end + IBusCachedPlugin_fetchPc_pc[0] = 1'b0; + IBusCachedPlugin_fetchPc_pc[1] = 1'b0; + end + + assign IBusCachedPlugin_fetchPc_preOutput_valid = _zz_77_; + assign IBusCachedPlugin_fetchPc_preOutput_payload = IBusCachedPlugin_fetchPc_pc; + assign IBusCachedPlugin_iBusRsp_stages_0_input_valid = IBusCachedPlugin_fetchPc_output_valid; + assign IBusCachedPlugin_fetchPc_output_ready = IBusCachedPlugin_iBusRsp_stages_0_input_ready; + assign IBusCachedPlugin_iBusRsp_stages_0_input_payload = IBusCachedPlugin_fetchPc_output_payload; + assign IBusCachedPlugin_iBusRsp_stages_0_inputSample = 1'b1; + always @ (*) begin + IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b0; + if(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt)begin + IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b1; + end + end + + assign _zz_78_ = (! IBusCachedPlugin_iBusRsp_stages_0_halt); + assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_78_); + assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_78_); + assign IBusCachedPlugin_iBusRsp_stages_0_output_payload = IBusCachedPlugin_iBusRsp_stages_0_input_payload; + always @ (*) begin + IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt = 1'b0; + if(IBusCachedPlugin_cache_io_cpu_fetch_haltIt)begin + IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt = 1'b1; + end + if((IBusCachedPlugin_rsp_issueDetected || IBusCachedPlugin_rsp_iBusRspOutputHalt))begin + IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt = 1'b1; + end + end + + assign _zz_79_ = (! IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt); + assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready = (IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_ready && _zz_79_); + assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_valid = (IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid && _zz_79_); + assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_payload = IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload; + assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_80_; + assign _zz_80_ = ((1'b0 && (! _zz_81_)) || IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready); + assign _zz_81_ = _zz_82_; + assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid = _zz_81_; + assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload = IBusCachedPlugin_fetchPc_pcReg; + always @ (*) begin + IBusCachedPlugin_iBusRsp_readyForError = 1'b1; + if((! IBusCachedPlugin_pcValids_0))begin + IBusCachedPlugin_iBusRsp_readyForError = 1'b0; + end + end + + assign IBusCachedPlugin_pcValids_0 = IBusCachedPlugin_injector_nextPcCalc_valids_0; + assign IBusCachedPlugin_pcValids_1 = IBusCachedPlugin_injector_nextPcCalc_valids_1; + assign IBusCachedPlugin_iBusRsp_decodeInput_ready = (! decode_arbitration_isStuck); + assign _zz_71_ = IBusCachedPlugin_iBusRsp_decodeInput_payload_pc; + assign _zz_70_ = IBusCachedPlugin_iBusRsp_decodeInput_payload_rsp_inst; + assign _zz_69_ = (decode_PC + (32'b00000000000000000000000000000100)); + assign iBus_cmd_valid = IBusCachedPlugin_cache_io_mem_cmd_valid; + always @ (*) begin + iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; + iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; + end + + assign iBus_cmd_payload_size = IBusCachedPlugin_cache_io_mem_cmd_payload_size; + assign IBusCachedPlugin_s0_tightlyCoupledHit = 1'b0; + assign _zz_136_ = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); + assign _zz_139_ = (IBusCachedPlugin_jump_pcLoad_valid || IBusCachedPlugin_fetcherflushIt); + assign _zz_140_ = (32'b00000000000000000000000000000000); + assign _zz_137_ = (IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); + assign _zz_138_ = (! IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready); + assign _zz_148_ = (CsrPlugin_privilege == (2'b00)); + assign IBusCachedPlugin_rsp_iBusRspOutputHalt = 1'b0; + assign IBusCachedPlugin_decodeExceptionPort_payload_badAddr = {IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload[31 : 2],(2'b00)}; + assign IBusCachedPlugin_redoBranch_valid = IBusCachedPlugin_rsp_redoFetch; + assign IBusCachedPlugin_redoBranch_payload = IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload; + assign IBusCachedPlugin_iBusRsp_decodeInput_valid = IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_valid; + assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_ready = IBusCachedPlugin_iBusRsp_decodeInput_ready; + assign IBusCachedPlugin_iBusRsp_decodeInput_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_fetch_data; + assign IBusCachedPlugin_iBusRsp_decodeInput_payload_pc = IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_payload; + assign _zz_144_ = 1'b1; + assign _zz_142_ = 1'b1; + assign _zz_143_ = 1'b1; + assign _zz_141_ = 1'b0; + assign _zz_145_ = 1'b0; + assign _zz_146_ = 1'b0; + assign _zz_147_ = 1'b0; + assign _zz_135_ = (decode_arbitration_isValid && decode_FLUSH_ALL); + assign _zz_64_ = (((dBus_cmd_payload_size == (2'b10)) && (dBus_cmd_payload_address[1 : 0] != (2'b00))) || ((dBus_cmd_payload_size == (2'b01)) && (dBus_cmd_payload_address[0 : 0] != (1'b0)))); + always @ (*) begin + execute_DBusSimplePlugin_skipCmd = 1'b0; + if(execute_ALIGNEMENT_FAULT)begin + execute_DBusSimplePlugin_skipCmd = 1'b1; + end + end + + assign dBus_cmd_valid = (((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! execute_arbitration_isStuckByOthers)) && (! execute_arbitration_isFlushed)) && (! execute_DBusSimplePlugin_skipCmd)) && (! execute_DBusSimplePlugin_cmdSent)); + assign dBus_cmd_payload_wr = execute_MEMORY_STORE; + assign dBus_cmd_payload_size = execute_INSTRUCTION[13 : 12]; + always @ (*) begin + case(dBus_cmd_payload_size) + 2'b00 : begin + _zz_83_ = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; + end + 2'b01 : begin + _zz_83_ = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; + end + default : begin + _zz_83_ = execute_RS2[31 : 0]; + end + endcase + end + + assign dBus_cmd_payload_data = _zz_83_; + assign _zz_63_ = dBus_cmd_payload_address[1 : 0]; + always @ (*) begin + case(dBus_cmd_payload_size) + 2'b00 : begin + _zz_84_ = (4'b0001); + end + 2'b01 : begin + _zz_84_ = (4'b0011); + end + default : begin + _zz_84_ = (4'b1111); + end + endcase + end + + assign execute_DBusSimplePlugin_formalMask = (_zz_84_ <<< dBus_cmd_payload_address[1 : 0]); + assign dBus_cmd_payload_address = execute_SRC_ADD; + assign _zz_62_ = dBus_rsp_data; + always @ (*) begin + DBusSimplePlugin_memoryExceptionPort_valid = 1'b0; + DBusSimplePlugin_memoryExceptionPort_payload_code = (4'bxxxx); + if(execute_ALIGNEMENT_FAULT)begin + DBusSimplePlugin_memoryExceptionPort_payload_code = {1'd0, _zz_177_}; + DBusSimplePlugin_memoryExceptionPort_valid = 1'b1; + end + if((! ((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (1'b0 || (! execute_arbitration_isStuckByOthers)))))begin + DBusSimplePlugin_memoryExceptionPort_valid = 1'b0; + end + end + + assign DBusSimplePlugin_memoryExceptionPort_payload_badAddr = execute_REGFILE_WRITE_DATA; + always @ (*) begin + execute_DBusSimplePlugin_rspShifted = execute_MEMORY_READ_DATA; + case(execute_MEMORY_ADDRESS_LOW) + 2'b01 : begin + execute_DBusSimplePlugin_rspShifted[7 : 0] = execute_MEMORY_READ_DATA[15 : 8]; + end + 2'b10 : begin + execute_DBusSimplePlugin_rspShifted[15 : 0] = execute_MEMORY_READ_DATA[31 : 16]; + end + 2'b11 : begin + execute_DBusSimplePlugin_rspShifted[7 : 0] = execute_MEMORY_READ_DATA[31 : 24]; + end + default : begin + end + endcase + end + + assign _zz_85_ = (execute_DBusSimplePlugin_rspShifted[7] && (! execute_INSTRUCTION[14])); + always @ (*) begin + _zz_86_[31] = _zz_85_; + _zz_86_[30] = _zz_85_; + _zz_86_[29] = _zz_85_; + _zz_86_[28] = _zz_85_; + _zz_86_[27] = _zz_85_; + _zz_86_[26] = _zz_85_; + _zz_86_[25] = _zz_85_; + _zz_86_[24] = _zz_85_; + _zz_86_[23] = _zz_85_; + _zz_86_[22] = _zz_85_; + _zz_86_[21] = _zz_85_; + _zz_86_[20] = _zz_85_; + _zz_86_[19] = _zz_85_; + _zz_86_[18] = _zz_85_; + _zz_86_[17] = _zz_85_; + _zz_86_[16] = _zz_85_; + _zz_86_[15] = _zz_85_; + _zz_86_[14] = _zz_85_; + _zz_86_[13] = _zz_85_; + _zz_86_[12] = _zz_85_; + _zz_86_[11] = _zz_85_; + _zz_86_[10] = _zz_85_; + _zz_86_[9] = _zz_85_; + _zz_86_[8] = _zz_85_; + _zz_86_[7 : 0] = execute_DBusSimplePlugin_rspShifted[7 : 0]; + end + + assign _zz_87_ = (execute_DBusSimplePlugin_rspShifted[15] && (! execute_INSTRUCTION[14])); + always @ (*) begin + _zz_88_[31] = _zz_87_; + _zz_88_[30] = _zz_87_; + _zz_88_[29] = _zz_87_; + _zz_88_[28] = _zz_87_; + _zz_88_[27] = _zz_87_; + _zz_88_[26] = _zz_87_; + _zz_88_[25] = _zz_87_; + _zz_88_[24] = _zz_87_; + _zz_88_[23] = _zz_87_; + _zz_88_[22] = _zz_87_; + _zz_88_[21] = _zz_87_; + _zz_88_[20] = _zz_87_; + _zz_88_[19] = _zz_87_; + _zz_88_[18] = _zz_87_; + _zz_88_[17] = _zz_87_; + _zz_88_[16] = _zz_87_; + _zz_88_[15 : 0] = execute_DBusSimplePlugin_rspShifted[15 : 0]; + end + + always @ (*) begin + case(_zz_172_) + 2'b00 : begin + execute_DBusSimplePlugin_rspFormated = _zz_86_; + end + 2'b01 : begin + execute_DBusSimplePlugin_rspFormated = _zz_88_; + end + default : begin + execute_DBusSimplePlugin_rspFormated = execute_DBusSimplePlugin_rspShifted; + end + endcase + end + + assign _zz_90_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001001000)) == (32'b00000000000000000000000001001000)); + assign _zz_91_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000000100)) == (32'b00000000000000000000000000000100)); + assign _zz_92_ = ((decode_INSTRUCTION & (32'b00010000000100000011000001010000)) == (32'b00000000000100000000000001010000)); + assign _zz_93_ = ((decode_INSTRUCTION & (32'b00000000000000000100000001010000)) == (32'b00000000000000000100000001010000)); + assign _zz_94_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001010000)) == (32'b00000000000000000000000000010000)); + assign _zz_89_ = {({(_zz_224_ == _zz_225_),(_zz_226_ == _zz_227_)} != (2'b00)),{(_zz_94_ != (1'b0)),{(_zz_228_ != (1'b0)),{(_zz_229_ != _zz_230_),{_zz_231_,{_zz_232_,_zz_233_}}}}}}; + assign _zz_60_ = ({((decode_INSTRUCTION & (32'b00000000000000000000000001011111)) == (32'b00000000000000000000000000010111)),{((decode_INSTRUCTION & (32'b00000000000000000000000001111111)) == (32'b00000000000000000000000001101111)),{((decode_INSTRUCTION & (32'b00000000000000000001000001101111)) == (32'b00000000000000000000000000000011)),{((decode_INSTRUCTION & _zz_332_) == (32'b00000000000000000001000001110011)),{(_zz_333_ == _zz_334_),{_zz_335_,{_zz_336_,_zz_337_}}}}}}} != (20'b00000000000000000000)); + assign _zz_95_ = _zz_89_[1 : 0]; + assign _zz_59_ = _zz_95_; + assign _zz_58_ = _zz_178_[0]; + assign _zz_96_ = _zz_89_[5 : 4]; + assign _zz_57_ = _zz_96_; + assign _zz_97_ = _zz_89_[8 : 7]; + assign _zz_56_ = _zz_97_; + assign _zz_55_ = _zz_179_[0]; + assign _zz_98_ = _zz_89_[11 : 10]; + assign _zz_54_ = _zz_98_; + assign _zz_53_ = _zz_180_[0]; + assign _zz_52_ = _zz_181_[0]; + assign _zz_99_ = _zz_89_[15 : 14]; + assign _zz_51_ = _zz_99_; + assign _zz_100_ = _zz_89_[17 : 16]; + assign _zz_50_ = _zz_100_; + assign _zz_49_ = _zz_182_[0]; + assign _zz_101_ = _zz_89_[22 : 21]; + assign _zz_48_ = _zz_101_; + assign _zz_47_ = _zz_183_[0]; + assign _zz_46_ = _zz_184_[0]; + assign _zz_45_ = _zz_185_[0]; + assign _zz_44_ = _zz_186_[0]; + assign decodeExceptionPort_valid = ((decode_arbitration_isValid && decode_INSTRUCTION_READY) && (! decode_LEGAL_INSTRUCTION)); + assign decodeExceptionPort_payload_code = (4'b0010); + assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION; + assign execute_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION[19 : 15]; + assign execute_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION[24 : 20]; + assign _zz_102_ = (! execute_arbitration_isStuck); + assign execute_RegFilePlugin_rs1Data = _zz_153_; + assign execute_RegFilePlugin_rs2Data = _zz_154_; + assign _zz_43_ = execute_RegFilePlugin_rs1Data; + assign _zz_42_ = execute_RegFilePlugin_rs2Data; + assign execute_RegFilePlugin_regFileWrite_valid = (execute_REGFILE_WRITE_VALID && execute_arbitration_isFiring); + assign execute_RegFilePlugin_regFileWrite_payload_address = execute_INSTRUCTION[11 : 7]; + assign execute_RegFilePlugin_regFileWrite_payload_data = _zz_61_; + always @ (*) begin + case(execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : begin + execute_IntAluPlugin_bitwise = (execute_SRC1 & execute_SRC2); + end + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : begin + execute_IntAluPlugin_bitwise = (execute_SRC1 | execute_SRC2); + end + default : begin + execute_IntAluPlugin_bitwise = (execute_SRC1 ^ execute_SRC2); + end + endcase + end + + always @ (*) begin + case(execute_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_BITWISE : begin + _zz_103_ = execute_IntAluPlugin_bitwise; + end + `AluCtrlEnum_defaultEncoding_SLT_SLTU : begin + _zz_103_ = {31'd0, _zz_187_}; + end + default : begin + _zz_103_ = execute_SRC_ADD_SUB; + end + endcase + end + + assign _zz_39_ = _zz_103_; + assign _zz_37_ = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS)); + always @ (*) begin + case(execute_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : begin + _zz_104_ = execute_RS1; + end + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : begin + _zz_104_ = {29'd0, _zz_188_}; + end + `Src1CtrlEnum_defaultEncoding_IMU : begin + _zz_104_ = {execute_INSTRUCTION[31 : 12],(12'b000000000000)}; + end + default : begin + _zz_104_ = {27'd0, _zz_189_}; + end + endcase + end + + assign _zz_36_ = _zz_104_; + assign _zz_105_ = _zz_190_[11]; + always @ (*) begin + _zz_106_[19] = _zz_105_; + _zz_106_[18] = _zz_105_; + _zz_106_[17] = _zz_105_; + _zz_106_[16] = _zz_105_; + _zz_106_[15] = _zz_105_; + _zz_106_[14] = _zz_105_; + _zz_106_[13] = _zz_105_; + _zz_106_[12] = _zz_105_; + _zz_106_[11] = _zz_105_; + _zz_106_[10] = _zz_105_; + _zz_106_[9] = _zz_105_; + _zz_106_[8] = _zz_105_; + _zz_106_[7] = _zz_105_; + _zz_106_[6] = _zz_105_; + _zz_106_[5] = _zz_105_; + _zz_106_[4] = _zz_105_; + _zz_106_[3] = _zz_105_; + _zz_106_[2] = _zz_105_; + _zz_106_[1] = _zz_105_; + _zz_106_[0] = _zz_105_; + end + + assign _zz_107_ = _zz_191_[11]; + always @ (*) begin + _zz_108_[19] = _zz_107_; + _zz_108_[18] = _zz_107_; + _zz_108_[17] = _zz_107_; + _zz_108_[16] = _zz_107_; + _zz_108_[15] = _zz_107_; + _zz_108_[14] = _zz_107_; + _zz_108_[13] = _zz_107_; + _zz_108_[12] = _zz_107_; + _zz_108_[11] = _zz_107_; + _zz_108_[10] = _zz_107_; + _zz_108_[9] = _zz_107_; + _zz_108_[8] = _zz_107_; + _zz_108_[7] = _zz_107_; + _zz_108_[6] = _zz_107_; + _zz_108_[5] = _zz_107_; + _zz_108_[4] = _zz_107_; + _zz_108_[3] = _zz_107_; + _zz_108_[2] = _zz_107_; + _zz_108_[1] = _zz_107_; + _zz_108_[0] = _zz_107_; + end + + always @ (*) begin + case(execute_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : begin + _zz_109_ = execute_RS2; + end + `Src2CtrlEnum_defaultEncoding_IMI : begin + _zz_109_ = {_zz_106_,execute_INSTRUCTION[31 : 20]}; + end + `Src2CtrlEnum_defaultEncoding_IMS : begin + _zz_109_ = {_zz_108_,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; + end + default : begin + _zz_109_ = execute_PC; + end + endcase + end + + assign _zz_34_ = _zz_109_; + always @ (*) begin + execute_SrcPlugin_addSub = _zz_192_; + if(execute_SRC2_FORCE_ZERO)begin + execute_SrcPlugin_addSub = execute_SRC1; + end + end + + assign execute_SrcPlugin_less = ((execute_SRC1[31] == execute_SRC2[31]) ? execute_SrcPlugin_addSub[31] : (execute_SRC_LESS_UNSIGNED ? execute_SRC2[31] : execute_SRC1[31])); + assign _zz_32_ = execute_SrcPlugin_addSub; + assign _zz_31_ = execute_SrcPlugin_addSub; + assign _zz_30_ = execute_SrcPlugin_less; + assign execute_LightShifterPlugin_isShift = (execute_SHIFT_CTRL != `ShiftCtrlEnum_defaultEncoding_DISABLE_1); + assign execute_LightShifterPlugin_amplitude = (execute_LightShifterPlugin_isActive ? execute_LightShifterPlugin_amplitudeReg : execute_SRC2[4 : 0]); + assign execute_LightShifterPlugin_shiftInput = (execute_LightShifterPlugin_isActive ? execute_LightShifterPlugin_shiftReg : execute_SRC1); + assign execute_LightShifterPlugin_done = (execute_LightShifterPlugin_amplitude[4 : 1] == (4'b0000)); + always @ (*) begin + case(execute_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_SLL_1 : begin + _zz_110_ = (execute_LightShifterPlugin_shiftInput <<< 1); + end + default : begin + _zz_110_ = _zz_199_; + end + endcase + end + + assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2); + assign _zz_111_ = execute_INSTRUCTION[14 : 12]; + always @ (*) begin + if((_zz_111_ == (3'b000))) begin + _zz_112_ = execute_BranchPlugin_eq; + end else if((_zz_111_ == (3'b001))) begin + _zz_112_ = (! execute_BranchPlugin_eq); + end else if((((_zz_111_ & (3'b101)) == (3'b101)))) begin + _zz_112_ = (! execute_SRC_LESS); + end else begin + _zz_112_ = execute_SRC_LESS; + end + end + + always @ (*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : begin + _zz_113_ = 1'b0; + end + `BranchCtrlEnum_defaultEncoding_JAL : begin + _zz_113_ = 1'b1; + end + `BranchCtrlEnum_defaultEncoding_JALR : begin + _zz_113_ = 1'b1; + end + default : begin + _zz_113_ = _zz_112_; + end + endcase + end + + assign _zz_28_ = _zz_113_; + assign execute_BranchPlugin_branch_src1 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JALR) ? execute_RS1 : execute_PC); + assign _zz_114_ = _zz_201_[19]; + always @ (*) begin + _zz_115_[10] = _zz_114_; + _zz_115_[9] = _zz_114_; + _zz_115_[8] = _zz_114_; + _zz_115_[7] = _zz_114_; + _zz_115_[6] = _zz_114_; + _zz_115_[5] = _zz_114_; + _zz_115_[4] = _zz_114_; + _zz_115_[3] = _zz_114_; + _zz_115_[2] = _zz_114_; + _zz_115_[1] = _zz_114_; + _zz_115_[0] = _zz_114_; + end + + assign _zz_116_ = _zz_202_[11]; + always @ (*) begin + _zz_117_[19] = _zz_116_; + _zz_117_[18] = _zz_116_; + _zz_117_[17] = _zz_116_; + _zz_117_[16] = _zz_116_; + _zz_117_[15] = _zz_116_; + _zz_117_[14] = _zz_116_; + _zz_117_[13] = _zz_116_; + _zz_117_[12] = _zz_116_; + _zz_117_[11] = _zz_116_; + _zz_117_[10] = _zz_116_; + _zz_117_[9] = _zz_116_; + _zz_117_[8] = _zz_116_; + _zz_117_[7] = _zz_116_; + _zz_117_[6] = _zz_116_; + _zz_117_[5] = _zz_116_; + _zz_117_[4] = _zz_116_; + _zz_117_[3] = _zz_116_; + _zz_117_[2] = _zz_116_; + _zz_117_[1] = _zz_116_; + _zz_117_[0] = _zz_116_; + end + + assign _zz_118_ = _zz_203_[11]; + always @ (*) begin + _zz_119_[18] = _zz_118_; + _zz_119_[17] = _zz_118_; + _zz_119_[16] = _zz_118_; + _zz_119_[15] = _zz_118_; + _zz_119_[14] = _zz_118_; + _zz_119_[13] = _zz_118_; + _zz_119_[12] = _zz_118_; + _zz_119_[11] = _zz_118_; + _zz_119_[10] = _zz_118_; + _zz_119_[9] = _zz_118_; + _zz_119_[8] = _zz_118_; + _zz_119_[7] = _zz_118_; + _zz_119_[6] = _zz_118_; + _zz_119_[5] = _zz_118_; + _zz_119_[4] = _zz_118_; + _zz_119_[3] = _zz_118_; + _zz_119_[2] = _zz_118_; + _zz_119_[1] = _zz_118_; + _zz_119_[0] = _zz_118_; + end + + always @ (*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_JAL : begin + _zz_120_ = {{_zz_115_,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; + end + `BranchCtrlEnum_defaultEncoding_JALR : begin + _zz_120_ = {_zz_117_,execute_INSTRUCTION[31 : 20]}; + end + default : begin + _zz_120_ = {{_zz_119_,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; + end + endcase + end + + assign execute_BranchPlugin_branch_src2 = _zz_120_; + assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2); + assign _zz_26_ = {execute_BranchPlugin_branchAdder[31 : 1],(1'b0)}; + assign BranchPlugin_jumpInterface_valid = ((execute_arbitration_isValid && (! execute_arbitration_isStuckByOthers)) && execute_BRANCH_DO); + assign BranchPlugin_jumpInterface_payload = execute_BRANCH_CALC; + always @ (*) begin + BranchPlugin_branchExceptionPort_valid = ((execute_arbitration_isValid && execute_BRANCH_DO) && BranchPlugin_jumpInterface_payload[1]); + if(1'b0)begin + BranchPlugin_branchExceptionPort_valid = 1'b0; + end + end + + assign BranchPlugin_branchExceptionPort_payload_code = (4'b0000); + assign BranchPlugin_branchExceptionPort_payload_badAddr = BranchPlugin_jumpInterface_payload; + always @ (*) begin + CsrPlugin_privilege = (2'b11); + if(CsrPlugin_forceMachineWire)begin + CsrPlugin_privilege = (2'b11); + end + end + + assign CsrPlugin_misa_base = (2'b01); + assign CsrPlugin_misa_extensions = (26'b00000000000000000000000000); + assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = (2'b11); + assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege); + assign _zz_121_ = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; + assign _zz_122_ = _zz_204_[0]; + assign _zz_123_ = {CsrPlugin_selfException_valid,{BranchPlugin_branchExceptionPort_valid,DBusSimplePlugin_memoryExceptionPort_valid}}; + assign _zz_124_ = (_zz_123_ & (~ _zz_206_)); + assign _zz_125_ = _zz_124_[1]; + assign _zz_126_ = _zz_124_[2]; + assign _zz_127_ = {_zz_126_,_zz_125_}; + always @ (*) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; + if(_zz_160_)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b1; + end + if(decode_arbitration_isFlushed)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b0; + end + end + + assign CsrPlugin_exceptionPendings_0 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; + assign CsrPlugin_exceptionPendings_1 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; + always @ (*) begin + CsrPlugin_interrupt = 1'b0; + CsrPlugin_interruptCode = (4'bxxxx); + CsrPlugin_interruptTargetPrivilege = (2'bxx); + if((CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < (2'b11))))begin + if((((CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE) && 1'b1) && (! 1'b0)))begin + CsrPlugin_interrupt = 1'b1; + CsrPlugin_interruptCode = (4'b0111); + CsrPlugin_interruptTargetPrivilege = (2'b11); + end + if((((CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE) && 1'b1) && (! 1'b0)))begin + CsrPlugin_interrupt = 1'b1; + CsrPlugin_interruptCode = (4'b0011); + CsrPlugin_interruptTargetPrivilege = (2'b11); + end + if((((CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE) && 1'b1) && (! 1'b0)))begin + CsrPlugin_interrupt = 1'b1; + CsrPlugin_interruptCode = (4'b1011); + CsrPlugin_interruptTargetPrivilege = (2'b11); + end + end + if((! CsrPlugin_allowInterrupts))begin + CsrPlugin_interrupt = 1'b0; + end + end + + assign CsrPlugin_exception = (CsrPlugin_exceptionPortCtrl_exceptionValids_execute && CsrPlugin_allowException); + assign CsrPlugin_lastStageWasWfi = 1'b0; + always @ (*) begin + CsrPlugin_pipelineLiberator_done = ((! (execute_arbitration_isValid != (1'b0))) && IBusCachedPlugin_pcValids_1); + if((CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute != (1'b0)))begin + CsrPlugin_pipelineLiberator_done = 1'b0; + end + if(CsrPlugin_hadException)begin + CsrPlugin_pipelineLiberator_done = 1'b0; + end + end + + assign CsrPlugin_interruptJump = (CsrPlugin_interrupt && CsrPlugin_pipelineLiberator_done); + always @ (*) begin + CsrPlugin_targetPrivilege = CsrPlugin_interruptTargetPrivilege; + if(CsrPlugin_hadException)begin + CsrPlugin_targetPrivilege = CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; + end + end + + always @ (*) begin + CsrPlugin_trapCause = CsrPlugin_interruptCode; + if(CsrPlugin_hadException)begin + CsrPlugin_trapCause = CsrPlugin_exceptionPortCtrl_exceptionContext_code; + end + end + + always @ (*) begin + CsrPlugin_xtvec_mode = (2'bxx); + CsrPlugin_xtvec_base = (30'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx); + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_xtvec_mode = CsrPlugin_mtvec_mode; + CsrPlugin_xtvec_base = CsrPlugin_mtvec_base; + end + default : begin + end + endcase + end + + assign contextSwitching = CsrPlugin_jumpInterface_valid; + assign _zz_24_ = (! (((decode_INSTRUCTION[14 : 13] == (2'b01)) && (decode_INSTRUCTION[19 : 15] == (5'b00000))) || ((decode_INSTRUCTION[14 : 13] == (2'b11)) && (decode_INSTRUCTION[19 : 15] == (5'b00000))))); + assign _zz_23_ = (decode_INSTRUCTION[13 : 7] != (7'b0100000)); + assign execute_CsrPlugin_inWfi = 1'b0; + assign execute_CsrPlugin_blockedBySideEffects = 1'b0; + always @ (*) begin + execute_CsrPlugin_illegalAccess = 1'b1; + execute_CsrPlugin_readData = (32'b00000000000000000000000000000000); + case(execute_CsrPlugin_csrAddress) + 12'b101111000000 : begin + execute_CsrPlugin_illegalAccess = 1'b0; + execute_CsrPlugin_readData[31 : 0] = _zz_128_; + end + 12'b001100000000 : begin + execute_CsrPlugin_illegalAccess = 1'b0; + execute_CsrPlugin_readData[12 : 11] = CsrPlugin_mstatus_MPP; + execute_CsrPlugin_readData[7 : 7] = CsrPlugin_mstatus_MPIE; + execute_CsrPlugin_readData[3 : 3] = CsrPlugin_mstatus_MIE; + end + 12'b001101000001 : begin + execute_CsrPlugin_illegalAccess = 1'b0; + execute_CsrPlugin_readData[31 : 0] = CsrPlugin_mepc; + end + 12'b001100000101 : begin + if(execute_CSR_WRITE_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + 12'b001101000100 : begin + execute_CsrPlugin_illegalAccess = 1'b0; + execute_CsrPlugin_readData[11 : 11] = CsrPlugin_mip_MEIP; + execute_CsrPlugin_readData[7 : 7] = CsrPlugin_mip_MTIP; + execute_CsrPlugin_readData[3 : 3] = CsrPlugin_mip_MSIP; + end + 12'b001101000011 : begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + execute_CsrPlugin_readData[31 : 0] = CsrPlugin_mtval; + end + 12'b111111000000 : begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + execute_CsrPlugin_readData[31 : 0] = _zz_129_; + end + 12'b001101000000 : begin + execute_CsrPlugin_illegalAccess = 1'b0; + execute_CsrPlugin_readData[31 : 0] = CsrPlugin_mscratch; + end + 12'b001100000100 : begin + execute_CsrPlugin_illegalAccess = 1'b0; + execute_CsrPlugin_readData[11 : 11] = CsrPlugin_mie_MEIE; + execute_CsrPlugin_readData[7 : 7] = CsrPlugin_mie_MTIE; + execute_CsrPlugin_readData[3 : 3] = CsrPlugin_mie_MSIE; + end + 12'b001101000010 : begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + execute_CsrPlugin_readData[31 : 31] = CsrPlugin_mcause_interrupt; + execute_CsrPlugin_readData[3 : 0] = CsrPlugin_mcause_exceptionCode; + end + default : begin + end + endcase + if((CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]))begin + execute_CsrPlugin_illegalAccess = 1'b1; + end + if(((! execute_arbitration_isValid) || (! execute_IS_CSR)))begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + + always @ (*) begin + execute_CsrPlugin_illegalInstruction = 1'b0; + if((execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)))begin + if((CsrPlugin_privilege < execute_INSTRUCTION[29 : 28]))begin + execute_CsrPlugin_illegalInstruction = 1'b1; + end + end + end + + always @ (*) begin + CsrPlugin_selfException_valid = 1'b0; + CsrPlugin_selfException_payload_code = (4'bxxxx); + if((execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)))begin + CsrPlugin_selfException_valid = 1'b1; + case(CsrPlugin_privilege) + 2'b00 : begin + CsrPlugin_selfException_payload_code = (4'b1000); + end + default : begin + CsrPlugin_selfException_payload_code = (4'b1011); + end + endcase + end + if((execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_EBREAK)))begin + CsrPlugin_selfException_valid = 1'b1; + CsrPlugin_selfException_payload_code = (4'b0011); + end + end + + assign CsrPlugin_selfException_payload_badAddr = execute_INSTRUCTION; + assign execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); + assign execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); + assign execute_CsrPlugin_writeEnable = ((execute_CsrPlugin_writeInstruction && (! execute_CsrPlugin_blockedBySideEffects)) && (! execute_arbitration_isStuckByOthers)); + assign execute_CsrPlugin_readEnable = ((execute_CsrPlugin_readInstruction && (! execute_CsrPlugin_blockedBySideEffects)) && (! execute_arbitration_isStuckByOthers)); + assign execute_CsrPlugin_readToWriteData = execute_CsrPlugin_readData; + always @ (*) begin + case(_zz_173_) + 1'b0 : begin + execute_CsrPlugin_writeData = execute_SRC1; + end + default : begin + execute_CsrPlugin_writeData = (execute_INSTRUCTION[12] ? (execute_CsrPlugin_readToWriteData & (~ execute_SRC1)) : (execute_CsrPlugin_readToWriteData | execute_SRC1)); + end + endcase + end + + assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20]; + assign _zz_129_ = (_zz_128_ & externalInterruptArray_regNext); + assign externalInterrupt = (_zz_129_ != (32'b00000000000000000000000000000000)); + always @ (*) begin + debug_bus_cmd_ready = 1'b1; + IBusCachedPlugin_injectionPort_valid = 1'b0; + if(debug_bus_cmd_valid)begin + case(_zz_169_) + 6'b000000 : begin + end + 6'b000001 : begin + if(debug_bus_cmd_payload_wr)begin + IBusCachedPlugin_injectionPort_valid = 1'b1; + debug_bus_cmd_ready = IBusCachedPlugin_injectionPort_ready; + end + end + 6'b010000 : begin + end + 6'b010001 : begin + end + 6'b010010 : begin + end + 6'b010011 : begin + end + default : begin + end + endcase + end + end + + always @ (*) begin + debug_bus_rsp_data = DebugPlugin_busReadDataReg; + if((! _zz_130_))begin + debug_bus_rsp_data[0] = DebugPlugin_resetIt; + debug_bus_rsp_data[1] = DebugPlugin_haltIt; + debug_bus_rsp_data[2] = DebugPlugin_isPipBusy; + debug_bus_rsp_data[3] = DebugPlugin_haltedByBreak; + debug_bus_rsp_data[4] = DebugPlugin_stepIt; + end + end + + assign IBusCachedPlugin_injectionPort_payload = debug_bus_cmd_payload_data; + assign _zz_22_ = ((! DebugPlugin_haltIt) && (decode_IS_EBREAK || ((((1'b0 || (DebugPlugin_hardwareBreakpoints_0_valid && (DebugPlugin_hardwareBreakpoints_0_pc == _zz_211_))) || (DebugPlugin_hardwareBreakpoints_1_valid && (DebugPlugin_hardwareBreakpoints_1_pc == _zz_212_))) || (DebugPlugin_hardwareBreakpoints_2_valid && (DebugPlugin_hardwareBreakpoints_2_pc == _zz_213_))) || (DebugPlugin_hardwareBreakpoints_3_valid && (DebugPlugin_hardwareBreakpoints_3_pc == _zz_214_))))); + assign debug_resetOut = DebugPlugin_resetIt_regNext; + assign _zz_21_ = decode_ALU_BITWISE_CTRL; + assign _zz_19_ = _zz_50_; + assign _zz_40_ = decode_to_execute_ALU_BITWISE_CTRL; + assign _zz_18_ = decode_ENV_CTRL; + assign _zz_16_ = _zz_54_; + assign _zz_25_ = decode_to_execute_ENV_CTRL; + assign _zz_15_ = decode_SHIFT_CTRL; + assign _zz_13_ = _zz_48_; + assign _zz_29_ = decode_to_execute_SHIFT_CTRL; + assign _zz_12_ = decode_BRANCH_CTRL; + assign _zz_10_ = _zz_59_; + assign _zz_27_ = decode_to_execute_BRANCH_CTRL; + assign _zz_9_ = decode_SRC1_CTRL; + assign _zz_7_ = _zz_51_; + assign _zz_35_ = decode_to_execute_SRC1_CTRL; + assign _zz_6_ = decode_SRC2_CTRL; + assign _zz_4_ = _zz_57_; + assign _zz_33_ = decode_to_execute_SRC2_CTRL; + assign _zz_3_ = decode_ALU_CTRL; + assign _zz_1_ = _zz_56_; + assign _zz_38_ = decode_to_execute_ALU_CTRL; + assign decode_arbitration_isFlushed = ({execute_arbitration_flushAll,decode_arbitration_flushAll} != (2'b00)); + assign execute_arbitration_isFlushed = (execute_arbitration_flushAll != (1'b0)); + assign decode_arbitration_isStuckByOthers = (decode_arbitration_haltByOther || (1'b0 || execute_arbitration_isStuck)); + assign decode_arbitration_isStuck = (decode_arbitration_haltItself || decode_arbitration_isStuckByOthers); + assign decode_arbitration_isMoving = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)); + assign decode_arbitration_isFiring = ((decode_arbitration_isValid && (! decode_arbitration_isStuck)) && (! decode_arbitration_removeIt)); + assign execute_arbitration_isStuckByOthers = (execute_arbitration_haltByOther || 1'b0); + assign execute_arbitration_isStuck = (execute_arbitration_haltItself || execute_arbitration_isStuckByOthers); + assign execute_arbitration_isMoving = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)); + assign execute_arbitration_isFiring = ((execute_arbitration_isValid && (! execute_arbitration_isStuck)) && (! execute_arbitration_removeIt)); + assign iBusWishbone_ADR = {_zz_221_,_zz_132_}; + assign iBusWishbone_CTI = ((_zz_132_ == (3'b111)) ? (3'b111) : (3'b010)); + assign iBusWishbone_BTE = (2'b00); + assign iBusWishbone_SEL = (4'b1111); + assign iBusWishbone_WE = 1'b0; + assign iBusWishbone_DAT_MOSI = (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx); + always @ (*) begin + iBusWishbone_CYC = 1'b0; + iBusWishbone_STB = 1'b0; + if(_zz_170_)begin + iBusWishbone_CYC = 1'b1; + iBusWishbone_STB = 1'b1; + end + end + + assign iBus_cmd_ready = (iBus_cmd_valid && iBusWishbone_ACK); + assign iBus_rsp_valid = _zz_133_; + assign iBus_rsp_payload_data = iBusWishbone_DAT_MISO_regNext; + assign iBus_rsp_payload_error = 1'b0; + assign dBus_cmd_halfPipe_valid = dBus_cmd_halfPipe_regs_valid; + assign dBus_cmd_halfPipe_payload_wr = dBus_cmd_halfPipe_regs_payload_wr; + assign dBus_cmd_halfPipe_payload_address = dBus_cmd_halfPipe_regs_payload_address; + assign dBus_cmd_halfPipe_payload_data = dBus_cmd_halfPipe_regs_payload_data; + assign dBus_cmd_halfPipe_payload_size = dBus_cmd_halfPipe_regs_payload_size; + assign dBus_cmd_ready = dBus_cmd_halfPipe_regs_ready; + assign dBusWishbone_ADR = (dBus_cmd_halfPipe_payload_address >>> 2); + assign dBusWishbone_CTI = (3'b000); + assign dBusWishbone_BTE = (2'b00); + always @ (*) begin + case(dBus_cmd_halfPipe_payload_size) + 2'b00 : begin + _zz_134_ = (4'b0001); + end + 2'b01 : begin + _zz_134_ = (4'b0011); + end + default : begin + _zz_134_ = (4'b1111); + end + endcase + end + + always @ (*) begin + dBusWishbone_SEL = _zz_222_[3:0]; + if((! dBus_cmd_halfPipe_payload_wr))begin + dBusWishbone_SEL = (4'b1111); + end + end + + assign dBusWishbone_WE = dBus_cmd_halfPipe_payload_wr; + assign dBusWishbone_DAT_MOSI = dBus_cmd_halfPipe_payload_data; + assign dBus_cmd_halfPipe_ready = (dBus_cmd_halfPipe_valid && dBusWishbone_ACK); + assign dBusWishbone_CYC = dBus_cmd_halfPipe_valid; + assign dBusWishbone_STB = dBus_cmd_halfPipe_valid; + assign dBus_rsp_ready = ((dBus_cmd_halfPipe_valid && (! dBusWishbone_WE)) && dBusWishbone_ACK); + assign dBus_rsp_data = dBusWishbone_DAT_MISO; + assign dBus_rsp_error = 1'b0; + always @ (posedge clk) begin + if(reset) begin + IBusCachedPlugin_fetchPc_pcReg <= externalResetVector; + IBusCachedPlugin_fetchPc_inc <= 1'b0; + _zz_77_ <= 1'b0; + _zz_82_ <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; + IBusCachedPlugin_injector_decodeRemoved <= 1'b0; + execute_DBusSimplePlugin_cmdSent <= 1'b0; + execute_LightShifterPlugin_isActive <= 1'b0; + CsrPlugin_mstatus_MIE <= 1'b0; + CsrPlugin_mstatus_MPIE <= 1'b0; + CsrPlugin_mstatus_MPP <= (2'b11); + CsrPlugin_mie_MEIE <= 1'b0; + CsrPlugin_mie_MTIE <= 1'b0; + CsrPlugin_mie_MSIE <= 1'b0; + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= 1'b0; + CsrPlugin_hadException <= 1'b0; + _zz_128_ <= (32'b00000000000000000000000000000000); + execute_arbitration_isValid <= 1'b0; + _zz_131_ <= (3'b000); + _zz_132_ <= (3'b000); + _zz_133_ <= 1'b0; + dBus_cmd_halfPipe_regs_valid <= 1'b0; + dBus_cmd_halfPipe_regs_ready <= 1'b1; + end else begin + if(IBusCachedPlugin_fetchPc_propagatePc)begin + IBusCachedPlugin_fetchPc_inc <= 1'b0; + end + if(IBusCachedPlugin_jump_pcLoad_valid)begin + IBusCachedPlugin_fetchPc_inc <= 1'b0; + end + if(_zz_168_)begin + IBusCachedPlugin_fetchPc_inc <= 1'b1; + end + if(IBusCachedPlugin_fetchPc_samplePcNext)begin + IBusCachedPlugin_fetchPc_pcReg <= IBusCachedPlugin_fetchPc_pc; + end + _zz_77_ <= 1'b1; + if((IBusCachedPlugin_jump_pcLoad_valid || IBusCachedPlugin_fetcherflushIt))begin + _zz_82_ <= 1'b0; + end + if(_zz_80_)begin + _zz_82_ <= IBusCachedPlugin_iBusRsp_stages_0_output_valid; + end + if((IBusCachedPlugin_jump_pcLoad_valid || IBusCachedPlugin_fetcherflushIt))begin + IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; + end + if((! (! IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready)))begin + IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b1; + end + if((IBusCachedPlugin_jump_pcLoad_valid || IBusCachedPlugin_fetcherflushIt))begin + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; + end + if((! execute_arbitration_isStuck))begin + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= IBusCachedPlugin_injector_nextPcCalc_valids_0; + end + if((IBusCachedPlugin_jump_pcLoad_valid || IBusCachedPlugin_fetcherflushIt))begin + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; + end + if(decode_arbitration_removeIt)begin + IBusCachedPlugin_injector_decodeRemoved <= 1'b1; + end + if((IBusCachedPlugin_jump_pcLoad_valid || IBusCachedPlugin_fetcherflushIt))begin + IBusCachedPlugin_injector_decodeRemoved <= 1'b0; + end + if((dBus_cmd_valid && dBus_cmd_ready))begin + execute_DBusSimplePlugin_cmdSent <= 1'b1; + end + if((! execute_arbitration_isStuck))begin + execute_DBusSimplePlugin_cmdSent <= 1'b0; + end + if(_zz_158_)begin + if(_zz_159_)begin + execute_LightShifterPlugin_isActive <= 1'b1; + if(execute_LightShifterPlugin_done)begin + execute_LightShifterPlugin_isActive <= 1'b0; + end + end + end + if(execute_arbitration_removeIt)begin + execute_LightShifterPlugin_isActive <= 1'b0; + end + if((! decode_arbitration_isStuck))begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; + end else begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= CsrPlugin_exceptionPortCtrl_exceptionValids_decode; + end + if((! execute_arbitration_isStuck))begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= (CsrPlugin_exceptionPortCtrl_exceptionValids_decode && (! decode_arbitration_isStuck)); + end else begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= 1'b0; + end + CsrPlugin_hadException <= CsrPlugin_exception; + if(_zz_162_)begin + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_mstatus_MIE <= 1'b0; + CsrPlugin_mstatus_MPIE <= CsrPlugin_mstatus_MIE; + CsrPlugin_mstatus_MPP <= CsrPlugin_privilege; + end + default : begin + end + endcase + end + if(_zz_163_)begin + case(_zz_164_) + 2'b11 : begin + CsrPlugin_mstatus_MPP <= (2'b00); + CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE; + CsrPlugin_mstatus_MPIE <= 1'b1; + end + default : begin + end + endcase + end + if(((! execute_arbitration_isStuck) || execute_arbitration_removeIt))begin + execute_arbitration_isValid <= 1'b0; + end + if(((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)))begin + execute_arbitration_isValid <= decode_arbitration_isValid; + end + case(_zz_131_) + 3'b000 : begin + if(IBusCachedPlugin_injectionPort_valid)begin + _zz_131_ <= (3'b001); + end + end + 3'b001 : begin + _zz_131_ <= (3'b010); + end + 3'b010 : begin + _zz_131_ <= (3'b011); + end + 3'b011 : begin + if((! decode_arbitration_isStuck))begin + _zz_131_ <= (3'b100); + end + end + 3'b100 : begin + _zz_131_ <= (3'b000); + end + default : begin + end + endcase + case(execute_CsrPlugin_csrAddress) + 12'b101111000000 : begin + if(execute_CsrPlugin_writeEnable)begin + _zz_128_ <= execute_CsrPlugin_writeData[31 : 0]; + end + end + 12'b001100000000 : begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11]; + CsrPlugin_mstatus_MPIE <= _zz_215_[0]; + CsrPlugin_mstatus_MIE <= _zz_216_[0]; + end + end + 12'b001101000001 : begin + end + 12'b001100000101 : begin + end + 12'b001101000100 : begin + end + 12'b001101000011 : begin + end + 12'b111111000000 : begin + end + 12'b001101000000 : begin + end + 12'b001100000100 : begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mie_MEIE <= _zz_218_[0]; + CsrPlugin_mie_MTIE <= _zz_219_[0]; + CsrPlugin_mie_MSIE <= _zz_220_[0]; + end + end + 12'b001101000010 : begin + end + default : begin + end + endcase + if(_zz_170_)begin + if(iBusWishbone_ACK)begin + _zz_132_ <= (_zz_132_ + (3'b001)); + end + end + _zz_133_ <= (iBusWishbone_CYC && iBusWishbone_ACK); + if(_zz_171_)begin + dBus_cmd_halfPipe_regs_valid <= dBus_cmd_valid; + dBus_cmd_halfPipe_regs_ready <= (! dBus_cmd_valid); + end else begin + dBus_cmd_halfPipe_regs_valid <= (! dBus_cmd_halfPipe_ready); + dBus_cmd_halfPipe_regs_ready <= dBus_cmd_halfPipe_ready; + end + end + end + + always @ (posedge clk) begin + if(IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready)begin + IBusCachedPlugin_s1_tightlyCoupledHit <= IBusCachedPlugin_s0_tightlyCoupledHit; + end + if((! execute_arbitration_isStuckByOthers))begin + execute_LightShifterPlugin_shiftReg <= _zz_61_; + end + if(_zz_158_)begin + if(_zz_159_)begin + execute_LightShifterPlugin_amplitudeReg <= (execute_LightShifterPlugin_amplitude - (5'b00001)); + end + end + CsrPlugin_mip_MEIP <= externalInterrupt; + CsrPlugin_mip_MTIP <= timerInterrupt; + CsrPlugin_mip_MSIP <= softwareInterrupt; + CsrPlugin_mcycle <= (CsrPlugin_mcycle + (64'b0000000000000000000000000000000000000000000000000000000000000001)); + if(execute_arbitration_isFiring)begin + CsrPlugin_minstret <= (CsrPlugin_minstret + (64'b0000000000000000000000000000000000000000000000000000000000000001)); + end + if(_zz_160_)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_122_ ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_122_ ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); + end + if(_zz_161_)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= _zz_156_; + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= _zz_157_; + end + if(_zz_162_)begin + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException); + CsrPlugin_mcause_exceptionCode <= CsrPlugin_trapCause; + CsrPlugin_mepc <= execute_PC; + if(CsrPlugin_hadException)begin + CsrPlugin_mtval <= CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; + end + end + default : begin + end + endcase + end + externalInterruptArray_regNext <= externalInterruptArray; + if((! execute_arbitration_isStuck))begin + decode_to_execute_INSTRUCTION <= decode_INSTRUCTION; + end + if(((! execute_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_execute)))begin + decode_to_execute_PC <= decode_PC; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_FORMAL_PC_NEXT <= _zz_68_; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_ALU_BITWISE_CTRL <= _zz_20_; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_CSR_READ_OPCODE <= decode_CSR_READ_OPCODE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_MEMORY_ENABLE <= decode_MEMORY_ENABLE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_ENV_CTRL <= _zz_17_; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC_USE_SUB_LESS <= decode_SRC_USE_SUB_LESS; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SHIFT_CTRL <= _zz_14_; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_MEMORY_STORE <= decode_MEMORY_STORE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_BRANCH_CTRL <= _zz_11_; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_CSR <= decode_IS_CSR; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC2_FORCE_ZERO <= decode_SRC2_FORCE_ZERO; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_CSR_WRITE_OPCODE <= decode_CSR_WRITE_OPCODE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC1_CTRL <= _zz_8_; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC2_CTRL <= _zz_5_; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_DO_EBREAK <= decode_DO_EBREAK; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_ALU_CTRL <= _zz_2_; + end + case(execute_CsrPlugin_csrAddress) + 12'b101111000000 : begin + end + 12'b001100000000 : begin + end + 12'b001101000001 : begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mepc <= execute_CsrPlugin_writeData[31 : 0]; + end + end + 12'b001100000101 : begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mtvec_base <= execute_CsrPlugin_writeData[31 : 2]; + CsrPlugin_mtvec_mode <= execute_CsrPlugin_writeData[1 : 0]; + end + end + 12'b001101000100 : begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mip_MSIP <= _zz_217_[0]; + end + end + 12'b001101000011 : begin + end + 12'b111111000000 : begin + end + 12'b001101000000 : begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mscratch <= execute_CsrPlugin_writeData[31 : 0]; + end + end + 12'b001100000100 : begin + end + 12'b001101000010 : begin + end + default : begin + end + endcase + iBusWishbone_DAT_MISO_regNext <= iBusWishbone_DAT_MISO; + if(_zz_171_)begin + dBus_cmd_halfPipe_regs_payload_wr <= dBus_cmd_payload_wr; + dBus_cmd_halfPipe_regs_payload_address <= dBus_cmd_payload_address; + dBus_cmd_halfPipe_regs_payload_data <= dBus_cmd_payload_data; + dBus_cmd_halfPipe_regs_payload_size <= dBus_cmd_payload_size; + end + end + + always @ (posedge clk) begin + DebugPlugin_firstCycle <= 1'b0; + if(debug_bus_cmd_ready)begin + DebugPlugin_firstCycle <= 1'b1; + end + DebugPlugin_secondCycle <= DebugPlugin_firstCycle; + DebugPlugin_isPipBusy <= (({execute_arbitration_isValid,decode_arbitration_isValid} != (2'b00)) || IBusCachedPlugin_incomingInstruction); + if(execute_arbitration_isValid)begin + DebugPlugin_busReadDataReg <= _zz_61_; + end + _zz_130_ <= debug_bus_cmd_payload_address[2]; + if(debug_bus_cmd_valid)begin + case(_zz_169_) + 6'b000000 : begin + end + 6'b000001 : begin + end + 6'b010000 : begin + if(debug_bus_cmd_payload_wr)begin + DebugPlugin_hardwareBreakpoints_0_pc <= debug_bus_cmd_payload_data[31 : 1]; + end + end + 6'b010001 : begin + if(debug_bus_cmd_payload_wr)begin + DebugPlugin_hardwareBreakpoints_1_pc <= debug_bus_cmd_payload_data[31 : 1]; + end + end + 6'b010010 : begin + if(debug_bus_cmd_payload_wr)begin + DebugPlugin_hardwareBreakpoints_2_pc <= debug_bus_cmd_payload_data[31 : 1]; + end + end + 6'b010011 : begin + if(debug_bus_cmd_payload_wr)begin + DebugPlugin_hardwareBreakpoints_3_pc <= debug_bus_cmd_payload_data[31 : 1]; + end + end + default : begin + end + endcase + end + if(_zz_165_)begin + DebugPlugin_busReadDataReg <= execute_PC; + end + DebugPlugin_resetIt_regNext <= DebugPlugin_resetIt; + end + + always @ (posedge clk) begin + if(debugReset) begin + DebugPlugin_resetIt <= 1'b0; + DebugPlugin_haltIt <= 1'b0; + DebugPlugin_stepIt <= 1'b0; + DebugPlugin_godmode <= 1'b0; + DebugPlugin_haltedByBreak <= 1'b0; + DebugPlugin_hardwareBreakpoints_0_valid <= 1'b0; + DebugPlugin_hardwareBreakpoints_1_valid <= 1'b0; + DebugPlugin_hardwareBreakpoints_2_valid <= 1'b0; + DebugPlugin_hardwareBreakpoints_3_valid <= 1'b0; + end else begin + if((DebugPlugin_haltIt && (! DebugPlugin_isPipBusy)))begin + DebugPlugin_godmode <= 1'b1; + end + if(debug_bus_cmd_valid)begin + case(_zz_169_) + 6'b000000 : begin + if(debug_bus_cmd_payload_wr)begin + DebugPlugin_stepIt <= debug_bus_cmd_payload_data[4]; + if(debug_bus_cmd_payload_data[16])begin + DebugPlugin_resetIt <= 1'b1; + end + if(debug_bus_cmd_payload_data[24])begin + DebugPlugin_resetIt <= 1'b0; + end + if(debug_bus_cmd_payload_data[17])begin + DebugPlugin_haltIt <= 1'b1; + end + if(debug_bus_cmd_payload_data[25])begin + DebugPlugin_haltIt <= 1'b0; + end + if(debug_bus_cmd_payload_data[25])begin + DebugPlugin_haltedByBreak <= 1'b0; + end + if(debug_bus_cmd_payload_data[25])begin + DebugPlugin_godmode <= 1'b0; + end + end + end + 6'b000001 : begin + end + 6'b010000 : begin + if(debug_bus_cmd_payload_wr)begin + DebugPlugin_hardwareBreakpoints_0_valid <= _zz_207_[0]; + end + end + 6'b010001 : begin + if(debug_bus_cmd_payload_wr)begin + DebugPlugin_hardwareBreakpoints_1_valid <= _zz_208_[0]; + end + end + 6'b010010 : begin + if(debug_bus_cmd_payload_wr)begin + DebugPlugin_hardwareBreakpoints_2_valid <= _zz_209_[0]; + end + end + 6'b010011 : begin + if(debug_bus_cmd_payload_wr)begin + DebugPlugin_hardwareBreakpoints_3_valid <= _zz_210_[0]; + end + end + default : begin + end + endcase + end + if(_zz_165_)begin + if(_zz_166_)begin + DebugPlugin_haltIt <= 1'b1; + DebugPlugin_haltedByBreak <= 1'b1; + end + end + if(_zz_167_)begin + if(decode_arbitration_isValid)begin + DebugPlugin_haltIt <= 1'b1; + end + end + end + end + + always @ (posedge clk) begin + IBusCachedPlugin_injectionPort_payload_regNext <= IBusCachedPlugin_injectionPort_payload; + end + +endmodule + diff --git a/hw/rtl/2-stage-1024-cache-debug.v_toplevel_RegFilePlugin_regFile.bin b/hw/rtl/2-stage-1024-cache-debug.v_toplevel_RegFilePlugin_regFile.bin new file mode 100644 index 0000000000000000000000000000000000000000..4c177b2156e519e76ef33fcac7621445a9beb984 GIT binary patch literal 1056 fcmXpozz?|aOB)!BDu9I0XgG|919Dy&Cg}kHTp__h literal 0 HcmV?d00001 diff --git a/hw/2-stage-1024-cache-debug.yaml b/hw/rtl/2-stage-1024-cache-debug.yaml similarity index 79% rename from hw/2-stage-1024-cache-debug.yaml rename to hw/rtl/2-stage-1024-cache-debug.yaml index 156f2e4..5864b0c 100644 --- a/hw/2-stage-1024-cache-debug.yaml +++ b/hw/rtl/2-stage-1024-cache-debug.yaml @@ -1,5 +1,5 @@ debug: !!vexriscv.DebugReport {hardwareBreakpointCount: 4} iBus: !!vexriscv.BusReport - flushInstructions: [16399, 19, 19, 19] + flushInstructions: [4111, 19, 19, 19] info: !!vexriscv.CacheReport {bytePerLine: 32, size: 1024} kind: cached diff --git a/hw/2-stage-1024-cache.v b/hw/rtl/2-stage-1024-cache.v similarity index 51% rename from hw/2-stage-1024-cache.v rename to hw/rtl/2-stage-1024-cache.v index 7a38ed6..79c9a28 100644 --- a/hw/2-stage-1024-cache.v +++ b/hw/rtl/2-stage-1024-cache.v @@ -1,32 +1,8 @@ -// Generator : SpinalHDL v1.3.2 git head : 41815ceafff4e72c2e3a3e1ff7e9ada5202a0d26 -// Date : 29/03/2019, 05:39:18 +// Generator : SpinalHDL v1.3.3 git head : 8b8cd335eecbea3b5f1f970f218a982dbdb12d99 +// Date : 25/04/2019, 14:34:00 // Component : VexRiscv -`define Src1CtrlEnum_defaultEncoding_type [1:0] -`define Src1CtrlEnum_defaultEncoding_RS 2'b00 -`define Src1CtrlEnum_defaultEncoding_IMU 2'b01 -`define Src1CtrlEnum_defaultEncoding_PC_INCREMENT 2'b10 -`define Src1CtrlEnum_defaultEncoding_URS1 2'b11 - -`define AluBitwiseCtrlEnum_defaultEncoding_type [1:0] -`define AluBitwiseCtrlEnum_defaultEncoding_XOR_1 2'b00 -`define AluBitwiseCtrlEnum_defaultEncoding_OR_1 2'b01 -`define AluBitwiseCtrlEnum_defaultEncoding_AND_1 2'b10 -`define AluBitwiseCtrlEnum_defaultEncoding_SRC1 2'b11 - -`define ShiftCtrlEnum_defaultEncoding_type [1:0] -`define ShiftCtrlEnum_defaultEncoding_DISABLE_1 2'b00 -`define ShiftCtrlEnum_defaultEncoding_SLL_1 2'b01 -`define ShiftCtrlEnum_defaultEncoding_SRL_1 2'b10 -`define ShiftCtrlEnum_defaultEncoding_SRA_1 2'b11 - -`define BranchCtrlEnum_defaultEncoding_type [1:0] -`define BranchCtrlEnum_defaultEncoding_INC 2'b00 -`define BranchCtrlEnum_defaultEncoding_B 2'b01 -`define BranchCtrlEnum_defaultEncoding_JAL 2'b10 -`define BranchCtrlEnum_defaultEncoding_JALR 2'b11 - `define EnvCtrlEnum_defaultEncoding_type [1:0] `define EnvCtrlEnum_defaultEncoding_NONE 2'b00 `define EnvCtrlEnum_defaultEncoding_XRET 2'b01 @@ -39,15 +15,36 @@ `define Src2CtrlEnum_defaultEncoding_IMS 2'b10 `define Src2CtrlEnum_defaultEncoding_PC 2'b11 +`define Src1CtrlEnum_defaultEncoding_type [1:0] +`define Src1CtrlEnum_defaultEncoding_RS 2'b00 +`define Src1CtrlEnum_defaultEncoding_IMU 2'b01 +`define Src1CtrlEnum_defaultEncoding_PC_INCREMENT 2'b10 +`define Src1CtrlEnum_defaultEncoding_URS1 2'b11 + `define AluCtrlEnum_defaultEncoding_type [1:0] `define AluCtrlEnum_defaultEncoding_ADD_SUB 2'b00 `define AluCtrlEnum_defaultEncoding_SLT_SLTU 2'b01 `define AluCtrlEnum_defaultEncoding_BITWISE 2'b10 +`define BranchCtrlEnum_defaultEncoding_type [1:0] +`define BranchCtrlEnum_defaultEncoding_INC 2'b00 +`define BranchCtrlEnum_defaultEncoding_B 2'b01 +`define BranchCtrlEnum_defaultEncoding_JAL 2'b10 +`define BranchCtrlEnum_defaultEncoding_JALR 2'b11 + +`define ShiftCtrlEnum_defaultEncoding_type [1:0] +`define ShiftCtrlEnum_defaultEncoding_DISABLE_1 2'b00 +`define ShiftCtrlEnum_defaultEncoding_SLL_1 2'b01 +`define ShiftCtrlEnum_defaultEncoding_SRL_1 2'b10 +`define ShiftCtrlEnum_defaultEncoding_SRA_1 2'b11 + +`define AluBitwiseCtrlEnum_defaultEncoding_type [1:0] +`define AluBitwiseCtrlEnum_defaultEncoding_XOR_1 2'b00 +`define AluBitwiseCtrlEnum_defaultEncoding_OR_1 2'b01 +`define AluBitwiseCtrlEnum_defaultEncoding_AND_1 2'b10 + module InstructionCache ( - input io_flush_cmd_valid, - output io_flush_cmd_ready, - output io_flush_rsp, + input io_flush, input io_cpu_prefetch_isValid, output reg io_cpu_prefetch_haltIt, input [31:0] io_cpu_prefetch_pc, @@ -66,21 +63,22 @@ module InstructionCache ( input io_cpu_fetch_mmuBus_rsp_allowRead, input io_cpu_fetch_mmuBus_rsp_allowWrite, input io_cpu_fetch_mmuBus_rsp_allowExecute, - input io_cpu_fetch_mmuBus_rsp_allowUser, - input io_cpu_fetch_mmuBus_rsp_miss, - input io_cpu_fetch_mmuBus_rsp_hit, + input io_cpu_fetch_mmuBus_rsp_exception, + input io_cpu_fetch_mmuBus_rsp_refilling, output io_cpu_fetch_mmuBus_end, + input io_cpu_fetch_mmuBus_busy, output [31:0] io_cpu_fetch_physicalAddress, + output io_cpu_fetch_cacheMiss, + output io_cpu_fetch_error, + output io_cpu_fetch_mmuRefilling, + output io_cpu_fetch_mmuException, + input io_cpu_fetch_isUser, + output io_cpu_fetch_haltIt, input io_cpu_decode_isValid, input io_cpu_decode_isStuck, input [31:0] io_cpu_decode_pc, output [31:0] io_cpu_decode_physicalAddress, output [31:0] io_cpu_decode_data, - output io_cpu_decode_cacheMiss, - output io_cpu_decode_error, - output io_cpu_decode_mmuMiss, - output io_cpu_decode_illegalAccess, - input io_cpu_decode_isUser, input io_cpu_fill_valid, input [31:0] io_cpu_fill_payload, output io_mem_cmd_valid, @@ -92,23 +90,22 @@ module InstructionCache ( input io_mem_rsp_payload_error, input clk, input reset); - reg [23:0] _zz_12_; - reg [31:0] _zz_13_; - wire _zz_14_; + reg [22:0] _zz_10_; + reg [31:0] _zz_11_; + wire _zz_12_; + wire _zz_13_; + wire [0:0] _zz_14_; wire [0:0] _zz_15_; - wire [0:0] _zz_16_; - wire [23:0] _zz_17_; + wire [22:0] _zz_16_; reg _zz_1_; reg _zz_2_; reg lineLoader_fire; reg lineLoader_valid; reg [31:0] lineLoader_address; reg lineLoader_hadError; - reg [5:0] lineLoader_flushCounter; + reg lineLoader_flushPending; + reg [6:0] lineLoader_flushCounter; reg _zz_3_; - reg lineLoader_flushFromInterface; - wire _zz_4_; - reg _zz_4__regNext; reg lineLoader_cmdSent; reg lineLoader_wayToAllocate_willIncrement; wire lineLoader_wayToAllocate_willClear; @@ -116,57 +113,44 @@ module InstructionCache ( wire lineLoader_wayToAllocate_willOverflow; reg [2:0] lineLoader_wordIndex; wire lineLoader_write_tag_0_valid; - wire [4:0] lineLoader_write_tag_0_payload_address; + wire [5:0] lineLoader_write_tag_0_payload_address; wire lineLoader_write_tag_0_payload_data_valid; wire lineLoader_write_tag_0_payload_data_error; - wire [21:0] lineLoader_write_tag_0_payload_data_address; + wire [20:0] lineLoader_write_tag_0_payload_data_address; wire lineLoader_write_data_0_valid; - wire [7:0] lineLoader_write_data_0_payload_address; + wire [8:0] lineLoader_write_data_0_payload_address; wire [31:0] lineLoader_write_data_0_payload_data; - wire _zz_5_; - wire [4:0] _zz_6_; - wire _zz_7_; + wire _zz_4_; + wire [5:0] _zz_5_; + wire _zz_6_; wire fetchStage_read_waysValues_0_tag_valid; wire fetchStage_read_waysValues_0_tag_error; - wire [21:0] fetchStage_read_waysValues_0_tag_address; - wire [23:0] _zz_8_; - wire [7:0] _zz_9_; - wire _zz_10_; + wire [20:0] fetchStage_read_waysValues_0_tag_address; + wire [22:0] _zz_7_; + wire [8:0] _zz_8_; + wire _zz_9_; wire [31:0] fetchStage_read_waysValues_0_data; - reg [31:0] decodeStage_mmuRsp_physicalAddress; - reg decodeStage_mmuRsp_isIoAccess; - reg decodeStage_mmuRsp_allowRead; - reg decodeStage_mmuRsp_allowWrite; - reg decodeStage_mmuRsp_allowExecute; - reg decodeStage_mmuRsp_allowUser; - reg decodeStage_mmuRsp_miss; - reg decodeStage_mmuRsp_hit; - reg decodeStage_hit_tags_0_valid; - reg decodeStage_hit_tags_0_error; - reg [21:0] decodeStage_hit_tags_0_address; - wire decodeStage_hit_hits_0; - wire decodeStage_hit_valid; - wire decodeStage_hit_error; - reg [31:0] _zz_11_; - wire [31:0] decodeStage_hit_data; - reg [31:0] decodeStage_hit_word; - reg io_cpu_fetch_dataBypassValid_regNextWhen; - reg [31:0] io_cpu_fetch_dataBypass_regNextWhen; - reg [23:0] ways_0_tags [0:31]; - reg [31:0] ways_0_datas [0:255]; - assign _zz_14_ = (! lineLoader_flushCounter[5]); - assign _zz_15_ = _zz_8_[0 : 0]; - assign _zz_16_ = _zz_8_[1 : 1]; - assign _zz_17_ = {lineLoader_write_tag_0_payload_data_address,{lineLoader_write_tag_0_payload_data_error,lineLoader_write_tag_0_payload_data_valid}}; + wire fetchStage_hit_hits_0; + wire fetchStage_hit_valid; + wire fetchStage_hit_error; + wire [31:0] fetchStage_hit_data; + wire [31:0] fetchStage_hit_word; + reg [22:0] ways_0_tags [0:63]; + reg [31:0] ways_0_datas [0:511]; + assign _zz_12_ = (! lineLoader_flushCounter[6]); + assign _zz_13_ = (lineLoader_flushPending && (! (lineLoader_valid || io_cpu_fetch_isValid))); + assign _zz_14_ = _zz_7_[0 : 0]; + assign _zz_15_ = _zz_7_[1 : 1]; + assign _zz_16_ = {lineLoader_write_tag_0_payload_data_address,{lineLoader_write_tag_0_payload_data_error,lineLoader_write_tag_0_payload_data_valid}}; always @ (posedge clk) begin if(_zz_2_) begin - ways_0_tags[lineLoader_write_tag_0_payload_address] <= _zz_17_; + ways_0_tags[lineLoader_write_tag_0_payload_address] <= _zz_16_; end end always @ (posedge clk) begin - if(_zz_7_) begin - _zz_12_ <= ways_0_tags[_zz_6_]; + if(_zz_6_) begin + _zz_10_ <= ways_0_tags[_zz_5_]; end end @@ -177,8 +161,8 @@ module InstructionCache ( end always @ (posedge clk) begin - if(_zz_10_) begin - _zz_13_ <= ways_0_datas[_zz_9_]; + if(_zz_9_) begin + _zz_11_ <= ways_0_datas[_zz_8_]; end end @@ -196,22 +180,7 @@ module InstructionCache ( end end - always @ (*) begin - io_cpu_prefetch_haltIt = 1'b0; - if(lineLoader_valid)begin - io_cpu_prefetch_haltIt = 1'b1; - end - if(_zz_14_)begin - io_cpu_prefetch_haltIt = 1'b1; - end - if((! _zz_3_))begin - io_cpu_prefetch_haltIt = 1'b1; - end - if(io_flush_cmd_valid)begin - io_cpu_prefetch_haltIt = 1'b1; - end - end - + assign io_cpu_fetch_haltIt = io_cpu_fetch_mmuBus_busy; always @ (*) begin lineLoader_fire = 1'b0; if(io_mem_rsp_valid)begin @@ -221,9 +190,19 @@ module InstructionCache ( end end - assign io_flush_cmd_ready = (! (lineLoader_valid || io_cpu_fetch_isValid)); - assign _zz_4_ = lineLoader_flushCounter[5]; - assign io_flush_rsp = ((_zz_4_ && (! _zz_4__regNext)) && lineLoader_flushFromInterface); + always @ (*) begin + io_cpu_prefetch_haltIt = (lineLoader_valid || lineLoader_flushPending); + if(_zz_12_)begin + io_cpu_prefetch_haltIt = 1'b1; + end + if((! _zz_3_))begin + io_cpu_prefetch_haltIt = 1'b1; + end + if(io_flush)begin + io_cpu_prefetch_haltIt = 1'b1; + end + end + assign io_mem_cmd_valid = (lineLoader_valid && (! lineLoader_cmdSent)); assign io_mem_cmd_payload_address = {lineLoader_address[31 : 5],(5'b00000)}; assign io_mem_cmd_payload_size = (3'b101); @@ -237,53 +216,44 @@ module InstructionCache ( assign lineLoader_wayToAllocate_willClear = 1'b0; assign lineLoader_wayToAllocate_willOverflowIfInc = 1'b1; assign lineLoader_wayToAllocate_willOverflow = (lineLoader_wayToAllocate_willOverflowIfInc && lineLoader_wayToAllocate_willIncrement); - assign _zz_5_ = 1'b1; - assign lineLoader_write_tag_0_valid = ((_zz_5_ && lineLoader_fire) || (! lineLoader_flushCounter[5])); - assign lineLoader_write_tag_0_payload_address = (lineLoader_flushCounter[5] ? lineLoader_address[9 : 5] : lineLoader_flushCounter[4 : 0]); - assign lineLoader_write_tag_0_payload_data_valid = lineLoader_flushCounter[5]; + assign _zz_4_ = 1'b1; + assign lineLoader_write_tag_0_valid = ((_zz_4_ && lineLoader_fire) || (! lineLoader_flushCounter[6])); + assign lineLoader_write_tag_0_payload_address = (lineLoader_flushCounter[6] ? lineLoader_address[10 : 5] : lineLoader_flushCounter[5 : 0]); + assign lineLoader_write_tag_0_payload_data_valid = lineLoader_flushCounter[6]; assign lineLoader_write_tag_0_payload_data_error = (lineLoader_hadError || io_mem_rsp_payload_error); - assign lineLoader_write_tag_0_payload_data_address = lineLoader_address[31 : 10]; - assign lineLoader_write_data_0_valid = (io_mem_rsp_valid && _zz_5_); - assign lineLoader_write_data_0_payload_address = {lineLoader_address[9 : 5],lineLoader_wordIndex}; + assign lineLoader_write_tag_0_payload_data_address = lineLoader_address[31 : 11]; + assign lineLoader_write_data_0_valid = (io_mem_rsp_valid && _zz_4_); + assign lineLoader_write_data_0_payload_address = {lineLoader_address[10 : 5],lineLoader_wordIndex}; assign lineLoader_write_data_0_payload_data = io_mem_rsp_payload_data; - assign _zz_6_ = io_cpu_prefetch_pc[9 : 5]; - assign _zz_7_ = (! io_cpu_fetch_isStuck); - assign _zz_8_ = _zz_12_; - assign fetchStage_read_waysValues_0_tag_valid = _zz_15_[0]; - assign fetchStage_read_waysValues_0_tag_error = _zz_16_[0]; - assign fetchStage_read_waysValues_0_tag_address = _zz_8_[23 : 2]; - assign _zz_9_ = io_cpu_prefetch_pc[9 : 2]; - assign _zz_10_ = (! io_cpu_fetch_isStuck); - assign fetchStage_read_waysValues_0_data = _zz_13_; - assign io_cpu_fetch_data = (io_cpu_fetch_dataBypassValid ? io_cpu_fetch_dataBypass : fetchStage_read_waysValues_0_data[31 : 0]); + assign _zz_5_ = io_cpu_prefetch_pc[10 : 5]; + assign _zz_6_ = (! io_cpu_fetch_isStuck); + assign _zz_7_ = _zz_10_; + assign fetchStage_read_waysValues_0_tag_valid = _zz_14_[0]; + assign fetchStage_read_waysValues_0_tag_error = _zz_15_[0]; + assign fetchStage_read_waysValues_0_tag_address = _zz_7_[22 : 2]; + assign _zz_8_ = io_cpu_prefetch_pc[10 : 2]; + assign _zz_9_ = (! io_cpu_fetch_isStuck); + assign fetchStage_read_waysValues_0_data = _zz_11_; + assign fetchStage_hit_hits_0 = (fetchStage_read_waysValues_0_tag_valid && (fetchStage_read_waysValues_0_tag_address == io_cpu_fetch_mmuBus_rsp_physicalAddress[31 : 11])); + assign fetchStage_hit_valid = (fetchStage_hit_hits_0 != (1'b0)); + assign fetchStage_hit_error = fetchStage_read_waysValues_0_tag_error; + assign fetchStage_hit_data = fetchStage_read_waysValues_0_data; + assign fetchStage_hit_word = fetchStage_hit_data[31 : 0]; + assign io_cpu_fetch_data = (io_cpu_fetch_dataBypassValid ? io_cpu_fetch_dataBypass : fetchStage_hit_word); assign io_cpu_fetch_mmuBus_cmd_isValid = io_cpu_fetch_isValid; assign io_cpu_fetch_mmuBus_cmd_virtualAddress = io_cpu_fetch_pc; assign io_cpu_fetch_mmuBus_cmd_bypassTranslation = 1'b0; assign io_cpu_fetch_mmuBus_end = ((! io_cpu_fetch_isStuck) || io_cpu_fetch_isRemoved); assign io_cpu_fetch_physicalAddress = io_cpu_fetch_mmuBus_rsp_physicalAddress; - assign decodeStage_hit_hits_0 = (decodeStage_hit_tags_0_valid && (decodeStage_hit_tags_0_address == decodeStage_mmuRsp_physicalAddress[31 : 10])); - assign decodeStage_hit_valid = (decodeStage_hit_hits_0 != (1'b0)); - assign decodeStage_hit_error = decodeStage_hit_tags_0_error; - assign decodeStage_hit_data = _zz_11_; - always @ (*) begin - decodeStage_hit_word = decodeStage_hit_data[31 : 0]; - if(io_cpu_fetch_dataBypassValid_regNextWhen)begin - decodeStage_hit_word = io_cpu_fetch_dataBypass_regNextWhen; - end - end - - assign io_cpu_decode_data = decodeStage_hit_word; - assign io_cpu_decode_cacheMiss = (! decodeStage_hit_valid); - assign io_cpu_decode_error = decodeStage_hit_error; - assign io_cpu_decode_mmuMiss = decodeStage_mmuRsp_miss; - assign io_cpu_decode_illegalAccess = ((! decodeStage_mmuRsp_allowExecute) || (io_cpu_decode_isUser && (! decodeStage_mmuRsp_allowUser))); - assign io_cpu_decode_physicalAddress = decodeStage_mmuRsp_physicalAddress; + assign io_cpu_fetch_cacheMiss = (! fetchStage_hit_valid); + assign io_cpu_fetch_error = fetchStage_hit_error; + assign io_cpu_fetch_mmuRefilling = io_cpu_fetch_mmuBus_rsp_refilling; + assign io_cpu_fetch_mmuException = ((! io_cpu_fetch_mmuBus_rsp_refilling) && (io_cpu_fetch_mmuBus_rsp_exception || (! io_cpu_fetch_mmuBus_rsp_allowExecute))); always @ (posedge clk) begin if(reset) begin lineLoader_valid <= 1'b0; lineLoader_hadError <= 1'b0; - lineLoader_flushCounter <= (6'b000000); - lineLoader_flushFromInterface <= 1'b0; + lineLoader_flushPending <= 1'b1; lineLoader_cmdSent <= 1'b0; lineLoader_wordIndex <= (3'b000); end else begin @@ -296,14 +266,11 @@ module InstructionCache ( if(io_cpu_fill_valid)begin lineLoader_valid <= 1'b1; end - if(_zz_14_)begin - lineLoader_flushCounter <= (lineLoader_flushCounter + (6'b000001)); + if(io_flush)begin + lineLoader_flushPending <= 1'b1; end - if(io_flush_cmd_valid)begin - if(io_flush_cmd_ready)begin - lineLoader_flushCounter <= (6'b000000); - lineLoader_flushFromInterface <= 1'b1; - end + if(_zz_13_)begin + lineLoader_flushPending <= 1'b0; end if((io_mem_cmd_valid && io_mem_cmd_ready))begin lineLoader_cmdSent <= 1'b1; @@ -324,34 +291,12 @@ module InstructionCache ( if(io_cpu_fill_valid)begin lineLoader_address <= io_cpu_fill_payload; end - _zz_3_ <= lineLoader_flushCounter[5]; - _zz_4__regNext <= _zz_4_; - if((! io_cpu_decode_isStuck))begin - decodeStage_mmuRsp_physicalAddress <= io_cpu_fetch_mmuBus_rsp_physicalAddress; - decodeStage_mmuRsp_isIoAccess <= io_cpu_fetch_mmuBus_rsp_isIoAccess; - decodeStage_mmuRsp_allowRead <= io_cpu_fetch_mmuBus_rsp_allowRead; - decodeStage_mmuRsp_allowWrite <= io_cpu_fetch_mmuBus_rsp_allowWrite; - decodeStage_mmuRsp_allowExecute <= io_cpu_fetch_mmuBus_rsp_allowExecute; - decodeStage_mmuRsp_allowUser <= io_cpu_fetch_mmuBus_rsp_allowUser; - decodeStage_mmuRsp_miss <= io_cpu_fetch_mmuBus_rsp_miss; - decodeStage_mmuRsp_hit <= io_cpu_fetch_mmuBus_rsp_hit; + if(_zz_12_)begin + lineLoader_flushCounter <= (lineLoader_flushCounter + (7'b0000001)); end - if((! io_cpu_decode_isStuck))begin - decodeStage_hit_tags_0_valid <= fetchStage_read_waysValues_0_tag_valid; - decodeStage_hit_tags_0_error <= fetchStage_read_waysValues_0_tag_error; - decodeStage_hit_tags_0_address <= fetchStage_read_waysValues_0_tag_address; - end - if((! io_cpu_decode_isStuck))begin - _zz_11_ <= fetchStage_read_waysValues_0_data; - end - if((! io_cpu_decode_isStuck))begin - io_cpu_fetch_dataBypassValid_regNextWhen <= io_cpu_fetch_dataBypassValid; - end - end - - always @ (posedge clk) begin - if((! io_cpu_decode_isStuck))begin - io_cpu_fetch_dataBypass_regNextWhen <= io_cpu_fetch_dataBypass; + _zz_3_ <= lineLoader_flushCounter[6]; + if(_zz_13_)begin + lineLoader_flushCounter <= (7'b0000000); end end @@ -360,6 +305,7 @@ endmodule module VexRiscv ( input [31:0] externalResetVector, input timerInterrupt, + input softwareInterrupt, input [31:0] externalInterruptArray, output reg iBusWishbone_CYC, output reg iBusWishbone_STB, @@ -385,286 +331,302 @@ module VexRiscv ( output [2:0] dBusWishbone_CTI, input clk, input reset); - reg _zz_158_; - wire _zz_159_; - wire _zz_160_; - wire _zz_161_; - wire _zz_162_; - wire [31:0] _zz_163_; - wire _zz_164_; - wire _zz_165_; - wire _zz_166_; - wire _zz_167_; - wire _zz_168_; - wire _zz_169_; - wire _zz_170_; - wire _zz_171_; - wire _zz_172_; - wire _zz_173_; - reg [31:0] _zz_174_; - reg [31:0] _zz_175_; - reg [31:0] _zz_176_; - reg [3:0] _zz_177_; - reg [31:0] _zz_178_; - wire IBusCachedPlugin_cache_io_flush_cmd_ready; - wire IBusCachedPlugin_cache_io_flush_rsp; + wire _zz_130_; + wire _zz_131_; + wire _zz_132_; + wire _zz_133_; + wire _zz_134_; + wire [31:0] _zz_135_; + wire _zz_136_; + wire _zz_137_; + wire _zz_138_; + wire _zz_139_; + wire _zz_140_; + wire _zz_141_; + wire _zz_142_; + wire _zz_143_; + wire _zz_144_; + wire _zz_145_; + wire [31:0] _zz_146_; + reg _zz_147_; + reg [31:0] _zz_148_; + reg [31:0] _zz_149_; + reg [31:0] _zz_150_; + reg [3:0] _zz_151_; + reg [31:0] _zz_152_; wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt; + wire IBusCachedPlugin_cache_io_cpu_fetch_error; + wire IBusCachedPlugin_cache_io_cpu_fetch_mmuRefilling; + wire IBusCachedPlugin_cache_io_cpu_fetch_mmuException; wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_data; + wire IBusCachedPlugin_cache_io_cpu_fetch_cacheMiss; wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress; + wire IBusCachedPlugin_cache_io_cpu_fetch_haltIt; wire IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_isValid; wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_virtualAddress; wire IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_bypassTranslation; wire IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_end; - wire IBusCachedPlugin_cache_io_cpu_decode_error; - wire IBusCachedPlugin_cache_io_cpu_decode_mmuMiss; - wire IBusCachedPlugin_cache_io_cpu_decode_illegalAccess; wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_data; - wire IBusCachedPlugin_cache_io_cpu_decode_cacheMiss; wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_physicalAddress; wire IBusCachedPlugin_cache_io_mem_cmd_valid; wire [31:0] IBusCachedPlugin_cache_io_mem_cmd_payload_address; wire [2:0] IBusCachedPlugin_cache_io_mem_cmd_payload_size; - wire _zz_179_; - wire _zz_180_; - wire _zz_181_; - wire _zz_182_; - wire _zz_183_; - wire _zz_184_; - wire _zz_185_; - wire [1:0] _zz_186_; - wire [1:0] _zz_187_; - wire _zz_188_; - wire [3:0] _zz_189_; - wire [2:0] _zz_190_; - wire [31:0] _zz_191_; + wire _zz_153_; + wire _zz_154_; + wire _zz_155_; + wire _zz_156_; + wire _zz_157_; + wire _zz_158_; + wire [1:0] _zz_159_; + wire _zz_160_; + wire _zz_161_; + wire _zz_162_; + wire [1:0] _zz_163_; + wire _zz_164_; + wire [2:0] _zz_165_; + wire [2:0] _zz_166_; + wire [31:0] _zz_167_; + wire [2:0] _zz_168_; + wire [0:0] _zz_169_; + wire [0:0] _zz_170_; + wire [0:0] _zz_171_; + wire [0:0] _zz_172_; + wire [0:0] _zz_173_; + wire [0:0] _zz_174_; + wire [0:0] _zz_175_; + wire [0:0] _zz_176_; + wire [0:0] _zz_177_; + wire [2:0] _zz_178_; + wire [4:0] _zz_179_; + wire [11:0] _zz_180_; + wire [11:0] _zz_181_; + wire [31:0] _zz_182_; + wire [31:0] _zz_183_; + wire [31:0] _zz_184_; + wire [31:0] _zz_185_; + wire [31:0] _zz_186_; + wire [31:0] _zz_187_; + wire [31:0] _zz_188_; + wire [31:0] _zz_189_; + wire [32:0] _zz_190_; + wire [19:0] _zz_191_; wire [11:0] _zz_192_; - wire [31:0] _zz_193_; - wire [19:0] _zz_194_; - wire [11:0] _zz_195_; - wire [0:0] _zz_196_; + wire [11:0] _zz_193_; + wire [1:0] _zz_194_; + wire [1:0] _zz_195_; + wire [2:0] _zz_196_; wire [0:0] _zz_197_; wire [0:0] _zz_198_; wire [0:0] _zz_199_; wire [0:0] _zz_200_; wire [0:0] _zz_201_; wire [0:0] _zz_202_; - wire [2:0] _zz_203_; - wire [4:0] _zz_204_; - wire [11:0] _zz_205_; - wire [11:0] _zz_206_; - wire [31:0] _zz_207_; - wire [31:0] _zz_208_; - wire [31:0] _zz_209_; - wire [31:0] _zz_210_; - wire [1:0] _zz_211_; - wire [31:0] _zz_212_; - wire [1:0] _zz_213_; - wire [1:0] _zz_214_; + wire [26:0] _zz_203_; + wire [6:0] _zz_204_; + wire [1:0] _zz_205_; + wire _zz_206_; + wire _zz_207_; + wire [0:0] _zz_208_; + wire [4:0] _zz_209_; + wire [0:0] _zz_210_; + wire [0:0] _zz_211_; + wire _zz_212_; + wire [0:0] _zz_213_; + wire [20:0] _zz_214_; wire [31:0] _zz_215_; - wire [32:0] _zz_216_; - wire [11:0] _zz_217_; - wire [19:0] _zz_218_; - wire [11:0] _zz_219_; + wire [31:0] _zz_216_; + wire _zz_217_; + wire [0:0] _zz_218_; + wire [1:0] _zz_219_; wire [31:0] _zz_220_; wire [31:0] _zz_221_; wire [31:0] _zz_222_; - wire [11:0] _zz_223_; - wire [19:0] _zz_224_; - wire [11:0] _zz_225_; - wire [2:0] _zz_226_; - wire [2:0] _zz_227_; - wire [2:0] _zz_228_; - wire [3:0] _zz_229_; - wire [0:0] _zz_230_; - wire [0:0] _zz_231_; - wire [0:0] _zz_232_; - wire [0:0] _zz_233_; - wire [0:0] _zz_234_; - wire [0:0] _zz_235_; - wire [26:0] _zz_236_; - wire [6:0] _zz_237_; - wire [1:0] _zz_238_; - wire [0:0] _zz_239_; - wire [7:0] _zz_240_; - wire _zz_241_; - wire [0:0] _zz_242_; + wire [0:0] _zz_223_; + wire [1:0] _zz_224_; + wire [1:0] _zz_225_; + wire [1:0] _zz_226_; + wire _zz_227_; + wire [0:0] _zz_228_; + wire [17:0] _zz_229_; + wire [31:0] _zz_230_; + wire _zz_231_; + wire _zz_232_; + wire [31:0] _zz_233_; + wire [31:0] _zz_234_; + wire _zz_235_; + wire _zz_236_; + wire _zz_237_; + wire _zz_238_; + wire _zz_239_; + wire [0:0] _zz_240_; + wire [0:0] _zz_241_; + wire _zz_242_; wire [0:0] _zz_243_; - wire [31:0] _zz_244_; + wire [15:0] _zz_244_; wire [31:0] _zz_245_; wire [31:0] _zz_246_; wire [31:0] _zz_247_; wire [31:0] _zz_248_; wire [31:0] _zz_249_; - wire [0:0] _zz_250_; - wire [2:0] _zz_251_; - wire [1:0] _zz_252_; - wire [1:0] _zz_253_; - wire _zz_254_; + wire [31:0] _zz_250_; + wire [31:0] _zz_251_; + wire [31:0] _zz_252_; + wire [31:0] _zz_253_; + wire [0:0] _zz_254_; wire [0:0] _zz_255_; - wire [18:0] _zz_256_; - wire [31:0] _zz_257_; - wire [31:0] _zz_258_; - wire [31:0] _zz_259_; - wire _zz_260_; - wire _zz_261_; + wire [1:0] _zz_256_; + wire [1:0] _zz_257_; + wire _zz_258_; + wire [0:0] _zz_259_; + wire [13:0] _zz_260_; + wire [31:0] _zz_261_; wire [31:0] _zz_262_; wire [31:0] _zz_263_; - wire [31:0] _zz_264_; - wire [31:0] _zz_265_; - wire _zz_266_; - wire _zz_267_; - wire [2:0] _zz_268_; - wire [2:0] _zz_269_; - wire _zz_270_; - wire [0:0] _zz_271_; - wire [15:0] _zz_272_; - wire [31:0] _zz_273_; + wire _zz_264_; + wire [0:0] _zz_265_; + wire [1:0] _zz_266_; + wire [0:0] _zz_267_; + wire [0:0] _zz_268_; + wire [1:0] _zz_269_; + wire [1:0] _zz_270_; + wire _zz_271_; + wire [0:0] _zz_272_; + wire [10:0] _zz_273_; wire [31:0] _zz_274_; - wire _zz_275_; - wire _zz_276_; - wire [31:0] _zz_277_; - wire [31:0] _zz_278_; - wire _zz_279_; - wire [0:0] _zz_280_; - wire [0:0] _zz_281_; - wire _zz_282_; - wire [0:0] _zz_283_; - wire [12:0] _zz_284_; - wire [31:0] _zz_285_; - wire _zz_286_; - wire [0:0] _zz_287_; + wire [31:0] _zz_275_; + wire [31:0] _zz_276_; + wire _zz_277_; + wire _zz_278_; + wire [31:0] _zz_279_; + wire [31:0] _zz_280_; + wire [31:0] _zz_281_; + wire [31:0] _zz_282_; + wire _zz_283_; + wire _zz_284_; + wire [0:0] _zz_285_; + wire [0:0] _zz_286_; + wire _zz_287_; wire [0:0] _zz_288_; - wire [0:0] _zz_289_; - wire [0:0] _zz_290_; - wire [2:0] _zz_291_; - wire [2:0] _zz_292_; - wire _zz_293_; + wire [8:0] _zz_289_; + wire [31:0] _zz_290_; + wire _zz_291_; + wire _zz_292_; + wire [0:0] _zz_293_; wire [0:0] _zz_294_; - wire [9:0] _zz_295_; - wire [31:0] _zz_296_; - wire [31:0] _zz_297_; - wire [31:0] _zz_298_; - wire _zz_299_; - wire _zz_300_; + wire [0:0] _zz_295_; + wire [0:0] _zz_296_; + wire _zz_297_; + wire [0:0] _zz_298_; + wire [5:0] _zz_299_; + wire [31:0] _zz_300_; wire [31:0] _zz_301_; wire [31:0] _zz_302_; - wire [0:0] _zz_303_; - wire [0:0] _zz_304_; - wire [5:0] _zz_305_; - wire [5:0] _zz_306_; - wire _zz_307_; - wire [0:0] _zz_308_; - wire [6:0] _zz_309_; - wire [31:0] _zz_310_; - wire [31:0] _zz_311_; - wire _zz_312_; - wire [0:0] _zz_313_; - wire [2:0] _zz_314_; - wire [31:0] _zz_315_; - wire [31:0] _zz_316_; + wire [31:0] _zz_303_; + wire [31:0] _zz_304_; + wire [0:0] _zz_305_; + wire [0:0] _zz_306_; + wire [1:0] _zz_307_; + wire [1:0] _zz_308_; + wire _zz_309_; + wire [0:0] _zz_310_; + wire [2:0] _zz_311_; + wire [31:0] _zz_312_; + wire [31:0] _zz_313_; + wire _zz_314_; + wire _zz_315_; + wire _zz_316_; wire [0:0] _zz_317_; wire [0:0] _zz_318_; wire [1:0] _zz_319_; wire [1:0] _zz_320_; - wire _zz_321_; - wire [0:0] _zz_322_; - wire [3:0] _zz_323_; - wire [31:0] _zz_324_; - wire _zz_325_; - wire _zz_326_; + wire [31:0] _zz_321_; + wire [31:0] _zz_322_; + wire [31:0] _zz_323_; + wire _zz_324_; + wire [0:0] _zz_325_; + wire [12:0] _zz_326_; wire [31:0] _zz_327_; wire [31:0] _zz_328_; wire [31:0] _zz_329_; - wire [31:0] _zz_330_; - wire [31:0] _zz_331_; - wire [0:0] _zz_332_; - wire [0:0] _zz_333_; - wire [1:0] _zz_334_; - wire [1:0] _zz_335_; + wire _zz_330_; + wire [0:0] _zz_331_; + wire [6:0] _zz_332_; + wire [31:0] _zz_333_; + wire [31:0] _zz_334_; + wire [31:0] _zz_335_; wire _zz_336_; wire [0:0] _zz_337_; wire [0:0] _zz_338_; - wire [31:0] _zz_339_; - wire [31:0] _zz_340_; - wire [31:0] _zz_341_; - wire [31:0] _zz_342_; - wire [31:0] _zz_343_; - wire [31:0] _zz_344_; - wire _zz_345_; - wire [0:0] _zz_346_; - wire [0:0] _zz_347_; - wire _zz_348_; - wire _zz_349_; - wire _zz_350_; - wire `Src1CtrlEnum_defaultEncoding_type decode_SRC1_CTRL; - wire `Src1CtrlEnum_defaultEncoding_type _zz_1_; - wire `Src1CtrlEnum_defaultEncoding_type _zz_2_; - wire `Src1CtrlEnum_defaultEncoding_type _zz_3_; - wire `AluBitwiseCtrlEnum_defaultEncoding_type decode_ALU_BITWISE_CTRL; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_4_; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_5_; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_6_; - wire `ShiftCtrlEnum_defaultEncoding_type decode_SHIFT_CTRL; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_7_; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_8_; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_9_; + wire decode_CSR_WRITE_OPCODE; + wire decode_SRC_LESS_UNSIGNED; + wire `EnvCtrlEnum_defaultEncoding_type decode_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_1_; + wire `EnvCtrlEnum_defaultEncoding_type _zz_2_; + wire `EnvCtrlEnum_defaultEncoding_type _zz_3_; wire [31:0] execute_FORMAL_PC_NEXT; wire [31:0] decode_FORMAL_PC_NEXT; - wire `BranchCtrlEnum_defaultEncoding_type _zz_10_; - wire `BranchCtrlEnum_defaultEncoding_type _zz_11_; - wire `EnvCtrlEnum_defaultEncoding_type decode_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_12_; - wire `EnvCtrlEnum_defaultEncoding_type _zz_13_; - wire `EnvCtrlEnum_defaultEncoding_type _zz_14_; - wire decode_FLUSH_ALL; - wire decode_PREDICTION_HAD_BRANCHED2; - wire decode_MEMORY_ENABLE; - wire execute_REGFILE_WRITE_VALID; - wire decode_IS_CSR; wire `Src2CtrlEnum_defaultEncoding_type decode_SRC2_CTRL; - wire `Src2CtrlEnum_defaultEncoding_type _zz_15_; - wire `Src2CtrlEnum_defaultEncoding_type _zz_16_; - wire `Src2CtrlEnum_defaultEncoding_type _zz_17_; - wire decode_CSR_WRITE_OPCODE; + wire `Src2CtrlEnum_defaultEncoding_type _zz_4_; + wire `Src2CtrlEnum_defaultEncoding_type _zz_5_; + wire `Src2CtrlEnum_defaultEncoding_type _zz_6_; + wire decode_IS_CSR; + wire decode_MEMORY_ENABLE; + wire `Src1CtrlEnum_defaultEncoding_type decode_SRC1_CTRL; + wire `Src1CtrlEnum_defaultEncoding_type _zz_7_; + wire `Src1CtrlEnum_defaultEncoding_type _zz_8_; + wire `Src1CtrlEnum_defaultEncoding_type _zz_9_; wire decode_CSR_READ_OPCODE; + wire execute_REGFILE_WRITE_VALID; wire `AluCtrlEnum_defaultEncoding_type decode_ALU_CTRL; - wire `AluCtrlEnum_defaultEncoding_type _zz_18_; - wire `AluCtrlEnum_defaultEncoding_type _zz_19_; - wire `AluCtrlEnum_defaultEncoding_type _zz_20_; - wire decode_SRC_USE_SUB_LESS; - wire decode_SRC_LESS_UNSIGNED; + wire `AluCtrlEnum_defaultEncoding_type _zz_10_; + wire `AluCtrlEnum_defaultEncoding_type _zz_11_; + wire `AluCtrlEnum_defaultEncoding_type _zz_12_; + wire decode_SRC2_FORCE_ZERO; + wire decode_MEMORY_STORE; + wire `BranchCtrlEnum_defaultEncoding_type decode_BRANCH_CTRL; + wire `BranchCtrlEnum_defaultEncoding_type _zz_13_; + wire `BranchCtrlEnum_defaultEncoding_type _zz_14_; + wire `BranchCtrlEnum_defaultEncoding_type _zz_15_; + wire `ShiftCtrlEnum_defaultEncoding_type decode_SHIFT_CTRL; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_16_; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_17_; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_18_; + wire `AluBitwiseCtrlEnum_defaultEncoding_type decode_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_19_; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_20_; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_21_; wire execute_CSR_READ_OPCODE; wire execute_CSR_WRITE_OPCODE; wire execute_IS_CSR; - wire _zz_21_; wire _zz_22_; + wire _zz_23_; wire `EnvCtrlEnum_defaultEncoding_type execute_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_23_; + wire `EnvCtrlEnum_defaultEncoding_type _zz_24_; wire [31:0] execute_BRANCH_CALC; wire execute_BRANCH_DO; - wire [31:0] _zz_24_; + wire [31:0] _zz_25_; wire [31:0] execute_PC; - wire execute_PREDICTION_HAD_BRANCHED2; - wire _zz_25_; wire [31:0] execute_RS1; - wire execute_BRANCH_COND_RESULT; wire `BranchCtrlEnum_defaultEncoding_type execute_BRANCH_CTRL; wire `BranchCtrlEnum_defaultEncoding_type _zz_26_; wire _zz_27_; - wire _zz_28_; wire `ShiftCtrlEnum_defaultEncoding_type execute_SHIFT_CTRL; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_29_; - wire _zz_30_; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_28_; + wire _zz_29_; + wire [31:0] _zz_30_; wire [31:0] _zz_31_; - wire [31:0] _zz_32_; wire execute_SRC_LESS_UNSIGNED; + wire execute_SRC2_FORCE_ZERO; wire execute_SRC_USE_SUB_LESS; wire `Src2CtrlEnum_defaultEncoding_type execute_SRC2_CTRL; - wire `Src2CtrlEnum_defaultEncoding_type _zz_33_; - wire [31:0] _zz_34_; + wire `Src2CtrlEnum_defaultEncoding_type _zz_32_; + wire [31:0] _zz_33_; wire `Src1CtrlEnum_defaultEncoding_type execute_SRC1_CTRL; - wire `Src1CtrlEnum_defaultEncoding_type _zz_35_; - wire [31:0] _zz_36_; + wire `Src1CtrlEnum_defaultEncoding_type _zz_34_; + wire [31:0] _zz_35_; + wire decode_SRC_USE_SUB_LESS; + wire decode_SRC_ADD_ZERO; + wire _zz_36_; wire [31:0] execute_SRC_ADD_SUB; wire execute_SRC_LESS; wire `AluCtrlEnum_defaultEncoding_type execute_ALU_CTRL; @@ -678,46 +640,52 @@ module VexRiscv ( wire [31:0] _zz_41_; wire [31:0] _zz_42_; reg decode_REGFILE_WRITE_VALID; + wire decode_LEGAL_INSTRUCTION; + wire decode_INSTRUCTION_READY; wire _zz_43_; - wire `BranchCtrlEnum_defaultEncoding_type _zz_44_; - wire `AluCtrlEnum_defaultEncoding_type _zz_45_; + wire _zz_44_; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_45_; wire _zz_46_; wire _zz_47_; wire _zz_48_; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_49_; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_50_; - wire _zz_51_; - wire `Src1CtrlEnum_defaultEncoding_type _zz_52_; - wire `EnvCtrlEnum_defaultEncoding_type _zz_53_; + wire _zz_49_; + wire `Src1CtrlEnum_defaultEncoding_type _zz_50_; + wire `BranchCtrlEnum_defaultEncoding_type _zz_51_; + wire `EnvCtrlEnum_defaultEncoding_type _zz_52_; + wire `AluCtrlEnum_defaultEncoding_type _zz_53_; wire _zz_54_; wire `Src2CtrlEnum_defaultEncoding_type _zz_55_; - reg [31:0] _zz_56_; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_56_; + wire _zz_57_; + wire _zz_58_; + reg [31:0] _zz_59_; wire [1:0] execute_MEMORY_ADDRESS_LOW; wire [31:0] execute_MEMORY_READ_DATA; wire [31:0] execute_REGFILE_WRITE_DATA; - wire [31:0] _zz_57_; - wire [1:0] _zz_58_; - wire [31:0] execute_RS2; + wire [31:0] _zz_60_; wire [31:0] execute_SRC_ADD; + wire [1:0] _zz_61_; + wire [31:0] execute_RS2; wire [31:0] execute_INSTRUCTION; - wire execute_ALIGNEMENT_FAULT; + wire execute_MEMORY_STORE; wire execute_MEMORY_ENABLE; - wire _zz_59_; - wire execute_FLUSH_ALL; + wire execute_ALIGNEMENT_FAULT; + wire _zz_62_; + wire decode_FLUSH_ALL; reg IBusCachedPlugin_rsp_issueDetected; - wire `BranchCtrlEnum_defaultEncoding_type decode_BRANCH_CTRL; - wire `BranchCtrlEnum_defaultEncoding_type _zz_60_; - reg [31:0] _zz_61_; - wire [31:0] _zz_62_; - wire [31:0] _zz_63_; - wire [31:0] _zz_64_; + reg _zz_63_; + reg _zz_64_; + reg _zz_65_; + reg [31:0] _zz_66_; + wire [31:0] _zz_67_; + wire [31:0] _zz_68_; + wire [31:0] _zz_69_; wire [31:0] decode_PC /* verilator public */ ; wire [31:0] decode_INSTRUCTION /* verilator public */ ; wire decode_arbitration_haltItself /* verilator public */ ; reg decode_arbitration_haltByOther; reg decode_arbitration_removeIt; reg decode_arbitration_flushAll /* verilator public */ ; - wire decode_arbitration_redoIt; wire decode_arbitration_isValid /* verilator public */ ; wire decode_arbitration_isStuck; wire decode_arbitration_isStuckByOthers; @@ -728,42 +696,56 @@ module VexRiscv ( wire execute_arbitration_haltByOther; reg execute_arbitration_removeIt; wire execute_arbitration_flushAll; - wire execute_arbitration_redoIt; reg execute_arbitration_isValid; wire execute_arbitration_isStuck; wire execute_arbitration_isStuckByOthers; wire execute_arbitration_isFlushed; wire execute_arbitration_isMoving; wire execute_arbitration_isFiring; - reg _zz_65_; - wire _zz_66_; - wire _zz_67_; - wire [31:0] _zz_68_; - wire _zz_69_; - wire _zz_70_; - wire [31:0] _zz_71_; - wire [31:0] _zz_72_; - reg _zz_73_; - wire _zz_74_; - reg _zz_75_; - reg _zz_76_; - reg [31:0] _zz_77_; + reg IBusCachedPlugin_fetcherHalt; + wire IBusCachedPlugin_fetcherflushIt; + reg IBusCachedPlugin_incomingInstruction; + wire IBusCachedPlugin_pcValids_0; + wire IBusCachedPlugin_pcValids_1; + wire IBusCachedPlugin_redoBranch_valid; + wire [31:0] IBusCachedPlugin_redoBranch_payload; + reg IBusCachedPlugin_decodeExceptionPort_valid; + reg [3:0] IBusCachedPlugin_decodeExceptionPort_payload_code; + wire [31:0] IBusCachedPlugin_decodeExceptionPort_payload_badAddr; + reg DBusSimplePlugin_memoryExceptionPort_valid; + reg [3:0] DBusSimplePlugin_memoryExceptionPort_payload_code; + wire [31:0] DBusSimplePlugin_memoryExceptionPort_payload_badAddr; + wire decodeExceptionPort_valid; + wire [3:0] decodeExceptionPort_payload_code; + wire [31:0] decodeExceptionPort_payload_badAddr; + wire BranchPlugin_jumpInterface_valid; + wire [31:0] BranchPlugin_jumpInterface_payload; + reg BranchPlugin_branchExceptionPort_valid; + wire [3:0] BranchPlugin_branchExceptionPort_payload_code; + wire [31:0] BranchPlugin_branchExceptionPort_payload_badAddr; + reg CsrPlugin_jumpInterface_valid; + reg [31:0] CsrPlugin_jumpInterface_payload; + wire CsrPlugin_exceptionPendings_0; + wire CsrPlugin_exceptionPendings_1; wire externalInterrupt; wire contextSwitching; reg [1:0] CsrPlugin_privilege; - reg _zz_78_; - reg [3:0] _zz_79_; + wire CsrPlugin_forceMachineWire; + reg CsrPlugin_selfException_valid; + reg [3:0] CsrPlugin_selfException_payload_code; + wire [31:0] CsrPlugin_selfException_payload_badAddr; + wire CsrPlugin_allowInterrupts; + wire CsrPlugin_allowException; wire IBusCachedPlugin_jump_pcLoad_valid; wire [31:0] IBusCachedPlugin_jump_pcLoad_payload; - wire [3:0] _zz_80_; - wire [3:0] _zz_81_; - wire _zz_82_; - wire _zz_83_; - wire _zz_84_; + wire [2:0] _zz_70_; + wire [2:0] _zz_71_; + wire _zz_72_; + wire _zz_73_; wire IBusCachedPlugin_fetchPc_preOutput_valid; wire IBusCachedPlugin_fetchPc_preOutput_ready; wire [31:0] IBusCachedPlugin_fetchPc_preOutput_payload; - wire _zz_85_; + wire _zz_74_; wire IBusCachedPlugin_fetchPc_output_valid; wire IBusCachedPlugin_fetchPc_output_ready; wire [31:0] IBusCachedPlugin_fetchPc_output_payload; @@ -772,7 +754,7 @@ module VexRiscv ( reg IBusCachedPlugin_fetchPc_propagatePc; reg [31:0] IBusCachedPlugin_fetchPc_pc; reg IBusCachedPlugin_fetchPc_samplePcNext; - reg _zz_86_; + reg _zz_75_; wire IBusCachedPlugin_iBusRsp_stages_0_input_valid; wire IBusCachedPlugin_iBusRsp_stages_0_input_ready; wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_input_payload; @@ -781,14 +763,6 @@ module VexRiscv ( wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_output_payload; reg IBusCachedPlugin_iBusRsp_stages_0_halt; wire IBusCachedPlugin_iBusRsp_stages_0_inputSample; - wire IBusCachedPlugin_iBusRsp_stages_1_input_valid; - wire IBusCachedPlugin_iBusRsp_stages_1_input_ready; - wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_input_payload; - wire IBusCachedPlugin_iBusRsp_stages_1_output_valid; - wire IBusCachedPlugin_iBusRsp_stages_1_output_ready; - wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_output_payload; - reg IBusCachedPlugin_iBusRsp_stages_1_halt; - wire IBusCachedPlugin_iBusRsp_stages_1_inputSample; wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid; wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready; wire [31:0] IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload; @@ -797,16 +771,12 @@ module VexRiscv ( wire [31:0] IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_payload; reg IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt; wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_inputSample; - wire _zz_87_; - wire _zz_88_; - wire _zz_89_; - wire _zz_90_; - wire _zz_91_; - reg _zz_92_; - wire _zz_93_; - reg _zz_94_; - reg [31:0] _zz_95_; - wire IBusCachedPlugin_iBusRsp_readyForError; + wire _zz_76_; + wire _zz_77_; + wire _zz_78_; + wire _zz_79_; + reg _zz_80_; + reg IBusCachedPlugin_iBusRsp_readyForError; wire IBusCachedPlugin_iBusRsp_decodeInput_valid; wire IBusCachedPlugin_iBusRsp_decodeInput_ready; wire [31:0] IBusCachedPlugin_iBusRsp_decodeInput_payload_pc; @@ -815,14 +785,7 @@ module VexRiscv ( wire IBusCachedPlugin_iBusRsp_decodeInput_payload_isRvc; reg IBusCachedPlugin_injector_nextPcCalc_valids_0; reg IBusCachedPlugin_injector_nextPcCalc_valids_1; - reg IBusCachedPlugin_injector_nextPcCalc_valids_2; reg IBusCachedPlugin_injector_decodeRemoved; - wire _zz_96_; - reg [18:0] _zz_97_; - wire _zz_98_; - reg [10:0] _zz_99_; - wire _zz_100_; - reg [18:0] _zz_101_; wire iBus_cmd_valid; wire iBus_cmd_ready; reg [31:0] iBus_cmd_payload_address; @@ -832,7 +795,6 @@ module VexRiscv ( wire iBus_rsp_payload_error; wire IBusCachedPlugin_s0_tightlyCoupledHit; reg IBusCachedPlugin_s1_tightlyCoupledHit; - reg IBusCachedPlugin_s2_tightlyCoupledHit; wire IBusCachedPlugin_rsp_iBusRspOutputHalt; reg IBusCachedPlugin_rsp_redoFetch; wire dBus_cmd_valid; @@ -845,44 +807,45 @@ module VexRiscv ( wire dBus_rsp_error; wire [31:0] dBus_rsp_data; reg execute_DBusSimplePlugin_cmdSent; - reg [31:0] _zz_102_; - reg [3:0] _zz_103_; + reg execute_DBusSimplePlugin_skipCmd; + reg [31:0] _zz_81_; + reg [3:0] _zz_82_; wire [3:0] execute_DBusSimplePlugin_formalMask; reg [31:0] execute_DBusSimplePlugin_rspShifted; - wire _zz_104_; - reg [31:0] _zz_105_; - wire _zz_106_; - reg [31:0] _zz_107_; + wire _zz_83_; + reg [31:0] _zz_84_; + wire _zz_85_; + reg [31:0] _zz_86_; reg [31:0] execute_DBusSimplePlugin_rspFormated; - wire [24:0] _zz_108_; - wire _zz_109_; - wire _zz_110_; - wire _zz_111_; - wire _zz_112_; - wire `Src2CtrlEnum_defaultEncoding_type _zz_113_; - wire `EnvCtrlEnum_defaultEncoding_type _zz_114_; - wire `Src1CtrlEnum_defaultEncoding_type _zz_115_; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_116_; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_117_; - wire `AluCtrlEnum_defaultEncoding_type _zz_118_; - wire `BranchCtrlEnum_defaultEncoding_type _zz_119_; + wire [26:0] _zz_87_; + wire _zz_88_; + wire _zz_89_; + wire _zz_90_; + wire _zz_91_; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_92_; + wire `Src2CtrlEnum_defaultEncoding_type _zz_93_; + wire `AluCtrlEnum_defaultEncoding_type _zz_94_; + wire `EnvCtrlEnum_defaultEncoding_type _zz_95_; + wire `BranchCtrlEnum_defaultEncoding_type _zz_96_; + wire `Src1CtrlEnum_defaultEncoding_type _zz_97_; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_98_; wire [4:0] execute_RegFilePlugin_regFileReadAddress1; wire [4:0] execute_RegFilePlugin_regFileReadAddress2; - wire _zz_120_; + wire _zz_99_; wire [31:0] execute_RegFilePlugin_rs1Data; wire [31:0] execute_RegFilePlugin_rs2Data; wire execute_RegFilePlugin_regFileWrite_valid /* verilator public */ ; wire [4:0] execute_RegFilePlugin_regFileWrite_payload_address /* verilator public */ ; wire [31:0] execute_RegFilePlugin_regFileWrite_payload_data /* verilator public */ ; reg [31:0] execute_IntAluPlugin_bitwise; - reg [31:0] _zz_121_; - reg [31:0] _zz_122_; - wire _zz_123_; - reg [19:0] _zz_124_; - wire _zz_125_; - reg [19:0] _zz_126_; - reg [31:0] _zz_127_; - wire [31:0] execute_SrcPlugin_addSub; + reg [31:0] _zz_100_; + reg [31:0] _zz_101_; + wire _zz_102_; + reg [19:0] _zz_103_; + wire _zz_104_; + reg [19:0] _zz_105_; + reg [31:0] _zz_106_; + reg [31:0] execute_SrcPlugin_addSub; wire execute_SrcPlugin_less; reg execute_LightShifterPlugin_isActive; wire execute_LightShifterPlugin_isShift; @@ -891,27 +854,20 @@ module VexRiscv ( reg [31:0] execute_LightShifterPlugin_shiftReg; wire [31:0] execute_LightShifterPlugin_shiftInput; wire execute_LightShifterPlugin_done; - reg [31:0] _zz_128_; + reg [31:0] _zz_107_; wire execute_BranchPlugin_eq; - wire [2:0] _zz_129_; - reg _zz_130_; - reg _zz_131_; - wire _zz_132_; - reg [19:0] _zz_133_; - wire _zz_134_; - reg [10:0] _zz_135_; - wire _zz_136_; - reg [18:0] _zz_137_; - reg _zz_138_; - wire execute_BranchPlugin_missAlignedTarget; - reg [31:0] execute_BranchPlugin_branch_src1; - reg [31:0] execute_BranchPlugin_branch_src2; - wire _zz_139_; - reg [19:0] _zz_140_; - wire _zz_141_; - reg [10:0] _zz_142_; - wire _zz_143_; - reg [18:0] _zz_144_; + wire [2:0] _zz_108_; + reg _zz_109_; + reg _zz_110_; + wire [31:0] execute_BranchPlugin_branch_src1; + wire _zz_111_; + reg [10:0] _zz_112_; + wire _zz_113_; + reg [19:0] _zz_114_; + wire _zz_115_; + reg [18:0] _zz_116_; + reg [31:0] _zz_117_; + wire [31:0] execute_BranchPlugin_branch_src2; wire [31:0] execute_BranchPlugin_branchAdder; wire [1:0] CsrPlugin_misa_base; wire [25:0] CsrPlugin_misa_extensions; @@ -933,29 +889,24 @@ module VexRiscv ( reg [31:0] CsrPlugin_mtval; reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000; reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000; - wire [31:0] CsrPlugin_medeleg; - wire [31:0] CsrPlugin_mideleg; - wire _zz_145_; - wire _zz_146_; - wire _zz_147_; - wire CsrPlugin_exceptionPortCtrl_exceptionValids_decode; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode; reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute; - wire CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; reg [3:0] CsrPlugin_exceptionPortCtrl_exceptionContext_code; reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; + wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped; wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; - wire execute_exception_agregat_valid; - wire [3:0] execute_exception_agregat_payload_code; - wire [31:0] execute_exception_agregat_payload_badAddr; - wire [2:0] _zz_148_; - wire [2:0] _zz_149_; - wire _zz_150_; - wire _zz_151_; - wire [1:0] _zz_152_; + wire [1:0] _zz_118_; + wire _zz_119_; + wire [2:0] _zz_120_; + wire [2:0] _zz_121_; + wire _zz_122_; + wire _zz_123_; + wire [1:0] _zz_124_; reg CsrPlugin_interrupt; reg [3:0] CsrPlugin_interruptCode /* verilator public */ ; - wire [1:0] CsrPlugin_interruptTargetPrivilege; + reg [1:0] CsrPlugin_interruptTargetPrivilege; wire CsrPlugin_exception; wire CsrPlugin_lastStageWasWfi; reg CsrPlugin_pipelineLiberator_done; @@ -963,6 +914,9 @@ module VexRiscv ( reg CsrPlugin_hadException; reg [1:0] CsrPlugin_targetPrivilege; reg [3:0] CsrPlugin_trapCause; + reg [1:0] CsrPlugin_xtvec_mode; + reg [29:0] CsrPlugin_xtvec_base; + wire execute_CsrPlugin_inWfi /* verilator public */ ; wire execute_CsrPlugin_blockedBySideEffects; reg execute_CsrPlugin_illegalAccess; reg execute_CsrPlugin_illegalInstruction; @@ -971,32 +925,33 @@ module VexRiscv ( wire execute_CsrPlugin_readInstruction; wire execute_CsrPlugin_writeEnable; wire execute_CsrPlugin_readEnable; + wire [31:0] execute_CsrPlugin_readToWriteData; reg [31:0] execute_CsrPlugin_writeData; wire [11:0] execute_CsrPlugin_csrAddress; - reg [31:0] _zz_153_; + reg [31:0] _zz_125_; reg [31:0] externalInterruptArray_regNext; - wire [31:0] _zz_154_; - reg decode_to_execute_SRC_LESS_UNSIGNED; - reg decode_to_execute_SRC_USE_SUB_LESS; - reg `AluCtrlEnum_defaultEncoding_type decode_to_execute_ALU_CTRL; - reg [31:0] decode_to_execute_INSTRUCTION; - reg decode_to_execute_CSR_READ_OPCODE; - reg decode_to_execute_CSR_WRITE_OPCODE; - reg `Src2CtrlEnum_defaultEncoding_type decode_to_execute_SRC2_CTRL; - reg decode_to_execute_IS_CSR; - reg decode_to_execute_REGFILE_WRITE_VALID; - reg decode_to_execute_MEMORY_ENABLE; - reg [31:0] decode_to_execute_PC; - reg decode_to_execute_PREDICTION_HAD_BRANCHED2; - reg decode_to_execute_FLUSH_ALL; - reg `EnvCtrlEnum_defaultEncoding_type decode_to_execute_ENV_CTRL; - reg `BranchCtrlEnum_defaultEncoding_type decode_to_execute_BRANCH_CTRL; - reg [31:0] decode_to_execute_FORMAL_PC_NEXT; - reg `ShiftCtrlEnum_defaultEncoding_type decode_to_execute_SHIFT_CTRL; + wire [31:0] _zz_126_; reg `AluBitwiseCtrlEnum_defaultEncoding_type decode_to_execute_ALU_BITWISE_CTRL; + reg `ShiftCtrlEnum_defaultEncoding_type decode_to_execute_SHIFT_CTRL; + reg `BranchCtrlEnum_defaultEncoding_type decode_to_execute_BRANCH_CTRL; + reg decode_to_execute_MEMORY_STORE; + reg decode_to_execute_SRC2_FORCE_ZERO; + reg `AluCtrlEnum_defaultEncoding_type decode_to_execute_ALU_CTRL; + reg decode_to_execute_SRC_USE_SUB_LESS; + reg decode_to_execute_REGFILE_WRITE_VALID; + reg decode_to_execute_CSR_READ_OPCODE; reg `Src1CtrlEnum_defaultEncoding_type decode_to_execute_SRC1_CTRL; - reg [2:0] _zz_155_; - reg _zz_156_; + reg decode_to_execute_MEMORY_ENABLE; + reg decode_to_execute_IS_CSR; + reg `Src2CtrlEnum_defaultEncoding_type decode_to_execute_SRC2_CTRL; + reg [31:0] decode_to_execute_PC; + reg [31:0] decode_to_execute_INSTRUCTION; + reg [31:0] decode_to_execute_FORMAL_PC_NEXT; + reg `EnvCtrlEnum_defaultEncoding_type decode_to_execute_ENV_CTRL; + reg decode_to_execute_SRC_LESS_UNSIGNED; + reg decode_to_execute_CSR_WRITE_OPCODE; + reg [2:0] _zz_127_; + reg _zz_128_; reg [31:0] iBusWishbone_DAT_MISO_regNext; wire dBus_cmd_halfPipe_valid; wire dBus_cmd_halfPipe_ready; @@ -1010,246 +965,263 @@ module VexRiscv ( reg [31:0] dBus_cmd_halfPipe_regs_payload_address; reg [31:0] dBus_cmd_halfPipe_regs_payload_data; reg [1:0] dBus_cmd_halfPipe_regs_payload_size; - reg [3:0] _zz_157_; + reg [3:0] _zz_129_; `ifndef SYNTHESIS - reg [95:0] decode_SRC1_CTRL_string; - reg [95:0] _zz_1__string; - reg [95:0] _zz_2__string; - reg [95:0] _zz_3__string; - reg [39:0] decode_ALU_BITWISE_CTRL_string; - reg [39:0] _zz_4__string; - reg [39:0] _zz_5__string; - reg [39:0] _zz_6__string; - reg [71:0] decode_SHIFT_CTRL_string; - reg [71:0] _zz_7__string; - reg [71:0] _zz_8__string; - reg [71:0] _zz_9__string; - reg [31:0] _zz_10__string; - reg [31:0] _zz_11__string; reg [47:0] decode_ENV_CTRL_string; - reg [47:0] _zz_12__string; - reg [47:0] _zz_13__string; - reg [47:0] _zz_14__string; + reg [47:0] _zz_1__string; + reg [47:0] _zz_2__string; + reg [47:0] _zz_3__string; reg [23:0] decode_SRC2_CTRL_string; - reg [23:0] _zz_15__string; - reg [23:0] _zz_16__string; - reg [23:0] _zz_17__string; + reg [23:0] _zz_4__string; + reg [23:0] _zz_5__string; + reg [23:0] _zz_6__string; + reg [95:0] decode_SRC1_CTRL_string; + reg [95:0] _zz_7__string; + reg [95:0] _zz_8__string; + reg [95:0] _zz_9__string; reg [63:0] decode_ALU_CTRL_string; - reg [63:0] _zz_18__string; - reg [63:0] _zz_19__string; - reg [63:0] _zz_20__string; + reg [63:0] _zz_10__string; + reg [63:0] _zz_11__string; + reg [63:0] _zz_12__string; + reg [31:0] decode_BRANCH_CTRL_string; + reg [31:0] _zz_13__string; + reg [31:0] _zz_14__string; + reg [31:0] _zz_15__string; + reg [71:0] decode_SHIFT_CTRL_string; + reg [71:0] _zz_16__string; + reg [71:0] _zz_17__string; + reg [71:0] _zz_18__string; + reg [39:0] decode_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_19__string; + reg [39:0] _zz_20__string; + reg [39:0] _zz_21__string; reg [47:0] execute_ENV_CTRL_string; - reg [47:0] _zz_23__string; + reg [47:0] _zz_24__string; reg [31:0] execute_BRANCH_CTRL_string; reg [31:0] _zz_26__string; reg [71:0] execute_SHIFT_CTRL_string; - reg [71:0] _zz_29__string; + reg [71:0] _zz_28__string; reg [23:0] execute_SRC2_CTRL_string; - reg [23:0] _zz_33__string; + reg [23:0] _zz_32__string; reg [95:0] execute_SRC1_CTRL_string; - reg [95:0] _zz_35__string; + reg [95:0] _zz_34__string; reg [63:0] execute_ALU_CTRL_string; reg [63:0] _zz_37__string; reg [39:0] execute_ALU_BITWISE_CTRL_string; reg [39:0] _zz_39__string; - reg [31:0] _zz_44__string; - reg [63:0] _zz_45__string; - reg [39:0] _zz_49__string; - reg [71:0] _zz_50__string; - reg [95:0] _zz_52__string; - reg [47:0] _zz_53__string; + reg [39:0] _zz_45__string; + reg [95:0] _zz_50__string; + reg [31:0] _zz_51__string; + reg [47:0] _zz_52__string; + reg [63:0] _zz_53__string; reg [23:0] _zz_55__string; - reg [31:0] decode_BRANCH_CTRL_string; - reg [31:0] _zz_60__string; - reg [23:0] _zz_113__string; - reg [47:0] _zz_114__string; - reg [95:0] _zz_115__string; - reg [71:0] _zz_116__string; - reg [39:0] _zz_117__string; - reg [63:0] _zz_118__string; - reg [31:0] _zz_119__string; + reg [71:0] _zz_56__string; + reg [71:0] _zz_92__string; + reg [23:0] _zz_93__string; + reg [63:0] _zz_94__string; + reg [47:0] _zz_95__string; + reg [31:0] _zz_96__string; + reg [95:0] _zz_97__string; + reg [39:0] _zz_98__string; + reg [39:0] decode_to_execute_ALU_BITWISE_CTRL_string; + reg [71:0] decode_to_execute_SHIFT_CTRL_string; + reg [31:0] decode_to_execute_BRANCH_CTRL_string; reg [63:0] decode_to_execute_ALU_CTRL_string; + reg [95:0] decode_to_execute_SRC1_CTRL_string; reg [23:0] decode_to_execute_SRC2_CTRL_string; reg [47:0] decode_to_execute_ENV_CTRL_string; - reg [31:0] decode_to_execute_BRANCH_CTRL_string; - reg [71:0] decode_to_execute_SHIFT_CTRL_string; - reg [39:0] decode_to_execute_ALU_BITWISE_CTRL_string; - reg [95:0] decode_to_execute_SRC1_CTRL_string; `endif reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; - assign _zz_179_ = ((execute_arbitration_isValid && execute_LightShifterPlugin_isShift) && (execute_SRC2[4 : 0] != (5'b00000))); - assign _zz_180_ = (! execute_arbitration_isStuckByOthers); - assign _zz_181_ = (CsrPlugin_hadException || CsrPlugin_interruptJump); - assign _zz_182_ = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); - assign _zz_183_ = (IBusCachedPlugin_fetchPc_preOutput_valid && IBusCachedPlugin_fetchPc_preOutput_ready); - assign _zz_184_ = (iBus_cmd_valid || (_zz_155_ != (3'b000))); - assign _zz_185_ = (! dBus_cmd_halfPipe_regs_valid); - assign _zz_186_ = execute_INSTRUCTION[13 : 12]; - assign _zz_187_ = execute_INSTRUCTION[29 : 28]; - assign _zz_188_ = execute_INSTRUCTION[13]; - assign _zz_189_ = (_zz_80_ - (4'b0001)); - assign _zz_190_ = {IBusCachedPlugin_fetchPc_inc,(2'b00)}; - assign _zz_191_ = {29'd0, _zz_190_}; - assign _zz_192_ = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_193_ = {{_zz_97_,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_194_ = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; - assign _zz_195_ = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_196_ = _zz_108_[3 : 3]; - assign _zz_197_ = _zz_108_[9 : 9]; - assign _zz_198_ = _zz_108_[14 : 14]; - assign _zz_199_ = _zz_108_[15 : 15]; - assign _zz_200_ = _zz_108_[16 : 16]; - assign _zz_201_ = _zz_108_[24 : 24]; - assign _zz_202_ = execute_SRC_LESS; - assign _zz_203_ = (3'b100); - assign _zz_204_ = execute_INSTRUCTION[19 : 15]; - assign _zz_205_ = execute_INSTRUCTION[31 : 20]; - assign _zz_206_ = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; - assign _zz_207_ = ($signed(_zz_208_) + $signed(_zz_212_)); - assign _zz_208_ = ($signed(_zz_209_) + $signed(_zz_210_)); - assign _zz_209_ = execute_SRC1; - assign _zz_210_ = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); - assign _zz_211_ = (execute_SRC_USE_SUB_LESS ? _zz_213_ : _zz_214_); - assign _zz_212_ = {{30{_zz_211_[1]}}, _zz_211_}; - assign _zz_213_ = (2'b01); - assign _zz_214_ = (2'b00); - assign _zz_215_ = (_zz_216_ >>> 1); - assign _zz_216_ = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_LightShifterPlugin_shiftInput[31]),execute_LightShifterPlugin_shiftInput}; - assign _zz_217_ = execute_INSTRUCTION[31 : 20]; - assign _zz_218_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz_219_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_220_ = {_zz_133_,execute_INSTRUCTION[31 : 20]}; - assign _zz_221_ = {{_zz_135_,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; - assign _zz_222_ = {{_zz_137_,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_223_ = execute_INSTRUCTION[31 : 20]; - assign _zz_224_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz_225_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_226_ = (3'b100); - assign _zz_227_ = (_zz_148_ - (3'b001)); - assign _zz_228_ = (execute_INSTRUCTION[5] ? (3'b110) : (3'b100)); - assign _zz_229_ = {1'd0, _zz_228_}; - assign _zz_230_ = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_231_ = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_232_ = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_233_ = execute_CsrPlugin_writeData[11 : 11]; - assign _zz_234_ = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_235_ = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_236_ = (iBus_cmd_payload_address >>> 5); - assign _zz_237_ = ({3'd0,_zz_157_} <<< dBus_cmd_halfPipe_payload_address[1 : 0]); - assign _zz_238_ = {_zz_84_,_zz_83_}; - assign _zz_239_ = decode_INSTRUCTION[31]; - assign _zz_240_ = decode_INSTRUCTION[19 : 12]; - assign _zz_241_ = decode_INSTRUCTION[20]; - assign _zz_242_ = decode_INSTRUCTION[31]; - assign _zz_243_ = decode_INSTRUCTION[7]; - assign _zz_244_ = (decode_INSTRUCTION & (32'b00000000000000000001000001010000)); - assign _zz_245_ = (32'b00000000000000000001000001010000); - assign _zz_246_ = (decode_INSTRUCTION & (32'b00000000000000000010000001010000)); - assign _zz_247_ = (32'b00000000000000000010000001010000); - assign _zz_248_ = (decode_INSTRUCTION & (32'b00000000000000000000000000010000)); - assign _zz_249_ = (32'b00000000000000000000000000010000); - assign _zz_250_ = ((decode_INSTRUCTION & _zz_257_) == (32'b00000000000000000000000000000000)); - assign _zz_251_ = {(_zz_258_ == _zz_259_),{_zz_260_,_zz_261_}}; - assign _zz_252_ = {(_zz_262_ == _zz_263_),(_zz_264_ == _zz_265_)}; - assign _zz_253_ = (2'b00); - assign _zz_254_ = ({_zz_112_,_zz_266_} != (2'b00)); - assign _zz_255_ = (_zz_267_ != (1'b0)); - assign _zz_256_ = {(_zz_268_ != _zz_269_),{_zz_270_,{_zz_271_,_zz_272_}}}; - assign _zz_257_ = (32'b00000000000000000000000001000100); - assign _zz_258_ = (decode_INSTRUCTION & (32'b00000000000000000000000000011000)); - assign _zz_259_ = (32'b00000000000000000000000000000000); - assign _zz_260_ = ((decode_INSTRUCTION & (32'b00000000000000000110000000000100)) == (32'b00000000000000000010000000000000)); - assign _zz_261_ = ((decode_INSTRUCTION & (32'b00000000000000000101000000000100)) == (32'b00000000000000000001000000000000)); - assign _zz_262_ = (decode_INSTRUCTION & (32'b00000000000000000000000000110100)); - assign _zz_263_ = (32'b00000000000000000000000000100000); - assign _zz_264_ = (decode_INSTRUCTION & (32'b00000000000000000000000001100100)); - assign _zz_265_ = (32'b00000000000000000000000000100000); - assign _zz_266_ = ((decode_INSTRUCTION & (32'b00000000000000000101000000010100)) == (32'b00000000000000000000000000000100)); - assign _zz_267_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001011000)) == (32'b00000000000000000000000001000000)); - assign _zz_268_ = {(_zz_273_ == _zz_274_),{_zz_275_,_zz_276_}}; - assign _zz_269_ = (3'b000); - assign _zz_270_ = ((_zz_277_ == _zz_278_) != (1'b0)); - assign _zz_271_ = (_zz_279_ != (1'b0)); - assign _zz_272_ = {(_zz_280_ != _zz_281_),{_zz_282_,{_zz_283_,_zz_284_}}}; - assign _zz_273_ = (decode_INSTRUCTION & (32'b00000000000000000000000001100100)); - assign _zz_274_ = (32'b00000000000000000000000000100100); - assign _zz_275_ = ((decode_INSTRUCTION & (32'b00000000000000000100000000010100)) == (32'b00000000000000000100000000010000)); - assign _zz_276_ = ((decode_INSTRUCTION & (32'b00000000000000000011000000010100)) == (32'b00000000000000000001000000010000)); - assign _zz_277_ = (decode_INSTRUCTION & (32'b00000000000000000110000000010100)); - assign _zz_278_ = (32'b00000000000000000010000000010000); - assign _zz_279_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001011000)) == (32'b00000000000000000000000000000000)); - assign _zz_280_ = ((decode_INSTRUCTION & _zz_285_) == (32'b00000000000000000000000000001000)); - assign _zz_281_ = (1'b0); - assign _zz_282_ = ({_zz_286_,{_zz_287_,_zz_288_}} != (3'b000)); - assign _zz_283_ = ({_zz_289_,_zz_290_} != (2'b00)); - assign _zz_284_ = {(_zz_291_ != _zz_292_),{_zz_293_,{_zz_294_,_zz_295_}}}; - assign _zz_285_ = (32'b00000000000000000001000001001000); - assign _zz_286_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001000100)) == (32'b00000000000000000000000001000000)); - assign _zz_287_ = ((decode_INSTRUCTION & _zz_296_) == (32'b01000000000000000000000000110000)); - assign _zz_288_ = ((decode_INSTRUCTION & _zz_297_) == (32'b00000000000000000010000000010000)); - assign _zz_289_ = ((decode_INSTRUCTION & _zz_298_) == (32'b00000000000000000001000000000000)); - assign _zz_290_ = _zz_110_; - assign _zz_291_ = {_zz_110_,{_zz_299_,_zz_300_}}; - assign _zz_292_ = (3'b000); - assign _zz_293_ = ((_zz_301_ == _zz_302_) != (1'b0)); - assign _zz_294_ = ({_zz_303_,_zz_304_} != (2'b00)); - assign _zz_295_ = {(_zz_305_ != _zz_306_),{_zz_307_,{_zz_308_,_zz_309_}}}; - assign _zz_296_ = (32'b01000000000000000000000000110000); - assign _zz_297_ = (32'b00000000000000000010000000010100); - assign _zz_298_ = (32'b00000000000000000001000000000000); - assign _zz_299_ = ((decode_INSTRUCTION & (32'b00000000000000000011000000000000)) == (32'b00000000000000000001000000000000)); - assign _zz_300_ = ((decode_INSTRUCTION & (32'b00000000000000000011000000000000)) == (32'b00000000000000000010000000000000)); - assign _zz_301_ = (decode_INSTRUCTION & (32'b00000000000000000111000001010100)); - assign _zz_302_ = (32'b00000000000000000101000000010000); - assign _zz_303_ = ((decode_INSTRUCTION & _zz_310_) == (32'b01000000000000000001000000010000)); - assign _zz_304_ = ((decode_INSTRUCTION & _zz_311_) == (32'b00000000000000000001000000010000)); - assign _zz_305_ = {_zz_112_,{_zz_312_,{_zz_313_,_zz_314_}}}; - assign _zz_306_ = (6'b000000); - assign _zz_307_ = ((_zz_315_ == _zz_316_) != (1'b0)); - assign _zz_308_ = ({_zz_317_,_zz_318_} != (2'b00)); - assign _zz_309_ = {(_zz_319_ != _zz_320_),{_zz_321_,{_zz_322_,_zz_323_}}}; - assign _zz_310_ = (32'b01000000000000000011000001010100); - assign _zz_311_ = (32'b00000000000000000111000001010100); - assign _zz_312_ = ((decode_INSTRUCTION & (32'b00000000000000000001000000010000)) == (32'b00000000000000000001000000010000)); - assign _zz_313_ = ((decode_INSTRUCTION & _zz_324_) == (32'b00000000000000000010000000010000)); - assign _zz_314_ = {_zz_109_,{_zz_325_,_zz_326_}}; - assign _zz_315_ = (decode_INSTRUCTION & (32'b00000000000000000000000000000000)); - assign _zz_316_ = (32'b00000000000000000000000000000000); - assign _zz_317_ = ((decode_INSTRUCTION & _zz_327_) == (32'b00000000000000000000000000000100)); - assign _zz_318_ = _zz_111_; - assign _zz_319_ = {(_zz_328_ == _zz_329_),_zz_111_}; + assign _zz_153_ = ((execute_arbitration_isValid && execute_LightShifterPlugin_isShift) && (execute_SRC2[4 : 0] != (5'b00000))); + assign _zz_154_ = (! execute_arbitration_isStuckByOthers); + assign _zz_155_ = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != (2'b00)); + assign _zz_156_ = ({CsrPlugin_selfException_valid,{BranchPlugin_branchExceptionPort_valid,DBusSimplePlugin_memoryExceptionPort_valid}} != (3'b000)); + assign _zz_157_ = (CsrPlugin_hadException || CsrPlugin_interruptJump); + assign _zz_158_ = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); + assign _zz_159_ = execute_INSTRUCTION[29 : 28]; + assign _zz_160_ = (IBusCachedPlugin_fetchPc_preOutput_valid && IBusCachedPlugin_fetchPc_preOutput_ready); + assign _zz_161_ = (iBus_cmd_valid || (_zz_127_ != (3'b000))); + assign _zz_162_ = (! dBus_cmd_halfPipe_regs_valid); + assign _zz_163_ = execute_INSTRUCTION[13 : 12]; + assign _zz_164_ = execute_INSTRUCTION[13]; + assign _zz_165_ = (_zz_70_ - (3'b001)); + assign _zz_166_ = {IBusCachedPlugin_fetchPc_inc,(2'b00)}; + assign _zz_167_ = {29'd0, _zz_166_}; + assign _zz_168_ = (execute_MEMORY_STORE ? (3'b110) : (3'b100)); + assign _zz_169_ = _zz_87_[0 : 0]; + assign _zz_170_ = _zz_87_[7 : 7]; + assign _zz_171_ = _zz_87_[18 : 18]; + assign _zz_172_ = _zz_87_[19 : 19]; + assign _zz_173_ = _zz_87_[20 : 20]; + assign _zz_174_ = _zz_87_[21 : 21]; + assign _zz_175_ = _zz_87_[24 : 24]; + assign _zz_176_ = _zz_87_[25 : 25]; + assign _zz_177_ = execute_SRC_LESS; + assign _zz_178_ = (3'b100); + assign _zz_179_ = execute_INSTRUCTION[19 : 15]; + assign _zz_180_ = execute_INSTRUCTION[31 : 20]; + assign _zz_181_ = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; + assign _zz_182_ = ($signed(_zz_183_) + $signed(_zz_186_)); + assign _zz_183_ = ($signed(_zz_184_) + $signed(_zz_185_)); + assign _zz_184_ = execute_SRC1; + assign _zz_185_ = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); + assign _zz_186_ = (execute_SRC_USE_SUB_LESS ? _zz_187_ : _zz_188_); + assign _zz_187_ = (32'b00000000000000000000000000000001); + assign _zz_188_ = (32'b00000000000000000000000000000000); + assign _zz_189_ = (_zz_190_ >>> 1); + assign _zz_190_ = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_LightShifterPlugin_shiftInput[31]),execute_LightShifterPlugin_shiftInput}; + assign _zz_191_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_192_ = execute_INSTRUCTION[31 : 20]; + assign _zz_193_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_194_ = (_zz_118_ & (~ _zz_195_)); + assign _zz_195_ = (_zz_118_ - (2'b01)); + assign _zz_196_ = (_zz_120_ - (3'b001)); + assign _zz_197_ = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_198_ = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_199_ = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_200_ = execute_CsrPlugin_writeData[11 : 11]; + assign _zz_201_ = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_202_ = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_203_ = (iBus_cmd_payload_address >>> 5); + assign _zz_204_ = ({3'd0,_zz_129_} <<< dBus_cmd_halfPipe_payload_address[1 : 0]); + assign _zz_205_ = {_zz_73_,_zz_72_}; + assign _zz_206_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001100100)) == (32'b00000000000000000000000000100100)); + assign _zz_207_ = ((decode_INSTRUCTION & (32'b00000000000000000011000001010100)) == (32'b00000000000000000001000000010000)); + assign _zz_208_ = _zz_89_; + assign _zz_209_ = {(_zz_215_ == _zz_216_),{_zz_217_,{_zz_218_,_zz_219_}}}; + assign _zz_210_ = ((decode_INSTRUCTION & _zz_220_) == (32'b00000000000000000001000000000000)); + assign _zz_211_ = (1'b0); + assign _zz_212_ = ((_zz_221_ == _zz_222_) != (1'b0)); + assign _zz_213_ = ({_zz_223_,_zz_224_} != (3'b000)); + assign _zz_214_ = {(_zz_225_ != _zz_226_),{_zz_227_,{_zz_228_,_zz_229_}}}; + assign _zz_215_ = (decode_INSTRUCTION & (32'b00000000000000000001000000010000)); + assign _zz_216_ = (32'b00000000000000000001000000010000); + assign _zz_217_ = ((decode_INSTRUCTION & _zz_230_) == (32'b00000000000000000010000000010000)); + assign _zz_218_ = _zz_91_; + assign _zz_219_ = {_zz_231_,_zz_232_}; + assign _zz_220_ = (32'b00000000000000000001000000000000); + assign _zz_221_ = (decode_INSTRUCTION & (32'b00000000000000000011000000000000)); + assign _zz_222_ = (32'b00000000000000000010000000000000); + assign _zz_223_ = (_zz_233_ == _zz_234_); + assign _zz_224_ = {_zz_235_,_zz_236_}; + assign _zz_225_ = {_zz_237_,_zz_238_}; + assign _zz_226_ = (2'b00); + assign _zz_227_ = (_zz_239_ != (1'b0)); + assign _zz_228_ = (_zz_240_ != _zz_241_); + assign _zz_229_ = {_zz_242_,{_zz_243_,_zz_244_}}; + assign _zz_230_ = (32'b00000000000000000010000000010000); + assign _zz_231_ = ((decode_INSTRUCTION & _zz_245_) == (32'b00000000000000000000000000000100)); + assign _zz_232_ = ((decode_INSTRUCTION & _zz_246_) == (32'b00000000000000000000000000000000)); + assign _zz_233_ = (decode_INSTRUCTION & (32'b00000000000000000000000001000100)); + assign _zz_234_ = (32'b00000000000000000000000001000000); + assign _zz_235_ = ((decode_INSTRUCTION & _zz_247_) == (32'b00000000000000000010000000010000)); + assign _zz_236_ = ((decode_INSTRUCTION & _zz_248_) == (32'b01000000000000000000000000110000)); + assign _zz_237_ = ((decode_INSTRUCTION & _zz_249_) == (32'b00000000000000000010000000000000)); + assign _zz_238_ = ((decode_INSTRUCTION & _zz_250_) == (32'b00000000000000000001000000000000)); + assign _zz_239_ = ((decode_INSTRUCTION & _zz_251_) == (32'b00000000000000000000000000100000)); + assign _zz_240_ = (_zz_252_ == _zz_253_); + assign _zz_241_ = (1'b0); + assign _zz_242_ = ({_zz_254_,_zz_255_} != (2'b00)); + assign _zz_243_ = (_zz_256_ != _zz_257_); + assign _zz_244_ = {_zz_258_,{_zz_259_,_zz_260_}}; + assign _zz_245_ = (32'b00000000000000000000000000001100); + assign _zz_246_ = (32'b00000000000000000000000000101000); + assign _zz_247_ = (32'b00000000000000000010000000010100); + assign _zz_248_ = (32'b01000000000000000100000000110100); + assign _zz_249_ = (32'b00000000000000000010000000010000); + assign _zz_250_ = (32'b00000000000000000101000000000000); + assign _zz_251_ = (32'b00000000000000000000000000100000); + assign _zz_252_ = (decode_INSTRUCTION & (32'b00000000000000000000000001011000)); + assign _zz_253_ = (32'b00000000000000000000000000000000); + assign _zz_254_ = ((decode_INSTRUCTION & _zz_261_) == (32'b00000000000000000000000000000100)); + assign _zz_255_ = _zz_90_; + assign _zz_256_ = {(_zz_262_ == _zz_263_),_zz_90_}; + assign _zz_257_ = (2'b00); + assign _zz_258_ = ({_zz_264_,{_zz_265_,_zz_266_}} != (4'b0000)); + assign _zz_259_ = ({_zz_267_,_zz_268_} != (2'b00)); + assign _zz_260_ = {(_zz_269_ != _zz_270_),{_zz_271_,{_zz_272_,_zz_273_}}}; + assign _zz_261_ = (32'b00000000000000000000000000010100); + assign _zz_262_ = (decode_INSTRUCTION & (32'b00000000000000000000000001000100)); + assign _zz_263_ = (32'b00000000000000000000000000000100); + assign _zz_264_ = ((decode_INSTRUCTION & _zz_274_) == (32'b00000000000000000000000000000000)); + assign _zz_265_ = (_zz_275_ == _zz_276_); + assign _zz_266_ = {_zz_277_,_zz_278_}; + assign _zz_267_ = (_zz_279_ == _zz_280_); + assign _zz_268_ = (_zz_281_ == _zz_282_); + assign _zz_269_ = {_zz_89_,_zz_283_}; + assign _zz_270_ = (2'b00); + assign _zz_271_ = (_zz_284_ != (1'b0)); + assign _zz_272_ = (_zz_285_ != _zz_286_); + assign _zz_273_ = {_zz_287_,{_zz_288_,_zz_289_}}; + assign _zz_274_ = (32'b00000000000000000000000001000100); + assign _zz_275_ = (decode_INSTRUCTION & (32'b00000000000000000000000000011000)); + assign _zz_276_ = (32'b00000000000000000000000000000000); + assign _zz_277_ = ((decode_INSTRUCTION & (32'b00000000000000000110000000000100)) == (32'b00000000000000000010000000000000)); + assign _zz_278_ = ((decode_INSTRUCTION & (32'b00000000000000000101000000000100)) == (32'b00000000000000000001000000000000)); + assign _zz_279_ = (decode_INSTRUCTION & (32'b00000000000000000000000000110100)); + assign _zz_280_ = (32'b00000000000000000000000000100000); + assign _zz_281_ = (decode_INSTRUCTION & (32'b00000000000000000000000001100100)); + assign _zz_282_ = (32'b00000000000000000000000000100000); + assign _zz_283_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000011100)) == (32'b00000000000000000000000000000100)); + assign _zz_284_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001011000)) == (32'b00000000000000000000000001000000)); + assign _zz_285_ = ((decode_INSTRUCTION & _zz_290_) == (32'b00000000000000000000000001010000)); + assign _zz_286_ = (1'b0); + assign _zz_287_ = ({_zz_291_,_zz_292_} != (2'b00)); + assign _zz_288_ = ({_zz_293_,_zz_294_} != (2'b00)); + assign _zz_289_ = {(_zz_295_ != _zz_296_),{_zz_297_,{_zz_298_,_zz_299_}}}; + assign _zz_290_ = (32'b00010000000000000011000001010000); + assign _zz_291_ = ((decode_INSTRUCTION & (32'b00010000000100000011000001010000)) == (32'b00000000000100000000000001010000)); + assign _zz_292_ = ((decode_INSTRUCTION & (32'b00010000010000000011000001010000)) == (32'b00010000000000000000000001010000)); + assign _zz_293_ = ((decode_INSTRUCTION & _zz_300_) == (32'b00000000000000000110000000010000)); + assign _zz_294_ = ((decode_INSTRUCTION & _zz_301_) == (32'b00000000000000000100000000010000)); + assign _zz_295_ = ((decode_INSTRUCTION & _zz_302_) == (32'b00000000000000000010000000010000)); + assign _zz_296_ = (1'b0); + assign _zz_297_ = ((_zz_303_ == _zz_304_) != (1'b0)); + assign _zz_298_ = ({_zz_305_,_zz_306_} != (2'b00)); + assign _zz_299_ = {(_zz_307_ != _zz_308_),{_zz_309_,{_zz_310_,_zz_311_}}}; + assign _zz_300_ = (32'b00000000000000000110000000010100); + assign _zz_301_ = (32'b00000000000000000101000000010100); + assign _zz_302_ = (32'b00000000000000000110000000010100); + assign _zz_303_ = (decode_INSTRUCTION & (32'b00000000000000000001000001001000)); + assign _zz_304_ = (32'b00000000000000000001000000001000); + assign _zz_305_ = _zz_88_; + assign _zz_306_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001110000)) == (32'b00000000000000000000000000100000)); + assign _zz_307_ = {_zz_88_,((decode_INSTRUCTION & _zz_312_) == (32'b00000000000000000000000000000000))}; + assign _zz_308_ = (2'b00); + assign _zz_309_ = (((decode_INSTRUCTION & _zz_313_) == (32'b00000000000000000101000000010000)) != (1'b0)); + assign _zz_310_ = ({_zz_314_,_zz_315_} != (2'b00)); + assign _zz_311_ = {(_zz_316_ != (1'b0)),{(_zz_317_ != _zz_318_),(_zz_319_ != _zz_320_)}}; + assign _zz_312_ = (32'b00000000000000000000000000100000); + assign _zz_313_ = (32'b00000000000000000111000001010100); + assign _zz_314_ = ((decode_INSTRUCTION & (32'b01000000000000000011000001010100)) == (32'b01000000000000000001000000010000)); + assign _zz_315_ = ((decode_INSTRUCTION & (32'b00000000000000000111000001010100)) == (32'b00000000000000000001000000010000)); + assign _zz_316_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000010000)) == (32'b00000000000000000000000000010000)); + assign _zz_317_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000000000)) == (32'b00000000000000000000000000000000)); + assign _zz_318_ = (1'b0); + assign _zz_319_ = {((decode_INSTRUCTION & (32'b00000000000000000001000001010000)) == (32'b00000000000000000001000001010000)),((decode_INSTRUCTION & (32'b00000000000000000010000001010000)) == (32'b00000000000000000010000001010000))}; assign _zz_320_ = (2'b00); - assign _zz_321_ = ((_zz_330_ == _zz_331_) != (1'b0)); - assign _zz_322_ = ({_zz_332_,_zz_333_} != (2'b00)); - assign _zz_323_ = {(_zz_334_ != _zz_335_),{_zz_336_,{_zz_337_,_zz_338_}}}; - assign _zz_324_ = (32'b00000000000000000010000000010000); - assign _zz_325_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000101000)) == (32'b00000000000000000000000000000000)); - assign _zz_326_ = ((decode_INSTRUCTION & (32'b00000000000000000101000000000100)) == (32'b00000000000000000000000000000100)); - assign _zz_327_ = (32'b00000000000000000000000000010100); - assign _zz_328_ = (decode_INSTRUCTION & (32'b00000000000000000000000001000100)); - assign _zz_329_ = (32'b00000000000000000000000000000100); - assign _zz_330_ = (decode_INSTRUCTION & (32'b00010000000000000011000001010000)); - assign _zz_331_ = (32'b00000000000000000000000001010000); - assign _zz_332_ = ((decode_INSTRUCTION & _zz_339_) == (32'b00000000000100000000000001010000)); - assign _zz_333_ = ((decode_INSTRUCTION & _zz_340_) == (32'b00010000000000000000000001010000)); - assign _zz_334_ = {(_zz_341_ == _zz_342_),(_zz_343_ == _zz_344_)}; - assign _zz_335_ = (2'b00); - assign _zz_336_ = ({_zz_110_,_zz_345_} != (2'b00)); - assign _zz_337_ = ({_zz_346_,_zz_347_} != (2'b00)); - assign _zz_338_ = (_zz_109_ != (1'b0)); - assign _zz_339_ = (32'b00010000000100000011000001010000); - assign _zz_340_ = (32'b00010000010000000011000001010000); - assign _zz_341_ = (decode_INSTRUCTION & (32'b00000000000000000010000000010000)); - assign _zz_342_ = (32'b00000000000000000010000000000000); - assign _zz_343_ = (decode_INSTRUCTION & (32'b00000000000000000101000000000000)); - assign _zz_344_ = (32'b00000000000000000001000000000000); - assign _zz_345_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001110000)) == (32'b00000000000000000000000000100000)); - assign _zz_346_ = _zz_110_; - assign _zz_347_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000100000)) == (32'b00000000000000000000000000000000)); - assign _zz_348_ = execute_INSTRUCTION[31]; - assign _zz_349_ = execute_INSTRUCTION[31]; - assign _zz_350_ = execute_INSTRUCTION[7]; + assign _zz_321_ = (32'b00000000000000000001000001111111); + assign _zz_322_ = (decode_INSTRUCTION & (32'b00000000000000000010000001111111)); + assign _zz_323_ = (32'b00000000000000000010000001110011); + assign _zz_324_ = ((decode_INSTRUCTION & (32'b00000000000000000100000001111111)) == (32'b00000000000000000100000001100011)); + assign _zz_325_ = ((decode_INSTRUCTION & (32'b00000000000000000010000001111111)) == (32'b00000000000000000010000000010011)); + assign _zz_326_ = {((decode_INSTRUCTION & (32'b00000000000000000110000000111111)) == (32'b00000000000000000000000000100011)),{((decode_INSTRUCTION & (32'b00000000000000000010000001111111)) == (32'b00000000000000000000000000000011)),{((decode_INSTRUCTION & _zz_327_) == (32'b00000000000000000000000000000011)),{(_zz_328_ == _zz_329_),{_zz_330_,{_zz_331_,_zz_332_}}}}}}; + assign _zz_327_ = (32'b00000000000000000101000001011111); + assign _zz_328_ = (decode_INSTRUCTION & (32'b00000000000000000111000001111011)); + assign _zz_329_ = (32'b00000000000000000000000001100011); + assign _zz_330_ = ((decode_INSTRUCTION & (32'b00000000000000000110000001111111)) == (32'b00000000000000000000000000001111)); + assign _zz_331_ = ((decode_INSTRUCTION & (32'b11111110000000000000000001111111)) == (32'b00000000000000000000000000110011)); + assign _zz_332_ = {((decode_INSTRUCTION & (32'b10111100000000000111000001111111)) == (32'b00000000000000000101000000010011)),{((decode_INSTRUCTION & (32'b11111100000000000011000001111111)) == (32'b00000000000000000001000000010011)),{((decode_INSTRUCTION & _zz_333_) == (32'b00000000000000000101000000110011)),{(_zz_334_ == _zz_335_),{_zz_336_,{_zz_337_,_zz_338_}}}}}}; + assign _zz_333_ = (32'b10111110000000000111000001111111); + assign _zz_334_ = (decode_INSTRUCTION & (32'b10111110000000000111000001111111)); + assign _zz_335_ = (32'b00000000000000000000000000110011); + assign _zz_336_ = ((decode_INSTRUCTION & (32'b11011111111111111111111111111111)) == (32'b00010000001000000000000001110011)); + assign _zz_337_ = ((decode_INSTRUCTION & (32'b11111111111011111111111111111111)) == (32'b00000000000000000000000001110011)); + assign _zz_338_ = ((decode_INSTRUCTION & (32'b11111111111111111111111111111111)) == (32'b00010000010100000000000001110011)); + initial begin + $readmemb("2-stage-1024-cache.v_toplevel_RegFilePlugin_regFile.bin",RegFilePlugin_regFile); + end always @ (posedge clk) begin if(_zz_40_) begin RegFilePlugin_regFile[execute_RegFilePlugin_regFileWrite_payload_address] <= execute_RegFilePlugin_regFileWrite_payload_data; @@ -1257,56 +1229,55 @@ module VexRiscv ( end always @ (posedge clk) begin - if(_zz_120_) begin - _zz_174_ <= RegFilePlugin_regFile[execute_RegFilePlugin_regFileReadAddress1]; + if(_zz_99_) begin + _zz_148_ <= RegFilePlugin_regFile[execute_RegFilePlugin_regFileReadAddress1]; end end always @ (posedge clk) begin - if(_zz_120_) begin - _zz_175_ <= RegFilePlugin_regFile[execute_RegFilePlugin_regFileReadAddress2]; + if(_zz_99_) begin + _zz_149_ <= RegFilePlugin_regFile[execute_RegFilePlugin_regFileReadAddress2]; end end InstructionCache IBusCachedPlugin_cache ( - .io_flush_cmd_valid(_zz_158_), - .io_flush_cmd_ready(IBusCachedPlugin_cache_io_flush_cmd_ready), - .io_flush_rsp(IBusCachedPlugin_cache_io_flush_rsp), - .io_cpu_prefetch_isValid(_zz_159_), + .io_flush(_zz_130_), + .io_cpu_prefetch_isValid(_zz_131_), .io_cpu_prefetch_haltIt(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt), .io_cpu_prefetch_pc(IBusCachedPlugin_iBusRsp_stages_0_input_payload), - .io_cpu_fetch_isValid(_zz_160_), - .io_cpu_fetch_isStuck(_zz_161_), - .io_cpu_fetch_isRemoved(_zz_162_), - .io_cpu_fetch_pc(IBusCachedPlugin_iBusRsp_stages_1_input_payload), + .io_cpu_fetch_isValid(_zz_132_), + .io_cpu_fetch_isStuck(_zz_133_), + .io_cpu_fetch_isRemoved(_zz_134_), + .io_cpu_fetch_pc(IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload), .io_cpu_fetch_data(IBusCachedPlugin_cache_io_cpu_fetch_data), .io_cpu_fetch_dataBypassValid(IBusCachedPlugin_s1_tightlyCoupledHit), - .io_cpu_fetch_dataBypass(_zz_163_), + .io_cpu_fetch_dataBypass(_zz_135_), .io_cpu_fetch_mmuBus_cmd_isValid(IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_isValid), .io_cpu_fetch_mmuBus_cmd_virtualAddress(IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_virtualAddress), .io_cpu_fetch_mmuBus_cmd_bypassTranslation(IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_bypassTranslation), - .io_cpu_fetch_mmuBus_rsp_physicalAddress(_zz_72_), - .io_cpu_fetch_mmuBus_rsp_isIoAccess(_zz_164_), - .io_cpu_fetch_mmuBus_rsp_allowRead(_zz_165_), - .io_cpu_fetch_mmuBus_rsp_allowWrite(_zz_166_), - .io_cpu_fetch_mmuBus_rsp_allowExecute(_zz_167_), - .io_cpu_fetch_mmuBus_rsp_allowUser(_zz_168_), - .io_cpu_fetch_mmuBus_rsp_miss(_zz_169_), - .io_cpu_fetch_mmuBus_rsp_hit(_zz_170_), + .io_cpu_fetch_mmuBus_rsp_physicalAddress(IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_virtualAddress), + .io_cpu_fetch_mmuBus_rsp_isIoAccess(_zz_136_), + .io_cpu_fetch_mmuBus_rsp_allowRead(_zz_137_), + .io_cpu_fetch_mmuBus_rsp_allowWrite(_zz_138_), + .io_cpu_fetch_mmuBus_rsp_allowExecute(_zz_139_), + .io_cpu_fetch_mmuBus_rsp_exception(_zz_140_), + .io_cpu_fetch_mmuBus_rsp_refilling(_zz_141_), .io_cpu_fetch_mmuBus_end(IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_end), + .io_cpu_fetch_mmuBus_busy(_zz_142_), .io_cpu_fetch_physicalAddress(IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress), - .io_cpu_decode_isValid(_zz_171_), - .io_cpu_decode_isStuck(_zz_172_), - .io_cpu_decode_pc(IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload), + .io_cpu_fetch_cacheMiss(IBusCachedPlugin_cache_io_cpu_fetch_cacheMiss), + .io_cpu_fetch_error(IBusCachedPlugin_cache_io_cpu_fetch_error), + .io_cpu_fetch_mmuRefilling(IBusCachedPlugin_cache_io_cpu_fetch_mmuRefilling), + .io_cpu_fetch_mmuException(IBusCachedPlugin_cache_io_cpu_fetch_mmuException), + .io_cpu_fetch_isUser(_zz_143_), + .io_cpu_fetch_haltIt(IBusCachedPlugin_cache_io_cpu_fetch_haltIt), + .io_cpu_decode_isValid(_zz_144_), + .io_cpu_decode_isStuck(_zz_145_), + .io_cpu_decode_pc(_zz_146_), .io_cpu_decode_physicalAddress(IBusCachedPlugin_cache_io_cpu_decode_physicalAddress), .io_cpu_decode_data(IBusCachedPlugin_cache_io_cpu_decode_data), - .io_cpu_decode_cacheMiss(IBusCachedPlugin_cache_io_cpu_decode_cacheMiss), - .io_cpu_decode_error(IBusCachedPlugin_cache_io_cpu_decode_error), - .io_cpu_decode_mmuMiss(IBusCachedPlugin_cache_io_cpu_decode_mmuMiss), - .io_cpu_decode_illegalAccess(IBusCachedPlugin_cache_io_cpu_decode_illegalAccess), - .io_cpu_decode_isUser(_zz_173_), - .io_cpu_fill_valid(IBusCachedPlugin_rsp_redoFetch), - .io_cpu_fill_payload(IBusCachedPlugin_cache_io_cpu_decode_physicalAddress), + .io_cpu_fill_valid(_zz_147_), + .io_cpu_fill_payload(IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress), .io_mem_cmd_valid(IBusCachedPlugin_cache_io_mem_cmd_valid), .io_mem_cmd_ready(iBus_cmd_ready), .io_mem_cmd_payload_address(IBusCachedPlugin_cache_io_mem_cmd_payload_address), @@ -1318,166 +1289,37 @@ module VexRiscv ( .reset(reset) ); always @(*) begin - case(_zz_238_) + case(_zz_205_) 2'b00 : begin - _zz_176_ = execute_BRANCH_CALC; + _zz_150_ = BranchPlugin_jumpInterface_payload; end 2'b01 : begin - _zz_176_ = _zz_77_; - end - 2'b10 : begin - _zz_176_ = _zz_71_; + _zz_150_ = CsrPlugin_jumpInterface_payload; end default : begin - _zz_176_ = _zz_68_; + _zz_150_ = IBusCachedPlugin_redoBranch_payload; end endcase end always @(*) begin - case(_zz_152_) + case(_zz_124_) 2'b00 : begin - _zz_177_ = _zz_229_; - _zz_178_ = execute_REGFILE_WRITE_DATA; + _zz_151_ = DBusSimplePlugin_memoryExceptionPort_payload_code; + _zz_152_ = DBusSimplePlugin_memoryExceptionPort_payload_badAddr; end 2'b01 : begin - _zz_177_ = (4'b0000); - _zz_178_ = execute_BRANCH_CALC; + _zz_151_ = BranchPlugin_branchExceptionPort_payload_code; + _zz_152_ = BranchPlugin_branchExceptionPort_payload_badAddr; end default : begin - _zz_177_ = _zz_79_; - _zz_178_ = (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx); + _zz_151_ = CsrPlugin_selfException_payload_code; + _zz_152_ = CsrPlugin_selfException_payload_badAddr; end endcase end `ifndef SYNTHESIS - always @(*) begin - case(decode_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : decode_SRC1_CTRL_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : decode_SRC1_CTRL_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : decode_SRC1_CTRL_string = "URS1 "; - default : decode_SRC1_CTRL_string = "????????????"; - endcase - end - always @(*) begin - case(_zz_1_) - `Src1CtrlEnum_defaultEncoding_RS : _zz_1__string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_1__string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_1__string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_1__string = "URS1 "; - default : _zz_1__string = "????????????"; - endcase - end - always @(*) begin - case(_zz_2_) - `Src1CtrlEnum_defaultEncoding_RS : _zz_2__string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_2__string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_2__string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_2__string = "URS1 "; - default : _zz_2__string = "????????????"; - endcase - end - always @(*) begin - case(_zz_3_) - `Src1CtrlEnum_defaultEncoding_RS : _zz_3__string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_3__string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_3__string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_3__string = "URS1 "; - default : _zz_3__string = "????????????"; - endcase - end - always @(*) begin - case(decode_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1"; - `AluBitwiseCtrlEnum_defaultEncoding_SRC1 : decode_ALU_BITWISE_CTRL_string = "SRC1 "; - default : decode_ALU_BITWISE_CTRL_string = "?????"; - endcase - end - always @(*) begin - case(_zz_4_) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_4__string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_4__string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_4__string = "AND_1"; - `AluBitwiseCtrlEnum_defaultEncoding_SRC1 : _zz_4__string = "SRC1 "; - default : _zz_4__string = "?????"; - endcase - end - always @(*) begin - case(_zz_5_) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_5__string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_5__string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_5__string = "AND_1"; - `AluBitwiseCtrlEnum_defaultEncoding_SRC1 : _zz_5__string = "SRC1 "; - default : _zz_5__string = "?????"; - endcase - end - always @(*) begin - case(_zz_6_) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_6__string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_6__string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_6__string = "AND_1"; - `AluBitwiseCtrlEnum_defaultEncoding_SRC1 : _zz_6__string = "SRC1 "; - default : _zz_6__string = "?????"; - endcase - end - always @(*) begin - case(decode_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 "; - default : decode_SHIFT_CTRL_string = "?????????"; - endcase - end - always @(*) begin - case(_zz_7_) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_7__string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_7__string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_7__string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_7__string = "SRA_1 "; - default : _zz_7__string = "?????????"; - endcase - end - always @(*) begin - case(_zz_8_) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_8__string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_8__string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_8__string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_8__string = "SRA_1 "; - default : _zz_8__string = "?????????"; - endcase - end - always @(*) begin - case(_zz_9_) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_9__string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_9__string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_9__string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_9__string = "SRA_1 "; - default : _zz_9__string = "?????????"; - endcase - end - always @(*) begin - case(_zz_10_) - `BranchCtrlEnum_defaultEncoding_INC : _zz_10__string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_10__string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_10__string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_10__string = "JALR"; - default : _zz_10__string = "????"; - endcase - end - always @(*) begin - case(_zz_11_) - `BranchCtrlEnum_defaultEncoding_INC : _zz_11__string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_11__string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_11__string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_11__string = "JALR"; - default : _zz_11__string = "????"; - endcase - end always @(*) begin case(decode_ENV_CTRL) `EnvCtrlEnum_defaultEncoding_NONE : decode_ENV_CTRL_string = "NONE "; @@ -1488,30 +1330,30 @@ module VexRiscv ( endcase end always @(*) begin - case(_zz_12_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_12__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_12__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_12__string = "ECALL "; - `EnvCtrlEnum_defaultEncoding_EBREAK : _zz_12__string = "EBREAK"; - default : _zz_12__string = "??????"; + case(_zz_1_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_1__string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_1__string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_1__string = "ECALL "; + `EnvCtrlEnum_defaultEncoding_EBREAK : _zz_1__string = "EBREAK"; + default : _zz_1__string = "??????"; endcase end always @(*) begin - case(_zz_13_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_13__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_13__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_13__string = "ECALL "; - `EnvCtrlEnum_defaultEncoding_EBREAK : _zz_13__string = "EBREAK"; - default : _zz_13__string = "??????"; + case(_zz_2_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_2__string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_2__string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_2__string = "ECALL "; + `EnvCtrlEnum_defaultEncoding_EBREAK : _zz_2__string = "EBREAK"; + default : _zz_2__string = "??????"; endcase end always @(*) begin - case(_zz_14_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_14__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_14__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_14__string = "ECALL "; - `EnvCtrlEnum_defaultEncoding_EBREAK : _zz_14__string = "EBREAK"; - default : _zz_14__string = "??????"; + case(_zz_3_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_3__string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_3__string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_3__string = "ECALL "; + `EnvCtrlEnum_defaultEncoding_EBREAK : _zz_3__string = "EBREAK"; + default : _zz_3__string = "??????"; endcase end always @(*) begin @@ -1524,30 +1366,66 @@ module VexRiscv ( endcase end always @(*) begin - case(_zz_15_) - `Src2CtrlEnum_defaultEncoding_RS : _zz_15__string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_15__string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_15__string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_15__string = "PC "; - default : _zz_15__string = "???"; + case(_zz_4_) + `Src2CtrlEnum_defaultEncoding_RS : _zz_4__string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_4__string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_4__string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_4__string = "PC "; + default : _zz_4__string = "???"; endcase end always @(*) begin - case(_zz_16_) - `Src2CtrlEnum_defaultEncoding_RS : _zz_16__string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_16__string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_16__string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_16__string = "PC "; - default : _zz_16__string = "???"; + case(_zz_5_) + `Src2CtrlEnum_defaultEncoding_RS : _zz_5__string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_5__string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_5__string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_5__string = "PC "; + default : _zz_5__string = "???"; endcase end always @(*) begin - case(_zz_17_) - `Src2CtrlEnum_defaultEncoding_RS : _zz_17__string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_17__string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_17__string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_17__string = "PC "; - default : _zz_17__string = "???"; + case(_zz_6_) + `Src2CtrlEnum_defaultEncoding_RS : _zz_6__string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_6__string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_6__string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_6__string = "PC "; + default : _zz_6__string = "???"; + endcase + end + always @(*) begin + case(decode_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : decode_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : decode_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : decode_SRC1_CTRL_string = "URS1 "; + default : decode_SRC1_CTRL_string = "????????????"; + endcase + end + always @(*) begin + case(_zz_7_) + `Src1CtrlEnum_defaultEncoding_RS : _zz_7__string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_7__string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_7__string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_7__string = "URS1 "; + default : _zz_7__string = "????????????"; + endcase + end + always @(*) begin + case(_zz_8_) + `Src1CtrlEnum_defaultEncoding_RS : _zz_8__string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_8__string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_8__string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_8__string = "URS1 "; + default : _zz_8__string = "????????????"; + endcase + end + always @(*) begin + case(_zz_9_) + `Src1CtrlEnum_defaultEncoding_RS : _zz_9__string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_9__string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_9__string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_9__string = "URS1 "; + default : _zz_9__string = "????????????"; endcase end always @(*) begin @@ -1558,28 +1436,132 @@ module VexRiscv ( default : decode_ALU_CTRL_string = "????????"; endcase end + always @(*) begin + case(_zz_10_) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_10__string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_10__string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_10__string = "BITWISE "; + default : _zz_10__string = "????????"; + endcase + end + always @(*) begin + case(_zz_11_) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_11__string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_11__string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_11__string = "BITWISE "; + default : _zz_11__string = "????????"; + endcase + end + always @(*) begin + case(_zz_12_) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_12__string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_12__string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_12__string = "BITWISE "; + default : _zz_12__string = "????????"; + endcase + end + always @(*) begin + case(decode_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : decode_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : decode_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : decode_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : decode_BRANCH_CTRL_string = "JALR"; + default : decode_BRANCH_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_13_) + `BranchCtrlEnum_defaultEncoding_INC : _zz_13__string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_13__string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_13__string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_13__string = "JALR"; + default : _zz_13__string = "????"; + endcase + end + always @(*) begin + case(_zz_14_) + `BranchCtrlEnum_defaultEncoding_INC : _zz_14__string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_14__string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_14__string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_14__string = "JALR"; + default : _zz_14__string = "????"; + endcase + end + always @(*) begin + case(_zz_15_) + `BranchCtrlEnum_defaultEncoding_INC : _zz_15__string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_15__string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_15__string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_15__string = "JALR"; + default : _zz_15__string = "????"; + endcase + end + always @(*) begin + case(decode_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 "; + default : decode_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_16_) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_16__string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_16__string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_16__string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_16__string = "SRA_1 "; + default : _zz_16__string = "?????????"; + endcase + end + always @(*) begin + case(_zz_17_) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_17__string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_17__string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_17__string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_17__string = "SRA_1 "; + default : _zz_17__string = "?????????"; + endcase + end always @(*) begin case(_zz_18_) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_18__string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_18__string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_18__string = "BITWISE "; - default : _zz_18__string = "????????"; + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_18__string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_18__string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_18__string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_18__string = "SRA_1 "; + default : _zz_18__string = "?????????"; + endcase + end + always @(*) begin + case(decode_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1"; + default : decode_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin case(_zz_19_) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_19__string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_19__string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_19__string = "BITWISE "; - default : _zz_19__string = "????????"; + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_19__string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_19__string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_19__string = "AND_1"; + default : _zz_19__string = "?????"; endcase end always @(*) begin case(_zz_20_) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_20__string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_20__string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_20__string = "BITWISE "; - default : _zz_20__string = "????????"; + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_20__string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_20__string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_20__string = "AND_1"; + default : _zz_20__string = "?????"; + endcase + end + always @(*) begin + case(_zz_21_) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_21__string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_21__string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_21__string = "AND_1"; + default : _zz_21__string = "?????"; endcase end always @(*) begin @@ -1592,12 +1574,12 @@ module VexRiscv ( endcase end always @(*) begin - case(_zz_23_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_23__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_23__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_23__string = "ECALL "; - `EnvCtrlEnum_defaultEncoding_EBREAK : _zz_23__string = "EBREAK"; - default : _zz_23__string = "??????"; + case(_zz_24_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_24__string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_24__string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_24__string = "ECALL "; + `EnvCtrlEnum_defaultEncoding_EBREAK : _zz_24__string = "EBREAK"; + default : _zz_24__string = "??????"; endcase end always @(*) begin @@ -1628,12 +1610,12 @@ module VexRiscv ( endcase end always @(*) begin - case(_zz_29_) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_29__string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_29__string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_29__string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_29__string = "SRA_1 "; - default : _zz_29__string = "?????????"; + case(_zz_28_) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_28__string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_28__string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_28__string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_28__string = "SRA_1 "; + default : _zz_28__string = "?????????"; endcase end always @(*) begin @@ -1646,12 +1628,12 @@ module VexRiscv ( endcase end always @(*) begin - case(_zz_33_) - `Src2CtrlEnum_defaultEncoding_RS : _zz_33__string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_33__string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_33__string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_33__string = "PC "; - default : _zz_33__string = "???"; + case(_zz_32_) + `Src2CtrlEnum_defaultEncoding_RS : _zz_32__string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_32__string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_32__string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_32__string = "PC "; + default : _zz_32__string = "???"; endcase end always @(*) begin @@ -1664,12 +1646,12 @@ module VexRiscv ( endcase end always @(*) begin - case(_zz_35_) - `Src1CtrlEnum_defaultEncoding_RS : _zz_35__string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_35__string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_35__string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_35__string = "URS1 "; - default : _zz_35__string = "????????????"; + case(_zz_34_) + `Src1CtrlEnum_defaultEncoding_RS : _zz_34__string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_34__string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_34__string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_34__string = "URS1 "; + default : _zz_34__string = "????????????"; endcase end always @(*) begin @@ -1693,7 +1675,6 @@ module VexRiscv ( `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1"; `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 "; `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1"; - `AluBitwiseCtrlEnum_defaultEncoding_SRC1 : execute_ALU_BITWISE_CTRL_string = "SRC1 "; default : execute_ALU_BITWISE_CTRL_string = "?????"; endcase end @@ -1702,61 +1683,50 @@ module VexRiscv ( `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_39__string = "XOR_1"; `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_39__string = "OR_1 "; `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_39__string = "AND_1"; - `AluBitwiseCtrlEnum_defaultEncoding_SRC1 : _zz_39__string = "SRC1 "; default : _zz_39__string = "?????"; endcase end - always @(*) begin - case(_zz_44_) - `BranchCtrlEnum_defaultEncoding_INC : _zz_44__string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_44__string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_44__string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_44__string = "JALR"; - default : _zz_44__string = "????"; - endcase - end always @(*) begin case(_zz_45_) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_45__string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_45__string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_45__string = "BITWISE "; - default : _zz_45__string = "????????"; - endcase - end - always @(*) begin - case(_zz_49_) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_49__string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_49__string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_49__string = "AND_1"; - `AluBitwiseCtrlEnum_defaultEncoding_SRC1 : _zz_49__string = "SRC1 "; - default : _zz_49__string = "?????"; + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_45__string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_45__string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_45__string = "AND_1"; + default : _zz_45__string = "?????"; endcase end always @(*) begin case(_zz_50_) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_50__string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_50__string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_50__string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_50__string = "SRA_1 "; - default : _zz_50__string = "?????????"; + `Src1CtrlEnum_defaultEncoding_RS : _zz_50__string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_50__string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_50__string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_50__string = "URS1 "; + default : _zz_50__string = "????????????"; + endcase + end + always @(*) begin + case(_zz_51_) + `BranchCtrlEnum_defaultEncoding_INC : _zz_51__string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_51__string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_51__string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_51__string = "JALR"; + default : _zz_51__string = "????"; endcase end always @(*) begin case(_zz_52_) - `Src1CtrlEnum_defaultEncoding_RS : _zz_52__string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_52__string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_52__string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_52__string = "URS1 "; - default : _zz_52__string = "????????????"; + `EnvCtrlEnum_defaultEncoding_NONE : _zz_52__string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_52__string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_52__string = "ECALL "; + `EnvCtrlEnum_defaultEncoding_EBREAK : _zz_52__string = "EBREAK"; + default : _zz_52__string = "??????"; endcase end always @(*) begin case(_zz_53_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_53__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_53__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_53__string = "ECALL "; - `EnvCtrlEnum_defaultEncoding_EBREAK : _zz_53__string = "EBREAK"; - default : _zz_53__string = "??????"; + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_53__string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_53__string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_53__string = "BITWISE "; + default : _zz_53__string = "????????"; endcase end always @(*) begin @@ -1769,83 +1739,99 @@ module VexRiscv ( endcase end always @(*) begin - case(decode_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_INC : decode_BRANCH_CTRL_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : decode_BRANCH_CTRL_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : decode_BRANCH_CTRL_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : decode_BRANCH_CTRL_string = "JALR"; - default : decode_BRANCH_CTRL_string = "????"; + case(_zz_56_) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_56__string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_56__string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_56__string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_56__string = "SRA_1 "; + default : _zz_56__string = "?????????"; endcase end always @(*) begin - case(_zz_60_) - `BranchCtrlEnum_defaultEncoding_INC : _zz_60__string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_60__string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_60__string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_60__string = "JALR"; - default : _zz_60__string = "????"; + case(_zz_92_) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_92__string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_92__string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_92__string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_92__string = "SRA_1 "; + default : _zz_92__string = "?????????"; endcase end always @(*) begin - case(_zz_113_) - `Src2CtrlEnum_defaultEncoding_RS : _zz_113__string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_113__string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_113__string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_113__string = "PC "; - default : _zz_113__string = "???"; + case(_zz_93_) + `Src2CtrlEnum_defaultEncoding_RS : _zz_93__string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_93__string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_93__string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_93__string = "PC "; + default : _zz_93__string = "???"; endcase end always @(*) begin - case(_zz_114_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_114__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_114__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_114__string = "ECALL "; - `EnvCtrlEnum_defaultEncoding_EBREAK : _zz_114__string = "EBREAK"; - default : _zz_114__string = "??????"; + case(_zz_94_) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_94__string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_94__string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_94__string = "BITWISE "; + default : _zz_94__string = "????????"; endcase end always @(*) begin - case(_zz_115_) - `Src1CtrlEnum_defaultEncoding_RS : _zz_115__string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_115__string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_115__string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_115__string = "URS1 "; - default : _zz_115__string = "????????????"; + case(_zz_95_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_95__string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_95__string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_95__string = "ECALL "; + `EnvCtrlEnum_defaultEncoding_EBREAK : _zz_95__string = "EBREAK"; + default : _zz_95__string = "??????"; endcase end always @(*) begin - case(_zz_116_) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_116__string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_116__string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_116__string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_116__string = "SRA_1 "; - default : _zz_116__string = "?????????"; + case(_zz_96_) + `BranchCtrlEnum_defaultEncoding_INC : _zz_96__string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_96__string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_96__string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_96__string = "JALR"; + default : _zz_96__string = "????"; endcase end always @(*) begin - case(_zz_117_) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_117__string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_117__string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_117__string = "AND_1"; - `AluBitwiseCtrlEnum_defaultEncoding_SRC1 : _zz_117__string = "SRC1 "; - default : _zz_117__string = "?????"; + case(_zz_97_) + `Src1CtrlEnum_defaultEncoding_RS : _zz_97__string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_97__string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_97__string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_97__string = "URS1 "; + default : _zz_97__string = "????????????"; endcase end always @(*) begin - case(_zz_118_) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_118__string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_118__string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_118__string = "BITWISE "; - default : _zz_118__string = "????????"; + case(_zz_98_) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_98__string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_98__string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_98__string = "AND_1"; + default : _zz_98__string = "?????"; endcase end always @(*) begin - case(_zz_119_) - `BranchCtrlEnum_defaultEncoding_INC : _zz_119__string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_119__string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_119__string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_119__string = "JALR"; - default : _zz_119__string = "????"; + case(decode_to_execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : decode_to_execute_ALU_BITWISE_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(decode_to_execute_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; + default : decode_to_execute_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(decode_to_execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : decode_to_execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : decode_to_execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR"; + default : decode_to_execute_BRANCH_CTRL_string = "????"; endcase end always @(*) begin @@ -1856,6 +1842,15 @@ module VexRiscv ( default : decode_to_execute_ALU_CTRL_string = "????????"; endcase end + always @(*) begin + case(decode_to_execute_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : decode_to_execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : decode_to_execute_SRC1_CTRL_string = "URS1 "; + default : decode_to_execute_SRC1_CTRL_string = "????????????"; + endcase + end always @(*) begin case(decode_to_execute_SRC2_CTRL) `Src2CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC2_CTRL_string = "RS "; @@ -1874,89 +1869,54 @@ module VexRiscv ( default : decode_to_execute_ENV_CTRL_string = "??????"; endcase end - always @(*) begin - case(decode_to_execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_INC : decode_to_execute_BRANCH_CTRL_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : decode_to_execute_BRANCH_CTRL_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR"; - default : decode_to_execute_BRANCH_CTRL_string = "????"; - endcase - end - always @(*) begin - case(decode_to_execute_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; - default : decode_to_execute_SHIFT_CTRL_string = "?????????"; - endcase - end - always @(*) begin - case(decode_to_execute_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; - `AluBitwiseCtrlEnum_defaultEncoding_SRC1 : decode_to_execute_ALU_BITWISE_CTRL_string = "SRC1 "; - default : decode_to_execute_ALU_BITWISE_CTRL_string = "?????"; - endcase - end - always @(*) begin - case(decode_to_execute_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC1_CTRL_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : decode_to_execute_SRC1_CTRL_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : decode_to_execute_SRC1_CTRL_string = "URS1 "; - default : decode_to_execute_SRC1_CTRL_string = "????????????"; - endcase - end `endif - assign decode_SRC1_CTRL = _zz_1_; + assign decode_CSR_WRITE_OPCODE = _zz_23_; + assign decode_SRC_LESS_UNSIGNED = _zz_47_; + assign decode_ENV_CTRL = _zz_1_; assign _zz_2_ = _zz_3_; - assign decode_ALU_BITWISE_CTRL = _zz_4_; - assign _zz_5_ = _zz_6_; - assign decode_SHIFT_CTRL = _zz_7_; - assign _zz_8_ = _zz_9_; assign execute_FORMAL_PC_NEXT = decode_to_execute_FORMAL_PC_NEXT; - assign decode_FORMAL_PC_NEXT = _zz_62_; - assign _zz_10_ = _zz_11_; - assign decode_ENV_CTRL = _zz_12_; - assign _zz_13_ = _zz_14_; - assign decode_FLUSH_ALL = _zz_47_; - assign decode_PREDICTION_HAD_BRANCHED2 = _zz_28_; - assign decode_MEMORY_ENABLE = _zz_46_; + assign decode_FORMAL_PC_NEXT = _zz_67_; + assign decode_SRC2_CTRL = _zz_4_; + assign _zz_5_ = _zz_6_; + assign decode_IS_CSR = _zz_57_; + assign decode_MEMORY_ENABLE = _zz_49_; + assign decode_SRC1_CTRL = _zz_7_; + assign _zz_8_ = _zz_9_; + assign decode_CSR_READ_OPCODE = _zz_22_; assign execute_REGFILE_WRITE_VALID = decode_to_execute_REGFILE_WRITE_VALID; - assign decode_IS_CSR = _zz_43_; - assign decode_SRC2_CTRL = _zz_15_; - assign _zz_16_ = _zz_17_; - assign decode_CSR_WRITE_OPCODE = _zz_22_; - assign decode_CSR_READ_OPCODE = _zz_21_; - assign decode_ALU_CTRL = _zz_18_; - assign _zz_19_ = _zz_20_; - assign decode_SRC_USE_SUB_LESS = _zz_48_; - assign decode_SRC_LESS_UNSIGNED = _zz_54_; + assign decode_ALU_CTRL = _zz_10_; + assign _zz_11_ = _zz_12_; + assign decode_SRC2_FORCE_ZERO = _zz_36_; + assign decode_MEMORY_STORE = _zz_48_; + assign decode_BRANCH_CTRL = _zz_13_; + assign _zz_14_ = _zz_15_; + assign decode_SHIFT_CTRL = _zz_16_; + assign _zz_17_ = _zz_18_; + assign decode_ALU_BITWISE_CTRL = _zz_19_; + assign _zz_20_ = _zz_21_; assign execute_CSR_READ_OPCODE = decode_to_execute_CSR_READ_OPCODE; assign execute_CSR_WRITE_OPCODE = decode_to_execute_CSR_WRITE_OPCODE; assign execute_IS_CSR = decode_to_execute_IS_CSR; - assign execute_ENV_CTRL = _zz_23_; - assign execute_BRANCH_CALC = _zz_24_; - assign execute_BRANCH_DO = _zz_25_; + assign execute_ENV_CTRL = _zz_24_; + assign execute_BRANCH_CALC = _zz_25_; + assign execute_BRANCH_DO = _zz_27_; assign execute_PC = decode_to_execute_PC; - assign execute_PREDICTION_HAD_BRANCHED2 = decode_to_execute_PREDICTION_HAD_BRANCHED2; assign execute_RS1 = _zz_42_; - assign execute_BRANCH_COND_RESULT = _zz_27_; assign execute_BRANCH_CTRL = _zz_26_; - assign execute_SHIFT_CTRL = _zz_29_; + assign execute_SHIFT_CTRL = _zz_28_; assign execute_SRC_LESS_UNSIGNED = decode_to_execute_SRC_LESS_UNSIGNED; + assign execute_SRC2_FORCE_ZERO = decode_to_execute_SRC2_FORCE_ZERO; assign execute_SRC_USE_SUB_LESS = decode_to_execute_SRC_USE_SUB_LESS; - assign execute_SRC2_CTRL = _zz_33_; - assign execute_SRC1_CTRL = _zz_35_; - assign execute_SRC_ADD_SUB = _zz_32_; - assign execute_SRC_LESS = _zz_30_; + assign execute_SRC2_CTRL = _zz_32_; + assign execute_SRC1_CTRL = _zz_34_; + assign decode_SRC_USE_SUB_LESS = _zz_46_; + assign decode_SRC_ADD_ZERO = _zz_43_; + assign execute_SRC_ADD_SUB = _zz_31_; + assign execute_SRC_LESS = _zz_29_; assign execute_ALU_CTRL = _zz_37_; - assign execute_SRC2 = _zz_34_; - assign execute_SRC1 = _zz_36_; + assign execute_SRC2 = _zz_33_; + assign execute_SRC1 = _zz_35_; assign execute_ALU_BITWISE_CTRL = _zz_39_; always @ (*) begin _zz_40_ = 1'b0; @@ -1966,91 +1926,119 @@ module VexRiscv ( end always @ (*) begin - decode_REGFILE_WRITE_VALID = _zz_51_; + decode_REGFILE_WRITE_VALID = _zz_44_; if((decode_INSTRUCTION[11 : 7] == (5'b00000)))begin decode_REGFILE_WRITE_VALID = 1'b0; end end + assign decode_LEGAL_INSTRUCTION = _zz_58_; + assign decode_INSTRUCTION_READY = 1'b1; always @ (*) begin - _zz_56_ = execute_REGFILE_WRITE_DATA; + _zz_59_ = execute_REGFILE_WRITE_DATA; execute_arbitration_haltItself = 1'b0; - _zz_158_ = 1'b0; - if((execute_arbitration_isValid && execute_FLUSH_ALL))begin - _zz_158_ = 1'b1; - if((! IBusCachedPlugin_cache_io_flush_cmd_ready))begin - execute_arbitration_haltItself = 1'b1; - end - end - if(((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! dBus_cmd_ready)) && (! execute_ALIGNEMENT_FAULT)) && (! execute_DBusSimplePlugin_cmdSent)))begin + if(((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! dBus_cmd_ready)) && (! execute_DBusSimplePlugin_skipCmd)) && (! execute_DBusSimplePlugin_cmdSent)))begin execute_arbitration_haltItself = 1'b1; end - if((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! execute_INSTRUCTION[5])) && (! dBus_rsp_ready)))begin + if((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! execute_MEMORY_STORE)) && (! dBus_rsp_ready)))begin execute_arbitration_haltItself = 1'b1; end if((execute_arbitration_isValid && execute_MEMORY_ENABLE))begin - _zz_56_ = execute_DBusSimplePlugin_rspFormated; + _zz_59_ = execute_DBusSimplePlugin_rspFormated; end - if(_zz_179_)begin - _zz_56_ = _zz_128_; - if(_zz_180_)begin + if(_zz_153_)begin + _zz_59_ = _zz_107_; + if(_zz_154_)begin if(! execute_LightShifterPlugin_done) begin execute_arbitration_haltItself = 1'b1; end end end if((execute_arbitration_isValid && execute_IS_CSR))begin - _zz_56_ = execute_CsrPlugin_readData; + _zz_59_ = execute_CsrPlugin_readData; if(execute_CsrPlugin_blockedBySideEffects)begin execute_arbitration_haltItself = 1'b1; end end end - assign execute_MEMORY_ADDRESS_LOW = _zz_58_; - assign execute_MEMORY_READ_DATA = _zz_57_; + assign execute_MEMORY_ADDRESS_LOW = _zz_61_; + assign execute_MEMORY_READ_DATA = _zz_60_; assign execute_REGFILE_WRITE_DATA = _zz_38_; + assign execute_SRC_ADD = _zz_30_; assign execute_RS2 = _zz_41_; - assign execute_SRC_ADD = _zz_31_; assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION; - assign execute_ALIGNEMENT_FAULT = _zz_59_; + assign execute_MEMORY_STORE = decode_to_execute_MEMORY_STORE; assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE; - assign execute_FLUSH_ALL = decode_to_execute_FLUSH_ALL; + assign execute_ALIGNEMENT_FAULT = _zz_62_; + assign decode_FLUSH_ALL = _zz_54_; always @ (*) begin - IBusCachedPlugin_rsp_issueDetected = 1'b0; - IBusCachedPlugin_rsp_redoFetch = 1'b0; - if(((_zz_171_ && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! 1'b0)))begin + IBusCachedPlugin_rsp_issueDetected = _zz_63_; + _zz_64_ = _zz_65_; + IBusCachedPlugin_decodeExceptionPort_valid = 1'b0; + IBusCachedPlugin_decodeExceptionPort_payload_code = (4'bxxxx); + if(((_zz_132_ && IBusCachedPlugin_cache_io_cpu_fetch_mmuException) && (! _zz_65_)))begin + _zz_64_ = 1'b1; + IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; + IBusCachedPlugin_decodeExceptionPort_payload_code = (4'b1100); + end + if(((_zz_132_ && IBusCachedPlugin_cache_io_cpu_fetch_error) && (! _zz_63_)))begin IBusCachedPlugin_rsp_issueDetected = 1'b1; - IBusCachedPlugin_rsp_redoFetch = IBusCachedPlugin_iBusRsp_readyForError; + IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; + IBusCachedPlugin_decodeExceptionPort_payload_code = (4'b0001); + end + if(IBusCachedPlugin_fetcherHalt)begin + IBusCachedPlugin_decodeExceptionPort_valid = 1'b0; end end - assign decode_BRANCH_CTRL = _zz_60_; always @ (*) begin - _zz_61_ = decode_FORMAL_PC_NEXT; - if(_zz_67_)begin - _zz_61_ = _zz_68_; + _zz_63_ = _zz_64_; + _zz_65_ = 1'b0; + IBusCachedPlugin_rsp_redoFetch = 1'b0; + _zz_147_ = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_fetch_mmuRefilling)); + if(((_zz_132_ && IBusCachedPlugin_cache_io_cpu_fetch_mmuRefilling) && (! 1'b0)))begin + _zz_65_ = 1'b1; + IBusCachedPlugin_rsp_redoFetch = 1'b1; end - if(_zz_70_)begin - _zz_61_ = _zz_71_; + if(((_zz_132_ && IBusCachedPlugin_cache_io_cpu_fetch_cacheMiss) && (! _zz_64_)))begin + _zz_63_ = 1'b1; + _zz_147_ = 1'b1; + IBusCachedPlugin_rsp_redoFetch = 1'b1; + end + if((! IBusCachedPlugin_iBusRsp_readyForError))begin + IBusCachedPlugin_rsp_redoFetch = 1'b0; + end + if((! IBusCachedPlugin_iBusRsp_readyForError))begin + _zz_147_ = 1'b0; end end - assign decode_PC = _zz_64_; - assign decode_INSTRUCTION = _zz_63_; + always @ (*) begin + _zz_66_ = decode_FORMAL_PC_NEXT; + if(IBusCachedPlugin_redoBranch_valid)begin + _zz_66_ = IBusCachedPlugin_redoBranch_payload; + end + end + + assign decode_PC = _zz_69_; + assign decode_INSTRUCTION = _zz_68_; assign decode_arbitration_haltItself = 1'b0; always @ (*) begin decode_arbitration_haltByOther = 1'b0; - if((CsrPlugin_interrupt && decode_arbitration_isValid))begin - decode_arbitration_haltByOther = 1'b1; + if(CsrPlugin_interrupt)begin + decode_arbitration_haltByOther = decode_arbitration_isValid; end - if(1'b0)begin + if(((execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)) != (1'b0)))begin decode_arbitration_haltByOther = 1'b1; end end always @ (*) begin decode_arbitration_removeIt = 1'b0; + if(_zz_155_)begin + decode_arbitration_removeIt = 1'b1; + end if(decode_arbitration_isFlushed)begin decode_arbitration_removeIt = 1'b1; end @@ -2059,64 +2047,79 @@ module VexRiscv ( always @ (*) begin decode_arbitration_flushAll = 1'b0; execute_arbitration_removeIt = 1'b0; - _zz_76_ = 1'b0; - _zz_77_ = (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx); - if(_zz_74_)begin + IBusCachedPlugin_fetcherHalt = 1'b0; + CsrPlugin_jumpInterface_valid = 1'b0; + CsrPlugin_jumpInterface_payload = (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx); + if(BranchPlugin_jumpInterface_valid)begin decode_arbitration_flushAll = 1'b1; end CsrPlugin_exceptionPortCtrl_exceptionValids_execute = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; - if(execute_exception_agregat_valid)begin + if(_zz_156_)begin decode_arbitration_flushAll = 1'b1; execute_arbitration_removeIt = 1'b1; CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b1; end - if(_zz_181_)begin - _zz_76_ = 1'b1; - _zz_77_ = {CsrPlugin_mtvec_base,(2'b00)}; + if(execute_arbitration_isFlushed)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b0; + end + if(({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode} != (2'b00)))begin + IBusCachedPlugin_fetcherHalt = 1'b1; + end + if(_zz_157_)begin + IBusCachedPlugin_fetcherHalt = 1'b1; + CsrPlugin_jumpInterface_valid = 1'b1; + CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,(2'b00)}; decode_arbitration_flushAll = 1'b1; end - if(_zz_182_)begin - _zz_77_ = CsrPlugin_mepc; - _zz_76_ = 1'b1; + if(_zz_158_)begin + IBusCachedPlugin_fetcherHalt = 1'b1; + CsrPlugin_jumpInterface_valid = 1'b1; decode_arbitration_flushAll = 1'b1; + case(_zz_159_) + 2'b11 : begin + CsrPlugin_jumpInterface_payload = CsrPlugin_mepc; + end + default : begin + end + endcase end if(execute_arbitration_isFlushed)begin execute_arbitration_removeIt = 1'b1; end end - assign decode_arbitration_redoIt = 1'b0; assign execute_arbitration_haltByOther = 1'b0; assign execute_arbitration_flushAll = 1'b0; - assign execute_arbitration_redoIt = 1'b0; + assign IBusCachedPlugin_fetcherflushIt = 1'b0; always @ (*) begin - _zz_65_ = 1'b0; - if(({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode} != (2'b00)))begin - _zz_65_ = 1'b1; + IBusCachedPlugin_incomingInstruction = 1'b0; + if(IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid)begin + IBusCachedPlugin_incomingInstruction = 1'b1; end end - assign _zz_66_ = 1'b0; - assign IBusCachedPlugin_jump_pcLoad_valid = ({_zz_76_,{_zz_74_,{_zz_70_,_zz_67_}}} != (4'b0000)); - assign _zz_80_ = {_zz_67_,{_zz_70_,{_zz_76_,_zz_74_}}}; - assign _zz_81_ = (_zz_80_ & (~ _zz_189_)); - assign _zz_82_ = _zz_81_[3]; - assign _zz_83_ = (_zz_81_[1] || _zz_82_); - assign _zz_84_ = (_zz_81_[2] || _zz_82_); - assign IBusCachedPlugin_jump_pcLoad_payload = _zz_176_; - assign _zz_85_ = (! _zz_65_); - assign IBusCachedPlugin_fetchPc_output_valid = (IBusCachedPlugin_fetchPc_preOutput_valid && _zz_85_); - assign IBusCachedPlugin_fetchPc_preOutput_ready = (IBusCachedPlugin_fetchPc_output_ready && _zz_85_); + assign CsrPlugin_forceMachineWire = 1'b0; + assign CsrPlugin_allowInterrupts = 1'b1; + assign CsrPlugin_allowException = 1'b1; + assign IBusCachedPlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,IBusCachedPlugin_redoBranch_valid}} != (3'b000)); + assign _zz_70_ = {IBusCachedPlugin_redoBranch_valid,{CsrPlugin_jumpInterface_valid,BranchPlugin_jumpInterface_valid}}; + assign _zz_71_ = (_zz_70_ & (~ _zz_165_)); + assign _zz_72_ = _zz_71_[1]; + assign _zz_73_ = _zz_71_[2]; + assign IBusCachedPlugin_jump_pcLoad_payload = _zz_150_; + assign _zz_74_ = (! IBusCachedPlugin_fetcherHalt); + assign IBusCachedPlugin_fetchPc_output_valid = (IBusCachedPlugin_fetchPc_preOutput_valid && _zz_74_); + assign IBusCachedPlugin_fetchPc_preOutput_ready = (IBusCachedPlugin_fetchPc_output_ready && _zz_74_); assign IBusCachedPlugin_fetchPc_output_payload = IBusCachedPlugin_fetchPc_preOutput_payload; always @ (*) begin IBusCachedPlugin_fetchPc_propagatePc = 1'b0; - if((IBusCachedPlugin_iBusRsp_stages_1_input_valid && IBusCachedPlugin_iBusRsp_stages_1_input_ready))begin + if((IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid && IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready))begin IBusCachedPlugin_fetchPc_propagatePc = 1'b1; end end always @ (*) begin - IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_191_); + IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_167_); IBusCachedPlugin_fetchPc_samplePcNext = 1'b0; if(IBusCachedPlugin_fetchPc_propagatePc)begin IBusCachedPlugin_fetchPc_samplePcNext = 1'b1; @@ -2125,14 +2128,14 @@ module VexRiscv ( IBusCachedPlugin_fetchPc_samplePcNext = 1'b1; IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_jump_pcLoad_payload; end - if(_zz_183_)begin + if(_zz_160_)begin IBusCachedPlugin_fetchPc_samplePcNext = 1'b1; end IBusCachedPlugin_fetchPc_pc[0] = 1'b0; IBusCachedPlugin_fetchPc_pc[1] = 1'b0; end - assign IBusCachedPlugin_fetchPc_preOutput_valid = _zz_86_; + assign IBusCachedPlugin_fetchPc_preOutput_valid = _zz_75_; assign IBusCachedPlugin_fetchPc_preOutput_payload = IBusCachedPlugin_fetchPc_pc; assign IBusCachedPlugin_iBusRsp_stages_0_input_valid = IBusCachedPlugin_fetchPc_output_valid; assign IBusCachedPlugin_fetchPc_output_ready = IBusCachedPlugin_iBusRsp_stages_0_input_ready; @@ -2145,111 +2148,43 @@ module VexRiscv ( end end - assign _zz_87_ = (! IBusCachedPlugin_iBusRsp_stages_0_halt); - assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_87_); - assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_87_); + assign _zz_76_ = (! IBusCachedPlugin_iBusRsp_stages_0_halt); + assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_76_); + assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_76_); assign IBusCachedPlugin_iBusRsp_stages_0_output_payload = IBusCachedPlugin_iBusRsp_stages_0_input_payload; - always @ (*) begin - IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b0; - if(((IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_isValid && (! 1'b1)) && (! 1'b0)))begin - IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b1; - end - end - - assign _zz_88_ = (! IBusCachedPlugin_iBusRsp_stages_1_halt); - assign IBusCachedPlugin_iBusRsp_stages_1_input_ready = (IBusCachedPlugin_iBusRsp_stages_1_output_ready && _zz_88_); - assign IBusCachedPlugin_iBusRsp_stages_1_output_valid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && _zz_88_); - assign IBusCachedPlugin_iBusRsp_stages_1_output_payload = IBusCachedPlugin_iBusRsp_stages_1_input_payload; always @ (*) begin IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt = 1'b0; + if(IBusCachedPlugin_cache_io_cpu_fetch_haltIt)begin + IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt = 1'b1; + end if((IBusCachedPlugin_rsp_issueDetected || IBusCachedPlugin_rsp_iBusRspOutputHalt))begin IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt = 1'b1; end end - assign _zz_89_ = (! IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt); - assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready = (IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_ready && _zz_89_); - assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_valid = (IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid && _zz_89_); + assign _zz_77_ = (! IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt); + assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready = (IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_ready && _zz_77_); + assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_valid = (IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid && _zz_77_); assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_payload = IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload; - assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_90_; - assign _zz_90_ = ((1'b0 && (! _zz_91_)) || IBusCachedPlugin_iBusRsp_stages_1_input_ready); - assign _zz_91_ = _zz_92_; - assign IBusCachedPlugin_iBusRsp_stages_1_input_valid = _zz_91_; - assign IBusCachedPlugin_iBusRsp_stages_1_input_payload = IBusCachedPlugin_fetchPc_pcReg; - assign IBusCachedPlugin_iBusRsp_stages_1_output_ready = ((1'b0 && (! _zz_93_)) || IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready); - assign _zz_93_ = _zz_94_; - assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid = _zz_93_; - assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload = _zz_95_; - assign IBusCachedPlugin_iBusRsp_readyForError = 1'b1; + assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_78_; + assign _zz_78_ = ((1'b0 && (! _zz_79_)) || IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready); + assign _zz_79_ = _zz_80_; + assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid = _zz_79_; + assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload = IBusCachedPlugin_fetchPc_pcReg; + always @ (*) begin + IBusCachedPlugin_iBusRsp_readyForError = 1'b1; + if((! IBusCachedPlugin_pcValids_0))begin + IBusCachedPlugin_iBusRsp_readyForError = 1'b0; + end + end + + assign IBusCachedPlugin_pcValids_0 = IBusCachedPlugin_injector_nextPcCalc_valids_0; + assign IBusCachedPlugin_pcValids_1 = IBusCachedPlugin_injector_nextPcCalc_valids_1; assign IBusCachedPlugin_iBusRsp_decodeInput_ready = (! decode_arbitration_isStuck); assign decode_arbitration_isValid = (IBusCachedPlugin_iBusRsp_decodeInput_valid && (! IBusCachedPlugin_injector_decodeRemoved)); - assign _zz_64_ = IBusCachedPlugin_iBusRsp_decodeInput_payload_pc; - assign _zz_63_ = IBusCachedPlugin_iBusRsp_decodeInput_payload_rsp_inst; - assign _zz_62_ = (decode_PC + (32'b00000000000000000000000000000100)); - assign _zz_96_ = _zz_192_[11]; - always @ (*) begin - _zz_97_[18] = _zz_96_; - _zz_97_[17] = _zz_96_; - _zz_97_[16] = _zz_96_; - _zz_97_[15] = _zz_96_; - _zz_97_[14] = _zz_96_; - _zz_97_[13] = _zz_96_; - _zz_97_[12] = _zz_96_; - _zz_97_[11] = _zz_96_; - _zz_97_[10] = _zz_96_; - _zz_97_[9] = _zz_96_; - _zz_97_[8] = _zz_96_; - _zz_97_[7] = _zz_96_; - _zz_97_[6] = _zz_96_; - _zz_97_[5] = _zz_96_; - _zz_97_[4] = _zz_96_; - _zz_97_[3] = _zz_96_; - _zz_97_[2] = _zz_96_; - _zz_97_[1] = _zz_96_; - _zz_97_[0] = _zz_96_; - end - - assign _zz_69_ = ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_B) && _zz_193_[31])); - assign _zz_67_ = (_zz_69_ && decode_arbitration_isFiring); - assign _zz_98_ = _zz_194_[19]; - always @ (*) begin - _zz_99_[10] = _zz_98_; - _zz_99_[9] = _zz_98_; - _zz_99_[8] = _zz_98_; - _zz_99_[7] = _zz_98_; - _zz_99_[6] = _zz_98_; - _zz_99_[5] = _zz_98_; - _zz_99_[4] = _zz_98_; - _zz_99_[3] = _zz_98_; - _zz_99_[2] = _zz_98_; - _zz_99_[1] = _zz_98_; - _zz_99_[0] = _zz_98_; - end - - assign _zz_100_ = _zz_195_[11]; - always @ (*) begin - _zz_101_[18] = _zz_100_; - _zz_101_[17] = _zz_100_; - _zz_101_[16] = _zz_100_; - _zz_101_[15] = _zz_100_; - _zz_101_[14] = _zz_100_; - _zz_101_[13] = _zz_100_; - _zz_101_[12] = _zz_100_; - _zz_101_[11] = _zz_100_; - _zz_101_[10] = _zz_100_; - _zz_101_[9] = _zz_100_; - _zz_101_[8] = _zz_100_; - _zz_101_[7] = _zz_100_; - _zz_101_[6] = _zz_100_; - _zz_101_[5] = _zz_100_; - _zz_101_[4] = _zz_100_; - _zz_101_[3] = _zz_100_; - _zz_101_[2] = _zz_100_; - _zz_101_[1] = _zz_100_; - _zz_101_[0] = _zz_100_; - end - - assign _zz_68_ = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_99_,{{{_zz_239_,_zz_240_},_zz_241_},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_101_,{{{_zz_242_,_zz_243_},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); + assign _zz_69_ = IBusCachedPlugin_iBusRsp_decodeInput_payload_pc; + assign _zz_68_ = IBusCachedPlugin_iBusRsp_decodeInput_payload_rsp_inst; + assign _zz_67_ = (decode_PC + (32'b00000000000000000000000000000100)); assign iBus_cmd_valid = IBusCachedPlugin_cache_io_mem_cmd_valid; always @ (*) begin iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; @@ -2258,72 +2193,85 @@ module VexRiscv ( assign iBus_cmd_payload_size = IBusCachedPlugin_cache_io_mem_cmd_payload_size; assign IBusCachedPlugin_s0_tightlyCoupledHit = 1'b0; - assign _zz_159_ = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); - assign _zz_162_ = (IBusCachedPlugin_jump_pcLoad_valid || _zz_66_); - assign _zz_163_ = (32'b00000000000000000000000000000000); - assign _zz_160_ = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); - assign _zz_161_ = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); - assign _zz_171_ = (IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); - assign _zz_172_ = (! IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready); - assign _zz_173_ = (CsrPlugin_privilege == (2'b00)); + assign _zz_131_ = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); + assign _zz_134_ = (IBusCachedPlugin_jump_pcLoad_valid || IBusCachedPlugin_fetcherflushIt); + assign _zz_135_ = (32'b00000000000000000000000000000000); + assign _zz_132_ = (IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); + assign _zz_133_ = (! IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready); + assign _zz_143_ = (CsrPlugin_privilege == (2'b00)); assign IBusCachedPlugin_rsp_iBusRspOutputHalt = 1'b0; - assign _zz_70_ = IBusCachedPlugin_rsp_redoFetch; - assign _zz_71_ = IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload; + assign IBusCachedPlugin_decodeExceptionPort_payload_badAddr = {IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload[31 : 2],(2'b00)}; + assign IBusCachedPlugin_redoBranch_valid = IBusCachedPlugin_rsp_redoFetch; + assign IBusCachedPlugin_redoBranch_payload = IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload; assign IBusCachedPlugin_iBusRsp_decodeInput_valid = IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_valid; assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_ready = IBusCachedPlugin_iBusRsp_decodeInput_ready; - assign IBusCachedPlugin_iBusRsp_decodeInput_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_decode_data; + assign IBusCachedPlugin_iBusRsp_decodeInput_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_fetch_data; assign IBusCachedPlugin_iBusRsp_decodeInput_payload_pc = IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_payload; - assign _zz_164_ = _zz_72_[31]; - assign _zz_165_ = 1'b1; - assign _zz_166_ = 1'b1; - assign _zz_167_ = 1'b1; - assign _zz_168_ = 1'b1; - assign _zz_169_ = 1'b0; - assign _zz_170_ = 1'b1; - assign _zz_59_ = (((dBus_cmd_payload_size == (2'b10)) && (dBus_cmd_payload_address[1 : 0] != (2'b00))) || ((dBus_cmd_payload_size == (2'b01)) && (dBus_cmd_payload_address[0 : 0] != (1'b0)))); - assign dBus_cmd_valid = (((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! execute_arbitration_isStuckByOthers)) && (! execute_arbitration_isFlushed)) && (! execute_ALIGNEMENT_FAULT)) && (! execute_DBusSimplePlugin_cmdSent)); - assign dBus_cmd_payload_wr = execute_INSTRUCTION[5]; - assign dBus_cmd_payload_address = execute_SRC_ADD; + assign _zz_139_ = 1'b1; + assign _zz_137_ = 1'b1; + assign _zz_138_ = 1'b1; + assign _zz_136_ = 1'b0; + assign _zz_140_ = 1'b0; + assign _zz_141_ = 1'b0; + assign _zz_142_ = 1'b0; + assign _zz_130_ = (decode_arbitration_isValid && decode_FLUSH_ALL); + assign _zz_62_ = (((dBus_cmd_payload_size == (2'b10)) && (dBus_cmd_payload_address[1 : 0] != (2'b00))) || ((dBus_cmd_payload_size == (2'b01)) && (dBus_cmd_payload_address[0 : 0] != (1'b0)))); + always @ (*) begin + execute_DBusSimplePlugin_skipCmd = 1'b0; + if(execute_ALIGNEMENT_FAULT)begin + execute_DBusSimplePlugin_skipCmd = 1'b1; + end + end + + assign dBus_cmd_valid = (((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! execute_arbitration_isStuckByOthers)) && (! execute_arbitration_isFlushed)) && (! execute_DBusSimplePlugin_skipCmd)) && (! execute_DBusSimplePlugin_cmdSent)); + assign dBus_cmd_payload_wr = execute_MEMORY_STORE; assign dBus_cmd_payload_size = execute_INSTRUCTION[13 : 12]; always @ (*) begin case(dBus_cmd_payload_size) 2'b00 : begin - _zz_102_ = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; + _zz_81_ = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; end 2'b01 : begin - _zz_102_ = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; + _zz_81_ = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; end default : begin - _zz_102_ = execute_RS2[31 : 0]; + _zz_81_ = execute_RS2[31 : 0]; end endcase end - assign dBus_cmd_payload_data = _zz_102_; - assign _zz_58_ = dBus_cmd_payload_address[1 : 0]; + assign dBus_cmd_payload_data = _zz_81_; + assign _zz_61_ = dBus_cmd_payload_address[1 : 0]; always @ (*) begin case(dBus_cmd_payload_size) 2'b00 : begin - _zz_103_ = (4'b0001); + _zz_82_ = (4'b0001); end 2'b01 : begin - _zz_103_ = (4'b0011); + _zz_82_ = (4'b0011); end default : begin - _zz_103_ = (4'b1111); + _zz_82_ = (4'b1111); end endcase end - assign execute_DBusSimplePlugin_formalMask = (_zz_103_ <<< dBus_cmd_payload_address[1 : 0]); - assign _zz_57_ = dBus_rsp_data; + assign execute_DBusSimplePlugin_formalMask = (_zz_82_ <<< dBus_cmd_payload_address[1 : 0]); + assign dBus_cmd_payload_address = execute_SRC_ADD; + assign _zz_60_ = dBus_rsp_data; always @ (*) begin - _zz_73_ = execute_ALIGNEMENT_FAULT; - if((! ((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! execute_arbitration_isStuckByOthers))))begin - _zz_73_ = 1'b0; + DBusSimplePlugin_memoryExceptionPort_valid = 1'b0; + DBusSimplePlugin_memoryExceptionPort_payload_code = (4'bxxxx); + if(execute_ALIGNEMENT_FAULT)begin + DBusSimplePlugin_memoryExceptionPort_payload_code = {1'd0, _zz_168_}; + DBusSimplePlugin_memoryExceptionPort_valid = 1'b1; + end + if((! ((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (1'b0 || (! execute_arbitration_isStuckByOthers)))))begin + DBusSimplePlugin_memoryExceptionPort_valid = 1'b0; end end + assign DBusSimplePlugin_memoryExceptionPort_payload_badAddr = execute_REGFILE_WRITE_DATA; always @ (*) begin execute_DBusSimplePlugin_rspShifted = execute_MEMORY_READ_DATA; case(execute_MEMORY_ADDRESS_LOW) @@ -2341,20 +2289,185 @@ module VexRiscv ( endcase end - assign _zz_104_ = (execute_DBusSimplePlugin_rspShifted[7] && (! execute_INSTRUCTION[14])); + assign _zz_83_ = (execute_DBusSimplePlugin_rspShifted[7] && (! execute_INSTRUCTION[14])); + always @ (*) begin + _zz_84_[31] = _zz_83_; + _zz_84_[30] = _zz_83_; + _zz_84_[29] = _zz_83_; + _zz_84_[28] = _zz_83_; + _zz_84_[27] = _zz_83_; + _zz_84_[26] = _zz_83_; + _zz_84_[25] = _zz_83_; + _zz_84_[24] = _zz_83_; + _zz_84_[23] = _zz_83_; + _zz_84_[22] = _zz_83_; + _zz_84_[21] = _zz_83_; + _zz_84_[20] = _zz_83_; + _zz_84_[19] = _zz_83_; + _zz_84_[18] = _zz_83_; + _zz_84_[17] = _zz_83_; + _zz_84_[16] = _zz_83_; + _zz_84_[15] = _zz_83_; + _zz_84_[14] = _zz_83_; + _zz_84_[13] = _zz_83_; + _zz_84_[12] = _zz_83_; + _zz_84_[11] = _zz_83_; + _zz_84_[10] = _zz_83_; + _zz_84_[9] = _zz_83_; + _zz_84_[8] = _zz_83_; + _zz_84_[7 : 0] = execute_DBusSimplePlugin_rspShifted[7 : 0]; + end + + assign _zz_85_ = (execute_DBusSimplePlugin_rspShifted[15] && (! execute_INSTRUCTION[14])); + always @ (*) begin + _zz_86_[31] = _zz_85_; + _zz_86_[30] = _zz_85_; + _zz_86_[29] = _zz_85_; + _zz_86_[28] = _zz_85_; + _zz_86_[27] = _zz_85_; + _zz_86_[26] = _zz_85_; + _zz_86_[25] = _zz_85_; + _zz_86_[24] = _zz_85_; + _zz_86_[23] = _zz_85_; + _zz_86_[22] = _zz_85_; + _zz_86_[21] = _zz_85_; + _zz_86_[20] = _zz_85_; + _zz_86_[19] = _zz_85_; + _zz_86_[18] = _zz_85_; + _zz_86_[17] = _zz_85_; + _zz_86_[16] = _zz_85_; + _zz_86_[15 : 0] = execute_DBusSimplePlugin_rspShifted[15 : 0]; + end + + always @ (*) begin + case(_zz_163_) + 2'b00 : begin + execute_DBusSimplePlugin_rspFormated = _zz_84_; + end + 2'b01 : begin + execute_DBusSimplePlugin_rspFormated = _zz_86_; + end + default : begin + execute_DBusSimplePlugin_rspFormated = execute_DBusSimplePlugin_rspShifted; + end + endcase + end + + assign _zz_88_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000000100)) == (32'b00000000000000000000000000000100)); + assign _zz_89_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001001000)) == (32'b00000000000000000000000001001000)); + assign _zz_90_ = ((decode_INSTRUCTION & (32'b00000000000000000100000001010000)) == (32'b00000000000000000100000001010000)); + assign _zz_91_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001010000)) == (32'b00000000000000000000000000010000)); + assign _zz_87_ = {(_zz_91_ != (1'b0)),{({_zz_206_,_zz_207_} != (2'b00)),{({_zz_208_,_zz_209_} != (6'b000000)),{(_zz_210_ != _zz_211_),{_zz_212_,{_zz_213_,_zz_214_}}}}}}; + assign _zz_58_ = ({((decode_INSTRUCTION & (32'b00000000000000000000000001011111)) == (32'b00000000000000000000000000010111)),{((decode_INSTRUCTION & (32'b00000000000000000000000001111111)) == (32'b00000000000000000000000001101111)),{((decode_INSTRUCTION & (32'b00000000000000000001000001101111)) == (32'b00000000000000000000000000000011)),{((decode_INSTRUCTION & _zz_321_) == (32'b00000000000000000001000001110011)),{(_zz_322_ == _zz_323_),{_zz_324_,{_zz_325_,_zz_326_}}}}}}} != (20'b00000000000000000000)); + assign _zz_57_ = _zz_169_[0]; + assign _zz_92_ = _zz_87_[4 : 3]; + assign _zz_56_ = _zz_92_; + assign _zz_93_ = _zz_87_[6 : 5]; + assign _zz_55_ = _zz_93_; + assign _zz_54_ = _zz_170_[0]; + assign _zz_94_ = _zz_87_[9 : 8]; + assign _zz_53_ = _zz_94_; + assign _zz_95_ = _zz_87_[11 : 10]; + assign _zz_52_ = _zz_95_; + assign _zz_96_ = _zz_87_[13 : 12]; + assign _zz_51_ = _zz_96_; + assign _zz_97_ = _zz_87_[17 : 16]; + assign _zz_50_ = _zz_97_; + assign _zz_49_ = _zz_171_[0]; + assign _zz_48_ = _zz_172_[0]; + assign _zz_47_ = _zz_173_[0]; + assign _zz_46_ = _zz_174_[0]; + assign _zz_98_ = _zz_87_[23 : 22]; + assign _zz_45_ = _zz_98_; + assign _zz_44_ = _zz_175_[0]; + assign _zz_43_ = _zz_176_[0]; + assign decodeExceptionPort_valid = ((decode_arbitration_isValid && decode_INSTRUCTION_READY) && (! decode_LEGAL_INSTRUCTION)); + assign decodeExceptionPort_payload_code = (4'b0010); + assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION; + assign execute_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION[19 : 15]; + assign execute_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION[24 : 20]; + assign _zz_99_ = (! execute_arbitration_isStuck); + assign execute_RegFilePlugin_rs1Data = _zz_148_; + assign execute_RegFilePlugin_rs2Data = _zz_149_; + assign _zz_42_ = execute_RegFilePlugin_rs1Data; + assign _zz_41_ = execute_RegFilePlugin_rs2Data; + assign execute_RegFilePlugin_regFileWrite_valid = (execute_REGFILE_WRITE_VALID && execute_arbitration_isFiring); + assign execute_RegFilePlugin_regFileWrite_payload_address = execute_INSTRUCTION[11 : 7]; + assign execute_RegFilePlugin_regFileWrite_payload_data = _zz_59_; + always @ (*) begin + case(execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : begin + execute_IntAluPlugin_bitwise = (execute_SRC1 & execute_SRC2); + end + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : begin + execute_IntAluPlugin_bitwise = (execute_SRC1 | execute_SRC2); + end + default : begin + execute_IntAluPlugin_bitwise = (execute_SRC1 ^ execute_SRC2); + end + endcase + end + + always @ (*) begin + case(execute_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_BITWISE : begin + _zz_100_ = execute_IntAluPlugin_bitwise; + end + `AluCtrlEnum_defaultEncoding_SLT_SLTU : begin + _zz_100_ = {31'd0, _zz_177_}; + end + default : begin + _zz_100_ = execute_SRC_ADD_SUB; + end + endcase + end + + assign _zz_38_ = _zz_100_; + assign _zz_36_ = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS)); + always @ (*) begin + case(execute_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : begin + _zz_101_ = execute_RS1; + end + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : begin + _zz_101_ = {29'd0, _zz_178_}; + end + `Src1CtrlEnum_defaultEncoding_IMU : begin + _zz_101_ = {execute_INSTRUCTION[31 : 12],(12'b000000000000)}; + end + default : begin + _zz_101_ = {27'd0, _zz_179_}; + end + endcase + end + + assign _zz_35_ = _zz_101_; + assign _zz_102_ = _zz_180_[11]; + always @ (*) begin + _zz_103_[19] = _zz_102_; + _zz_103_[18] = _zz_102_; + _zz_103_[17] = _zz_102_; + _zz_103_[16] = _zz_102_; + _zz_103_[15] = _zz_102_; + _zz_103_[14] = _zz_102_; + _zz_103_[13] = _zz_102_; + _zz_103_[12] = _zz_102_; + _zz_103_[11] = _zz_102_; + _zz_103_[10] = _zz_102_; + _zz_103_[9] = _zz_102_; + _zz_103_[8] = _zz_102_; + _zz_103_[7] = _zz_102_; + _zz_103_[6] = _zz_102_; + _zz_103_[5] = _zz_102_; + _zz_103_[4] = _zz_102_; + _zz_103_[3] = _zz_102_; + _zz_103_[2] = _zz_102_; + _zz_103_[1] = _zz_102_; + _zz_103_[0] = _zz_102_; + end + + assign _zz_104_ = _zz_181_[11]; always @ (*) begin - _zz_105_[31] = _zz_104_; - _zz_105_[30] = _zz_104_; - _zz_105_[29] = _zz_104_; - _zz_105_[28] = _zz_104_; - _zz_105_[27] = _zz_104_; - _zz_105_[26] = _zz_104_; - _zz_105_[25] = _zz_104_; - _zz_105_[24] = _zz_104_; - _zz_105_[23] = _zz_104_; - _zz_105_[22] = _zz_104_; - _zz_105_[21] = _zz_104_; - _zz_105_[20] = _zz_104_; _zz_105_[19] = _zz_104_; _zz_105_[18] = _zz_104_; _zz_105_[17] = _zz_104_; @@ -2367,201 +2480,45 @@ module VexRiscv ( _zz_105_[10] = _zz_104_; _zz_105_[9] = _zz_104_; _zz_105_[8] = _zz_104_; - _zz_105_[7 : 0] = execute_DBusSimplePlugin_rspShifted[7 : 0]; - end - - assign _zz_106_ = (execute_DBusSimplePlugin_rspShifted[15] && (! execute_INSTRUCTION[14])); - always @ (*) begin - _zz_107_[31] = _zz_106_; - _zz_107_[30] = _zz_106_; - _zz_107_[29] = _zz_106_; - _zz_107_[28] = _zz_106_; - _zz_107_[27] = _zz_106_; - _zz_107_[26] = _zz_106_; - _zz_107_[25] = _zz_106_; - _zz_107_[24] = _zz_106_; - _zz_107_[23] = _zz_106_; - _zz_107_[22] = _zz_106_; - _zz_107_[21] = _zz_106_; - _zz_107_[20] = _zz_106_; - _zz_107_[19] = _zz_106_; - _zz_107_[18] = _zz_106_; - _zz_107_[17] = _zz_106_; - _zz_107_[16] = _zz_106_; - _zz_107_[15 : 0] = execute_DBusSimplePlugin_rspShifted[15 : 0]; - end - - always @ (*) begin - case(_zz_186_) - 2'b00 : begin - execute_DBusSimplePlugin_rspFormated = _zz_105_; - end - 2'b01 : begin - execute_DBusSimplePlugin_rspFormated = _zz_107_; - end - default : begin - execute_DBusSimplePlugin_rspFormated = execute_DBusSimplePlugin_rspShifted; - end - endcase - end - - assign _zz_72_ = IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_virtualAddress; - assign _zz_109_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001010000)) == (32'b00000000000000000000000000010000)); - assign _zz_110_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000000100)) == (32'b00000000000000000000000000000100)); - assign _zz_111_ = ((decode_INSTRUCTION & (32'b00000000000000000100000001010000)) == (32'b00000000000000000100000001010000)); - assign _zz_112_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001001000)) == (32'b00000000000000000000000001001000)); - assign _zz_108_ = {({(_zz_244_ == _zz_245_),(_zz_246_ == _zz_247_)} != (2'b00)),{((_zz_248_ == _zz_249_) != (1'b0)),{({_zz_250_,_zz_251_} != (4'b0000)),{(_zz_252_ != _zz_253_),{_zz_254_,{_zz_255_,_zz_256_}}}}}}; - assign _zz_113_ = _zz_108_[2 : 1]; - assign _zz_55_ = _zz_113_; - assign _zz_54_ = _zz_196_[0]; - assign _zz_114_ = _zz_108_[5 : 4]; - assign _zz_53_ = _zz_114_; - assign _zz_115_ = _zz_108_[7 : 6]; - assign _zz_52_ = _zz_115_; - assign _zz_51_ = _zz_197_[0]; - assign _zz_116_ = _zz_108_[11 : 10]; - assign _zz_50_ = _zz_116_; - assign _zz_117_ = _zz_108_[13 : 12]; - assign _zz_49_ = _zz_117_; - assign _zz_48_ = _zz_198_[0]; - assign _zz_47_ = _zz_199_[0]; - assign _zz_46_ = _zz_200_[0]; - assign _zz_118_ = _zz_108_[18 : 17]; - assign _zz_45_ = _zz_118_; - assign _zz_119_ = _zz_108_[20 : 19]; - assign _zz_44_ = _zz_119_; - assign _zz_43_ = _zz_201_[0]; - assign execute_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION[19 : 15]; - assign execute_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION[24 : 20]; - assign _zz_120_ = (! execute_arbitration_isStuck); - assign execute_RegFilePlugin_rs1Data = _zz_174_; - assign execute_RegFilePlugin_rs2Data = _zz_175_; - assign _zz_42_ = execute_RegFilePlugin_rs1Data; - assign _zz_41_ = execute_RegFilePlugin_rs2Data; - assign execute_RegFilePlugin_regFileWrite_valid = (execute_REGFILE_WRITE_VALID && execute_arbitration_isFiring); - assign execute_RegFilePlugin_regFileWrite_payload_address = execute_INSTRUCTION[11 : 7]; - assign execute_RegFilePlugin_regFileWrite_payload_data = _zz_56_; - always @ (*) begin - case(execute_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : begin - execute_IntAluPlugin_bitwise = (execute_SRC1 & execute_SRC2); - end - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : begin - execute_IntAluPlugin_bitwise = (execute_SRC1 | execute_SRC2); - end - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : begin - execute_IntAluPlugin_bitwise = (execute_SRC1 ^ execute_SRC2); - end - default : begin - execute_IntAluPlugin_bitwise = execute_SRC1; - end - endcase - end - - always @ (*) begin - case(execute_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_BITWISE : begin - _zz_121_ = execute_IntAluPlugin_bitwise; - end - `AluCtrlEnum_defaultEncoding_SLT_SLTU : begin - _zz_121_ = {31'd0, _zz_202_}; - end - default : begin - _zz_121_ = execute_SRC_ADD_SUB; - end - endcase - end - - assign _zz_38_ = _zz_121_; - always @ (*) begin - case(execute_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : begin - _zz_122_ = execute_RS1; - end - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : begin - _zz_122_ = {29'd0, _zz_203_}; - end - `Src1CtrlEnum_defaultEncoding_IMU : begin - _zz_122_ = {execute_INSTRUCTION[31 : 12],(12'b000000000000)}; - end - default : begin - _zz_122_ = {27'd0, _zz_204_}; - end - endcase - end - - assign _zz_36_ = _zz_122_; - assign _zz_123_ = _zz_205_[11]; - always @ (*) begin - _zz_124_[19] = _zz_123_; - _zz_124_[18] = _zz_123_; - _zz_124_[17] = _zz_123_; - _zz_124_[16] = _zz_123_; - _zz_124_[15] = _zz_123_; - _zz_124_[14] = _zz_123_; - _zz_124_[13] = _zz_123_; - _zz_124_[12] = _zz_123_; - _zz_124_[11] = _zz_123_; - _zz_124_[10] = _zz_123_; - _zz_124_[9] = _zz_123_; - _zz_124_[8] = _zz_123_; - _zz_124_[7] = _zz_123_; - _zz_124_[6] = _zz_123_; - _zz_124_[5] = _zz_123_; - _zz_124_[4] = _zz_123_; - _zz_124_[3] = _zz_123_; - _zz_124_[2] = _zz_123_; - _zz_124_[1] = _zz_123_; - _zz_124_[0] = _zz_123_; - end - - assign _zz_125_ = _zz_206_[11]; - always @ (*) begin - _zz_126_[19] = _zz_125_; - _zz_126_[18] = _zz_125_; - _zz_126_[17] = _zz_125_; - _zz_126_[16] = _zz_125_; - _zz_126_[15] = _zz_125_; - _zz_126_[14] = _zz_125_; - _zz_126_[13] = _zz_125_; - _zz_126_[12] = _zz_125_; - _zz_126_[11] = _zz_125_; - _zz_126_[10] = _zz_125_; - _zz_126_[9] = _zz_125_; - _zz_126_[8] = _zz_125_; - _zz_126_[7] = _zz_125_; - _zz_126_[6] = _zz_125_; - _zz_126_[5] = _zz_125_; - _zz_126_[4] = _zz_125_; - _zz_126_[3] = _zz_125_; - _zz_126_[2] = _zz_125_; - _zz_126_[1] = _zz_125_; - _zz_126_[0] = _zz_125_; + _zz_105_[7] = _zz_104_; + _zz_105_[6] = _zz_104_; + _zz_105_[5] = _zz_104_; + _zz_105_[4] = _zz_104_; + _zz_105_[3] = _zz_104_; + _zz_105_[2] = _zz_104_; + _zz_105_[1] = _zz_104_; + _zz_105_[0] = _zz_104_; end always @ (*) begin case(execute_SRC2_CTRL) `Src2CtrlEnum_defaultEncoding_RS : begin - _zz_127_ = execute_RS2; + _zz_106_ = execute_RS2; end `Src2CtrlEnum_defaultEncoding_IMI : begin - _zz_127_ = {_zz_124_,execute_INSTRUCTION[31 : 20]}; + _zz_106_ = {_zz_103_,execute_INSTRUCTION[31 : 20]}; end `Src2CtrlEnum_defaultEncoding_IMS : begin - _zz_127_ = {_zz_126_,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; + _zz_106_ = {_zz_105_,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; end default : begin - _zz_127_ = execute_PC; + _zz_106_ = execute_PC; end endcase end - assign _zz_34_ = _zz_127_; - assign execute_SrcPlugin_addSub = _zz_207_; + assign _zz_33_ = _zz_106_; + always @ (*) begin + execute_SrcPlugin_addSub = _zz_182_; + if(execute_SRC2_FORCE_ZERO)begin + execute_SrcPlugin_addSub = execute_SRC1; + end + end + assign execute_SrcPlugin_less = ((execute_SRC1[31] == execute_SRC2[31]) ? execute_SrcPlugin_addSub[31] : (execute_SRC_LESS_UNSIGNED ? execute_SRC2[31] : execute_SRC1[31])); - assign _zz_32_ = execute_SrcPlugin_addSub; assign _zz_31_ = execute_SrcPlugin_addSub; - assign _zz_30_ = execute_SrcPlugin_less; + assign _zz_30_ = execute_SrcPlugin_addSub; + assign _zz_29_ = execute_SrcPlugin_less; assign execute_LightShifterPlugin_isShift = (execute_SHIFT_CTRL != `ShiftCtrlEnum_defaultEncoding_DISABLE_1); assign execute_LightShifterPlugin_amplitude = (execute_LightShifterPlugin_isActive ? execute_LightShifterPlugin_amplitudeReg : execute_SRC2[4 : 0]); assign execute_LightShifterPlugin_shiftInput = (execute_LightShifterPlugin_isActive ? execute_LightShifterPlugin_shiftReg : execute_SRC1); @@ -2569,258 +2526,197 @@ module VexRiscv ( always @ (*) begin case(execute_SHIFT_CTRL) `ShiftCtrlEnum_defaultEncoding_SLL_1 : begin - _zz_128_ = (execute_LightShifterPlugin_shiftInput <<< 1); + _zz_107_ = (execute_LightShifterPlugin_shiftInput <<< 1); end default : begin - _zz_128_ = _zz_215_; + _zz_107_ = _zz_189_; end endcase end - assign _zz_28_ = _zz_69_; assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2); - assign _zz_129_ = execute_INSTRUCTION[14 : 12]; + assign _zz_108_ = execute_INSTRUCTION[14 : 12]; always @ (*) begin - if((_zz_129_ == (3'b000))) begin - _zz_130_ = execute_BranchPlugin_eq; - end else if((_zz_129_ == (3'b001))) begin - _zz_130_ = (! execute_BranchPlugin_eq); - end else if((((_zz_129_ & (3'b101)) == (3'b101)))) begin - _zz_130_ = (! execute_SRC_LESS); + if((_zz_108_ == (3'b000))) begin + _zz_109_ = execute_BranchPlugin_eq; + end else if((_zz_108_ == (3'b001))) begin + _zz_109_ = (! execute_BranchPlugin_eq); + end else if((((_zz_108_ & (3'b101)) == (3'b101)))) begin + _zz_109_ = (! execute_SRC_LESS); end else begin - _zz_130_ = execute_SRC_LESS; + _zz_109_ = execute_SRC_LESS; end end always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_INC : begin - _zz_131_ = 1'b0; + _zz_110_ = 1'b0; end `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_131_ = 1'b1; + _zz_110_ = 1'b1; end `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_131_ = 1'b1; + _zz_110_ = 1'b1; end default : begin - _zz_131_ = _zz_130_; + _zz_110_ = _zz_109_; end endcase end - assign _zz_27_ = _zz_131_; - assign _zz_132_ = _zz_217_[11]; + assign _zz_27_ = _zz_110_; + assign execute_BranchPlugin_branch_src1 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JALR) ? execute_RS1 : execute_PC); + assign _zz_111_ = _zz_191_[19]; always @ (*) begin - _zz_133_[19] = _zz_132_; - _zz_133_[18] = _zz_132_; - _zz_133_[17] = _zz_132_; - _zz_133_[16] = _zz_132_; - _zz_133_[15] = _zz_132_; - _zz_133_[14] = _zz_132_; - _zz_133_[13] = _zz_132_; - _zz_133_[12] = _zz_132_; - _zz_133_[11] = _zz_132_; - _zz_133_[10] = _zz_132_; - _zz_133_[9] = _zz_132_; - _zz_133_[8] = _zz_132_; - _zz_133_[7] = _zz_132_; - _zz_133_[6] = _zz_132_; - _zz_133_[5] = _zz_132_; - _zz_133_[4] = _zz_132_; - _zz_133_[3] = _zz_132_; - _zz_133_[2] = _zz_132_; - _zz_133_[1] = _zz_132_; - _zz_133_[0] = _zz_132_; + _zz_112_[10] = _zz_111_; + _zz_112_[9] = _zz_111_; + _zz_112_[8] = _zz_111_; + _zz_112_[7] = _zz_111_; + _zz_112_[6] = _zz_111_; + _zz_112_[5] = _zz_111_; + _zz_112_[4] = _zz_111_; + _zz_112_[3] = _zz_111_; + _zz_112_[2] = _zz_111_; + _zz_112_[1] = _zz_111_; + _zz_112_[0] = _zz_111_; end - assign _zz_134_ = _zz_218_[19]; + assign _zz_113_ = _zz_192_[11]; always @ (*) begin - _zz_135_[10] = _zz_134_; - _zz_135_[9] = _zz_134_; - _zz_135_[8] = _zz_134_; - _zz_135_[7] = _zz_134_; - _zz_135_[6] = _zz_134_; - _zz_135_[5] = _zz_134_; - _zz_135_[4] = _zz_134_; - _zz_135_[3] = _zz_134_; - _zz_135_[2] = _zz_134_; - _zz_135_[1] = _zz_134_; - _zz_135_[0] = _zz_134_; + _zz_114_[19] = _zz_113_; + _zz_114_[18] = _zz_113_; + _zz_114_[17] = _zz_113_; + _zz_114_[16] = _zz_113_; + _zz_114_[15] = _zz_113_; + _zz_114_[14] = _zz_113_; + _zz_114_[13] = _zz_113_; + _zz_114_[12] = _zz_113_; + _zz_114_[11] = _zz_113_; + _zz_114_[10] = _zz_113_; + _zz_114_[9] = _zz_113_; + _zz_114_[8] = _zz_113_; + _zz_114_[7] = _zz_113_; + _zz_114_[6] = _zz_113_; + _zz_114_[5] = _zz_113_; + _zz_114_[4] = _zz_113_; + _zz_114_[3] = _zz_113_; + _zz_114_[2] = _zz_113_; + _zz_114_[1] = _zz_113_; + _zz_114_[0] = _zz_113_; end - assign _zz_136_ = _zz_219_[11]; + assign _zz_115_ = _zz_193_[11]; always @ (*) begin - _zz_137_[18] = _zz_136_; - _zz_137_[17] = _zz_136_; - _zz_137_[16] = _zz_136_; - _zz_137_[15] = _zz_136_; - _zz_137_[14] = _zz_136_; - _zz_137_[13] = _zz_136_; - _zz_137_[12] = _zz_136_; - _zz_137_[11] = _zz_136_; - _zz_137_[10] = _zz_136_; - _zz_137_[9] = _zz_136_; - _zz_137_[8] = _zz_136_; - _zz_137_[7] = _zz_136_; - _zz_137_[6] = _zz_136_; - _zz_137_[5] = _zz_136_; - _zz_137_[4] = _zz_136_; - _zz_137_[3] = _zz_136_; - _zz_137_[2] = _zz_136_; - _zz_137_[1] = _zz_136_; - _zz_137_[0] = _zz_136_; + _zz_116_[18] = _zz_115_; + _zz_116_[17] = _zz_115_; + _zz_116_[16] = _zz_115_; + _zz_116_[15] = _zz_115_; + _zz_116_[14] = _zz_115_; + _zz_116_[13] = _zz_115_; + _zz_116_[12] = _zz_115_; + _zz_116_[11] = _zz_115_; + _zz_116_[10] = _zz_115_; + _zz_116_[9] = _zz_115_; + _zz_116_[8] = _zz_115_; + _zz_116_[7] = _zz_115_; + _zz_116_[6] = _zz_115_; + _zz_116_[5] = _zz_115_; + _zz_116_[4] = _zz_115_; + _zz_116_[3] = _zz_115_; + _zz_116_[2] = _zz_115_; + _zz_116_[1] = _zz_115_; + _zz_116_[0] = _zz_115_; end always @ (*) begin case(execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_138_ = (_zz_220_[1] ^ execute_RS1[1]); - end `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_138_ = _zz_221_[1]; + _zz_117_ = {{_zz_112_,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; end - default : begin - _zz_138_ = _zz_222_[1]; - end - endcase - end - - assign execute_BranchPlugin_missAlignedTarget = (execute_BRANCH_COND_RESULT && _zz_138_); - assign _zz_25_ = ((execute_PREDICTION_HAD_BRANCHED2 != execute_BRANCH_COND_RESULT) || execute_BranchPlugin_missAlignedTarget); - always @ (*) begin - case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JALR : begin - execute_BranchPlugin_branch_src1 = execute_RS1; - execute_BranchPlugin_branch_src2 = {_zz_140_,execute_INSTRUCTION[31 : 20]}; + _zz_117_ = {_zz_114_,execute_INSTRUCTION[31 : 20]}; end default : begin - execute_BranchPlugin_branch_src1 = execute_PC; - execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_142_,{{{_zz_348_,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_144_,{{{_zz_349_,_zz_350_},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); - if((execute_PREDICTION_HAD_BRANCHED2 && (! execute_BranchPlugin_missAlignedTarget)))begin - execute_BranchPlugin_branch_src2 = {29'd0, _zz_226_}; - end + _zz_117_ = {{_zz_116_,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; end endcase end - assign _zz_139_ = _zz_223_[11]; - always @ (*) begin - _zz_140_[19] = _zz_139_; - _zz_140_[18] = _zz_139_; - _zz_140_[17] = _zz_139_; - _zz_140_[16] = _zz_139_; - _zz_140_[15] = _zz_139_; - _zz_140_[14] = _zz_139_; - _zz_140_[13] = _zz_139_; - _zz_140_[12] = _zz_139_; - _zz_140_[11] = _zz_139_; - _zz_140_[10] = _zz_139_; - _zz_140_[9] = _zz_139_; - _zz_140_[8] = _zz_139_; - _zz_140_[7] = _zz_139_; - _zz_140_[6] = _zz_139_; - _zz_140_[5] = _zz_139_; - _zz_140_[4] = _zz_139_; - _zz_140_[3] = _zz_139_; - _zz_140_[2] = _zz_139_; - _zz_140_[1] = _zz_139_; - _zz_140_[0] = _zz_139_; - end - - assign _zz_141_ = _zz_224_[19]; - always @ (*) begin - _zz_142_[10] = _zz_141_; - _zz_142_[9] = _zz_141_; - _zz_142_[8] = _zz_141_; - _zz_142_[7] = _zz_141_; - _zz_142_[6] = _zz_141_; - _zz_142_[5] = _zz_141_; - _zz_142_[4] = _zz_141_; - _zz_142_[3] = _zz_141_; - _zz_142_[2] = _zz_141_; - _zz_142_[1] = _zz_141_; - _zz_142_[0] = _zz_141_; - end - - assign _zz_143_ = _zz_225_[11]; - always @ (*) begin - _zz_144_[18] = _zz_143_; - _zz_144_[17] = _zz_143_; - _zz_144_[16] = _zz_143_; - _zz_144_[15] = _zz_143_; - _zz_144_[14] = _zz_143_; - _zz_144_[13] = _zz_143_; - _zz_144_[12] = _zz_143_; - _zz_144_[11] = _zz_143_; - _zz_144_[10] = _zz_143_; - _zz_144_[9] = _zz_143_; - _zz_144_[8] = _zz_143_; - _zz_144_[7] = _zz_143_; - _zz_144_[6] = _zz_143_; - _zz_144_[5] = _zz_143_; - _zz_144_[4] = _zz_143_; - _zz_144_[3] = _zz_143_; - _zz_144_[2] = _zz_143_; - _zz_144_[1] = _zz_143_; - _zz_144_[0] = _zz_143_; - end - + assign execute_BranchPlugin_branch_src2 = _zz_117_; assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2); - assign _zz_24_ = {execute_BranchPlugin_branchAdder[31 : 1],(1'b0)}; - assign _zz_74_ = ((execute_arbitration_isValid && (! execute_arbitration_isStuckByOthers)) && execute_BRANCH_DO); + assign _zz_25_ = {execute_BranchPlugin_branchAdder[31 : 1],(1'b0)}; + assign BranchPlugin_jumpInterface_valid = ((execute_arbitration_isValid && (! execute_arbitration_isStuckByOthers)) && execute_BRANCH_DO); + assign BranchPlugin_jumpInterface_payload = execute_BRANCH_CALC; always @ (*) begin - _zz_75_ = (execute_arbitration_isValid && (execute_BRANCH_DO && execute_BRANCH_CALC[1])); + BranchPlugin_branchExceptionPort_valid = ((execute_arbitration_isValid && execute_BRANCH_DO) && BranchPlugin_jumpInterface_payload[1]); if(1'b0)begin - _zz_75_ = 1'b0; + BranchPlugin_branchExceptionPort_valid = 1'b0; + end + end + + assign BranchPlugin_branchExceptionPort_payload_code = (4'b0000); + assign BranchPlugin_branchExceptionPort_payload_badAddr = BranchPlugin_jumpInterface_payload; + always @ (*) begin + CsrPlugin_privilege = (2'b11); + if(CsrPlugin_forceMachineWire)begin + CsrPlugin_privilege = (2'b11); end end assign CsrPlugin_misa_base = (2'b01); assign CsrPlugin_misa_extensions = (26'b00000000000000000000000000); - assign CsrPlugin_medeleg = (32'b00000000000000000000000000000000); - assign CsrPlugin_mideleg = (32'b00000000000000000000000000000000); - assign _zz_145_ = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); - assign _zz_146_ = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); - assign _zz_147_ = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); - assign CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode = 1'b0; - assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = (2'b11); - assign execute_exception_agregat_valid = ({_zz_78_,{_zz_75_,_zz_73_}} != (3'b000)); - assign _zz_148_ = {_zz_78_,{_zz_75_,_zz_73_}}; - assign _zz_149_ = (_zz_148_ & (~ _zz_227_)); - assign _zz_150_ = _zz_149_[1]; - assign _zz_151_ = _zz_149_[2]; - assign _zz_152_ = {_zz_151_,_zz_150_}; - assign execute_exception_agregat_payload_code = _zz_177_; - assign execute_exception_agregat_payload_badAddr = _zz_178_; - assign CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; + assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = (2'b11); + assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege); + assign _zz_118_ = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; + assign _zz_119_ = _zz_194_[0]; + assign _zz_120_ = {CsrPlugin_selfException_valid,{BranchPlugin_branchExceptionPort_valid,DBusSimplePlugin_memoryExceptionPort_valid}}; + assign _zz_121_ = (_zz_120_ & (~ _zz_196_)); + assign _zz_122_ = _zz_121_[1]; + assign _zz_123_ = _zz_121_[2]; + assign _zz_124_ = {_zz_123_,_zz_122_}; + always @ (*) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; + if(_zz_155_)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b1; + end + if(decode_arbitration_isFlushed)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b0; + end + end + + assign CsrPlugin_exceptionPendings_0 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; + assign CsrPlugin_exceptionPendings_1 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; always @ (*) begin CsrPlugin_interrupt = 1'b0; CsrPlugin_interruptCode = (4'bxxxx); - if(CsrPlugin_mstatus_MIE)begin - if(({_zz_147_,{_zz_146_,_zz_145_}} != (3'b000)))begin + CsrPlugin_interruptTargetPrivilege = (2'bxx); + if((CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < (2'b11))))begin + if((((CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE) && 1'b1) && (! 1'b0)))begin CsrPlugin_interrupt = 1'b1; - end - if(_zz_145_)begin CsrPlugin_interruptCode = (4'b0111); + CsrPlugin_interruptTargetPrivilege = (2'b11); end - if(_zz_146_)begin + if((((CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE) && 1'b1) && (! 1'b0)))begin + CsrPlugin_interrupt = 1'b1; CsrPlugin_interruptCode = (4'b0011); + CsrPlugin_interruptTargetPrivilege = (2'b11); end - if(_zz_147_)begin + if((((CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE) && 1'b1) && (! 1'b0)))begin + CsrPlugin_interrupt = 1'b1; CsrPlugin_interruptCode = (4'b1011); + CsrPlugin_interruptTargetPrivilege = (2'b11); end end - if((! 1'b1))begin + if((! CsrPlugin_allowInterrupts))begin CsrPlugin_interrupt = 1'b0; end end - assign CsrPlugin_interruptTargetPrivilege = (2'b11); - assign CsrPlugin_exception = (CsrPlugin_exceptionPortCtrl_exceptionValids_execute && 1'b1); + assign CsrPlugin_exception = (CsrPlugin_exceptionPortCtrl_exceptionValids_execute && CsrPlugin_allowException); assign CsrPlugin_lastStageWasWfi = 1'b0; always @ (*) begin - CsrPlugin_pipelineLiberator_done = ((! (execute_arbitration_isValid != (1'b0))) && IBusCachedPlugin_injector_nextPcCalc_valids_2); + CsrPlugin_pipelineLiberator_done = ((! (execute_arbitration_isValid != (1'b0))) && IBusCachedPlugin_pcValids_1); if((CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute != (1'b0)))begin CsrPlugin_pipelineLiberator_done = 1'b0; end @@ -2844,9 +2740,23 @@ module VexRiscv ( end end - assign contextSwitching = _zz_76_; - assign _zz_22_ = (! (((decode_INSTRUCTION[14 : 13] == (2'b01)) && (decode_INSTRUCTION[19 : 15] == (5'b00000))) || ((decode_INSTRUCTION[14 : 13] == (2'b11)) && (decode_INSTRUCTION[19 : 15] == (5'b00000))))); - assign _zz_21_ = (decode_INSTRUCTION[13 : 7] != (7'b0100000)); + always @ (*) begin + CsrPlugin_xtvec_mode = (2'bxx); + CsrPlugin_xtvec_base = (30'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx); + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_xtvec_mode = CsrPlugin_mtvec_mode; + CsrPlugin_xtvec_base = CsrPlugin_mtvec_base; + end + default : begin + end + endcase + end + + assign contextSwitching = CsrPlugin_jumpInterface_valid; + assign _zz_23_ = (! (((decode_INSTRUCTION[14 : 13] == (2'b01)) && (decode_INSTRUCTION[19 : 15] == (5'b00000))) || ((decode_INSTRUCTION[14 : 13] == (2'b11)) && (decode_INSTRUCTION[19 : 15] == (5'b00000))))); + assign _zz_22_ = (decode_INSTRUCTION[13 : 7] != (7'b0100000)); + assign execute_CsrPlugin_inWfi = 1'b0; assign execute_CsrPlugin_blockedBySideEffects = 1'b0; always @ (*) begin execute_CsrPlugin_illegalAccess = 1'b1; @@ -2854,7 +2764,7 @@ module VexRiscv ( case(execute_CsrPlugin_csrAddress) 12'b101111000000 : begin execute_CsrPlugin_illegalAccess = 1'b0; - execute_CsrPlugin_readData[31 : 0] = _zz_153_; + execute_CsrPlugin_readData[31 : 0] = _zz_125_; end 12'b001100000000 : begin execute_CsrPlugin_illegalAccess = 1'b0; @@ -2887,7 +2797,7 @@ module VexRiscv ( if(execute_CSR_READ_OPCODE)begin execute_CsrPlugin_illegalAccess = 1'b0; end - execute_CsrPlugin_readData[31 : 0] = _zz_154_; + execute_CsrPlugin_readData[31 : 0] = _zz_126_; end 12'b001101000000 : begin execute_CsrPlugin_illegalAccess = 1'b0; @@ -2920,64 +2830,73 @@ module VexRiscv ( always @ (*) begin execute_CsrPlugin_illegalInstruction = 1'b0; if((execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)))begin - if((execute_INSTRUCTION[29 : 28] != CsrPlugin_privilege))begin + if((CsrPlugin_privilege < execute_INSTRUCTION[29 : 28]))begin execute_CsrPlugin_illegalInstruction = 1'b1; end end end always @ (*) begin - _zz_78_ = 1'b0; - _zz_79_ = (4'bxxxx); + CsrPlugin_selfException_valid = 1'b0; + CsrPlugin_selfException_payload_code = (4'bxxxx); if((execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)))begin - _zz_78_ = 1'b1; - _zz_79_ = (4'b1011); + CsrPlugin_selfException_valid = 1'b1; + case(CsrPlugin_privilege) + 2'b00 : begin + CsrPlugin_selfException_payload_code = (4'b1000); + end + default : begin + CsrPlugin_selfException_payload_code = (4'b1011); + end + endcase end if((execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_EBREAK)))begin - _zz_78_ = 1'b1; - _zz_79_ = (4'b0011); + CsrPlugin_selfException_valid = 1'b1; + CsrPlugin_selfException_payload_code = (4'b0011); end end + assign CsrPlugin_selfException_payload_badAddr = execute_INSTRUCTION; assign execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); assign execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); assign execute_CsrPlugin_writeEnable = ((execute_CsrPlugin_writeInstruction && (! execute_CsrPlugin_blockedBySideEffects)) && (! execute_arbitration_isStuckByOthers)); assign execute_CsrPlugin_readEnable = ((execute_CsrPlugin_readInstruction && (! execute_CsrPlugin_blockedBySideEffects)) && (! execute_arbitration_isStuckByOthers)); + assign execute_CsrPlugin_readToWriteData = execute_CsrPlugin_readData; always @ (*) begin - case(_zz_188_) + case(_zz_164_) 1'b0 : begin execute_CsrPlugin_writeData = execute_SRC1; end default : begin - execute_CsrPlugin_writeData = (execute_INSTRUCTION[12] ? (execute_CsrPlugin_readData & (~ execute_SRC1)) : (execute_CsrPlugin_readData | execute_SRC1)); + execute_CsrPlugin_writeData = (execute_INSTRUCTION[12] ? (execute_CsrPlugin_readToWriteData & (~ execute_SRC1)) : (execute_CsrPlugin_readToWriteData | execute_SRC1)); end endcase end assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20]; - assign _zz_154_ = (_zz_153_ & externalInterruptArray_regNext); - assign externalInterrupt = (_zz_154_ != (32'b00000000000000000000000000000000)); - assign _zz_20_ = decode_ALU_CTRL; - assign _zz_18_ = _zz_45_; - assign _zz_37_ = decode_to_execute_ALU_CTRL; - assign _zz_17_ = decode_SRC2_CTRL; - assign _zz_15_ = _zz_55_; - assign _zz_33_ = decode_to_execute_SRC2_CTRL; - assign _zz_14_ = decode_ENV_CTRL; - assign _zz_12_ = _zz_53_; - assign _zz_23_ = decode_to_execute_ENV_CTRL; - assign _zz_11_ = decode_BRANCH_CTRL; - assign _zz_60_ = _zz_44_; - assign _zz_26_ = decode_to_execute_BRANCH_CTRL; - assign _zz_9_ = decode_SHIFT_CTRL; - assign _zz_7_ = _zz_50_; - assign _zz_29_ = decode_to_execute_SHIFT_CTRL; - assign _zz_6_ = decode_ALU_BITWISE_CTRL; - assign _zz_4_ = _zz_49_; + assign _zz_126_ = (_zz_125_ & externalInterruptArray_regNext); + assign externalInterrupt = (_zz_126_ != (32'b00000000000000000000000000000000)); + assign _zz_21_ = decode_ALU_BITWISE_CTRL; + assign _zz_19_ = _zz_45_; assign _zz_39_ = decode_to_execute_ALU_BITWISE_CTRL; - assign _zz_3_ = decode_SRC1_CTRL; + assign _zz_18_ = decode_SHIFT_CTRL; + assign _zz_16_ = _zz_56_; + assign _zz_28_ = decode_to_execute_SHIFT_CTRL; + assign _zz_15_ = decode_BRANCH_CTRL; + assign _zz_13_ = _zz_51_; + assign _zz_26_ = decode_to_execute_BRANCH_CTRL; + assign _zz_12_ = decode_ALU_CTRL; + assign _zz_10_ = _zz_53_; + assign _zz_37_ = decode_to_execute_ALU_CTRL; + assign _zz_9_ = decode_SRC1_CTRL; + assign _zz_7_ = _zz_50_; + assign _zz_34_ = decode_to_execute_SRC1_CTRL; + assign _zz_6_ = decode_SRC2_CTRL; + assign _zz_4_ = _zz_55_; + assign _zz_32_ = decode_to_execute_SRC2_CTRL; + assign _zz_3_ = decode_ENV_CTRL; assign _zz_1_ = _zz_52_; - assign _zz_35_ = decode_to_execute_SRC1_CTRL; + assign _zz_24_ = decode_to_execute_ENV_CTRL; assign decode_arbitration_isFlushed = ({execute_arbitration_flushAll,decode_arbitration_flushAll} != (2'b00)); assign execute_arbitration_isFlushed = (execute_arbitration_flushAll != (1'b0)); assign decode_arbitration_isStuckByOthers = (decode_arbitration_haltByOther || (1'b0 || execute_arbitration_isStuck)); @@ -2988,8 +2907,8 @@ module VexRiscv ( assign execute_arbitration_isStuck = (execute_arbitration_haltItself || execute_arbitration_isStuckByOthers); assign execute_arbitration_isMoving = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)); assign execute_arbitration_isFiring = ((execute_arbitration_isValid && (! execute_arbitration_isStuck)) && (! execute_arbitration_removeIt)); - assign iBusWishbone_ADR = {_zz_236_,_zz_155_}; - assign iBusWishbone_CTI = ((_zz_155_ == (3'b111)) ? (3'b111) : (3'b010)); + assign iBusWishbone_ADR = {_zz_203_,_zz_127_}; + assign iBusWishbone_CTI = ((_zz_127_ == (3'b111)) ? (3'b111) : (3'b010)); assign iBusWishbone_BTE = (2'b00); assign iBusWishbone_SEL = (4'b1111); assign iBusWishbone_WE = 1'b0; @@ -2997,14 +2916,14 @@ module VexRiscv ( always @ (*) begin iBusWishbone_CYC = 1'b0; iBusWishbone_STB = 1'b0; - if(_zz_184_)begin + if(_zz_161_)begin iBusWishbone_CYC = 1'b1; iBusWishbone_STB = 1'b1; end end assign iBus_cmd_ready = (iBus_cmd_valid && iBusWishbone_ACK); - assign iBus_rsp_valid = _zz_156_; + assign iBus_rsp_valid = _zz_128_; assign iBus_rsp_payload_data = iBusWishbone_DAT_MISO_regNext; assign iBus_rsp_payload_error = 1'b0; assign dBus_cmd_halfPipe_valid = dBus_cmd_halfPipe_regs_valid; @@ -3019,19 +2938,19 @@ module VexRiscv ( always @ (*) begin case(dBus_cmd_halfPipe_payload_size) 2'b00 : begin - _zz_157_ = (4'b0001); + _zz_129_ = (4'b0001); end 2'b01 : begin - _zz_157_ = (4'b0011); + _zz_129_ = (4'b0011); end default : begin - _zz_157_ = (4'b1111); + _zz_129_ = (4'b1111); end endcase end always @ (*) begin - dBusWishbone_SEL = _zz_237_[3:0]; + dBusWishbone_SEL = _zz_204_[3:0]; if((! dBus_cmd_halfPipe_payload_wr))begin dBusWishbone_SEL = (4'b1111); end @@ -3047,33 +2966,28 @@ module VexRiscv ( assign dBus_rsp_error = 1'b0; always @ (posedge clk) begin if(reset) begin - CsrPlugin_privilege <= (2'b11); IBusCachedPlugin_fetchPc_pcReg <= externalResetVector; IBusCachedPlugin_fetchPc_inc <= 1'b0; - _zz_86_ <= 1'b0; - _zz_92_ <= 1'b0; - _zz_94_ <= 1'b0; + _zz_75_ <= 1'b0; + _zz_80_ <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; - IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; IBusCachedPlugin_injector_decodeRemoved <= 1'b0; execute_DBusSimplePlugin_cmdSent <= 1'b0; execute_LightShifterPlugin_isActive <= 1'b0; CsrPlugin_mstatus_MIE <= 1'b0; CsrPlugin_mstatus_MPIE <= 1'b0; CsrPlugin_mstatus_MPP <= (2'b11); - CsrPlugin_mip_MEIP <= 1'b0; - CsrPlugin_mip_MTIP <= 1'b0; - CsrPlugin_mip_MSIP <= 1'b0; CsrPlugin_mie_MEIE <= 1'b0; CsrPlugin_mie_MTIE <= 1'b0; CsrPlugin_mie_MSIE <= 1'b0; + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= 1'b0; CsrPlugin_hadException <= 1'b0; - _zz_153_ <= (32'b00000000000000000000000000000000); + _zz_125_ <= (32'b00000000000000000000000000000000); execute_arbitration_isValid <= 1'b0; - _zz_155_ <= (3'b000); - _zz_156_ <= 1'b0; + _zz_127_ <= (3'b000); + _zz_128_ <= 1'b0; dBus_cmd_halfPipe_regs_valid <= 1'b0; dBus_cmd_halfPipe_regs_ready <= 1'b1; end else begin @@ -3083,53 +2997,38 @@ module VexRiscv ( if(IBusCachedPlugin_jump_pcLoad_valid)begin IBusCachedPlugin_fetchPc_inc <= 1'b0; end - if(_zz_183_)begin + if(_zz_160_)begin IBusCachedPlugin_fetchPc_inc <= 1'b1; end if(IBusCachedPlugin_fetchPc_samplePcNext)begin IBusCachedPlugin_fetchPc_pcReg <= IBusCachedPlugin_fetchPc_pc; end - _zz_86_ <= 1'b1; - if((IBusCachedPlugin_jump_pcLoad_valid || _zz_66_))begin - _zz_92_ <= 1'b0; + _zz_75_ <= 1'b1; + if((IBusCachedPlugin_jump_pcLoad_valid || IBusCachedPlugin_fetcherflushIt))begin + _zz_80_ <= 1'b0; end - if(_zz_90_)begin - _zz_92_ <= IBusCachedPlugin_iBusRsp_stages_0_output_valid; + if(_zz_78_)begin + _zz_80_ <= IBusCachedPlugin_iBusRsp_stages_0_output_valid; end - if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin - _zz_94_ <= IBusCachedPlugin_iBusRsp_stages_1_output_valid; - end - if((IBusCachedPlugin_jump_pcLoad_valid || _zz_66_))begin - _zz_94_ <= 1'b0; - end - if((IBusCachedPlugin_jump_pcLoad_valid || _zz_66_))begin + if((IBusCachedPlugin_jump_pcLoad_valid || IBusCachedPlugin_fetcherflushIt))begin IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; end - if((! (! IBusCachedPlugin_iBusRsp_stages_1_input_ready)))begin + if((! (! IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready)))begin IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b1; end - if((IBusCachedPlugin_jump_pcLoad_valid || _zz_66_))begin + if((IBusCachedPlugin_jump_pcLoad_valid || IBusCachedPlugin_fetcherflushIt))begin IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; end - if((! (! IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready)))begin - IBusCachedPlugin_injector_nextPcCalc_valids_1 <= IBusCachedPlugin_injector_nextPcCalc_valids_0; - end - if((IBusCachedPlugin_jump_pcLoad_valid || _zz_66_))begin - IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; - end - if((IBusCachedPlugin_jump_pcLoad_valid || _zz_66_))begin - IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; - end if((! execute_arbitration_isStuck))begin - IBusCachedPlugin_injector_nextPcCalc_valids_2 <= IBusCachedPlugin_injector_nextPcCalc_valids_1; + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= IBusCachedPlugin_injector_nextPcCalc_valids_0; end - if((IBusCachedPlugin_jump_pcLoad_valid || _zz_66_))begin - IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; + if((IBusCachedPlugin_jump_pcLoad_valid || IBusCachedPlugin_fetcherflushIt))begin + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; end if(decode_arbitration_removeIt)begin IBusCachedPlugin_injector_decodeRemoved <= 1'b1; end - if((IBusCachedPlugin_jump_pcLoad_valid || _zz_66_))begin + if((IBusCachedPlugin_jump_pcLoad_valid || IBusCachedPlugin_fetcherflushIt))begin IBusCachedPlugin_injector_decodeRemoved <= 1'b0; end if((dBus_cmd_valid && dBus_cmd_ready))begin @@ -3138,8 +3037,8 @@ module VexRiscv ( if((! execute_arbitration_isStuck))begin execute_DBusSimplePlugin_cmdSent <= 1'b0; end - if(_zz_179_)begin - if(_zz_180_)begin + if(_zz_153_)begin + if(_zz_154_)begin execute_LightShifterPlugin_isActive <= 1'b1; if(execute_LightShifterPlugin_done)begin execute_LightShifterPlugin_isActive <= 1'b0; @@ -3149,16 +3048,18 @@ module VexRiscv ( if(execute_arbitration_removeIt)begin execute_LightShifterPlugin_isActive <= 1'b0; end - CsrPlugin_mip_MEIP <= externalInterrupt; - CsrPlugin_mip_MTIP <= timerInterrupt; + if((! decode_arbitration_isStuck))begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; + end else begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= CsrPlugin_exceptionPortCtrl_exceptionValids_decode; + end if((! execute_arbitration_isStuck))begin - CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= 1'b0; + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= (CsrPlugin_exceptionPortCtrl_exceptionValids_decode && (! decode_arbitration_isStuck)); end else begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= 1'b0; end CsrPlugin_hadException <= CsrPlugin_exception; - if(_zz_181_)begin - CsrPlugin_privilege <= CsrPlugin_targetPrivilege; + if(_zz_157_)begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mstatus_MIE <= 1'b0; @@ -3169,13 +3070,12 @@ module VexRiscv ( end endcase end - if(_zz_182_)begin - case(_zz_187_) + if(_zz_158_)begin + case(_zz_159_) 2'b11 : begin - CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE; CsrPlugin_mstatus_MPP <= (2'b00); + CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE; CsrPlugin_mstatus_MPIE <= 1'b1; - CsrPlugin_privilege <= CsrPlugin_mstatus_MPP; end default : begin end @@ -3190,14 +3090,14 @@ module VexRiscv ( case(execute_CsrPlugin_csrAddress) 12'b101111000000 : begin if(execute_CsrPlugin_writeEnable)begin - _zz_153_ <= execute_CsrPlugin_writeData[31 : 0]; + _zz_125_ <= execute_CsrPlugin_writeData[31 : 0]; end end 12'b001100000000 : begin if(execute_CsrPlugin_writeEnable)begin CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11]; - CsrPlugin_mstatus_MPIE <= _zz_230_[0]; - CsrPlugin_mstatus_MIE <= _zz_231_[0]; + CsrPlugin_mstatus_MPIE <= _zz_197_[0]; + CsrPlugin_mstatus_MIE <= _zz_198_[0]; end end 12'b001101000001 : begin @@ -3205,9 +3105,6 @@ module VexRiscv ( 12'b001100000101 : begin end 12'b001101000100 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mip_MSIP <= _zz_232_[0]; - end end 12'b001101000011 : begin end @@ -3217,9 +3114,9 @@ module VexRiscv ( end 12'b001100000100 : begin if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mie_MEIE <= _zz_233_[0]; - CsrPlugin_mie_MTIE <= _zz_234_[0]; - CsrPlugin_mie_MSIE <= _zz_235_[0]; + CsrPlugin_mie_MEIE <= _zz_200_[0]; + CsrPlugin_mie_MTIE <= _zz_201_[0]; + CsrPlugin_mie_MSIE <= _zz_202_[0]; end end 12'b001101000010 : begin @@ -3227,13 +3124,13 @@ module VexRiscv ( default : begin end endcase - if(_zz_184_)begin + if(_zz_161_)begin if(iBusWishbone_ACK)begin - _zz_155_ <= (_zz_155_ + (3'b001)); + _zz_127_ <= (_zz_127_ + (3'b001)); end end - _zz_156_ <= (iBusWishbone_CYC && iBusWishbone_ACK); - if(_zz_185_)begin + _zz_128_ <= (iBusWishbone_CYC && iBusWishbone_ACK); + if(_zz_162_)begin dBus_cmd_halfPipe_regs_valid <= dBus_cmd_valid; dBus_cmd_halfPipe_regs_ready <= (! dBus_cmd_valid); end else begin @@ -3244,46 +3141,41 @@ module VexRiscv ( end always @ (posedge clk) begin - if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin - _zz_95_ <= IBusCachedPlugin_iBusRsp_stages_1_output_payload; - end - if(IBusCachedPlugin_iBusRsp_stages_1_input_ready)begin + if(IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready)begin IBusCachedPlugin_s1_tightlyCoupledHit <= IBusCachedPlugin_s0_tightlyCoupledHit; end - if(IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready)begin - IBusCachedPlugin_s2_tightlyCoupledHit <= IBusCachedPlugin_s1_tightlyCoupledHit; - end if((! execute_arbitration_isStuckByOthers))begin - execute_LightShifterPlugin_shiftReg <= _zz_56_; + execute_LightShifterPlugin_shiftReg <= _zz_59_; end - if(_zz_179_)begin - if(_zz_180_)begin + if(_zz_153_)begin + if(_zz_154_)begin execute_LightShifterPlugin_amplitudeReg <= (execute_LightShifterPlugin_amplitude - (5'b00001)); end end + CsrPlugin_mip_MEIP <= externalInterrupt; + CsrPlugin_mip_MTIP <= timerInterrupt; + CsrPlugin_mip_MSIP <= softwareInterrupt; CsrPlugin_mcycle <= (CsrPlugin_mcycle + (64'b0000000000000000000000000000000000000000000000000000000000000001)); if(execute_arbitration_isFiring)begin CsrPlugin_minstret <= (CsrPlugin_minstret + (64'b0000000000000000000000000000000000000000000000000000000000000001)); end - if(execute_exception_agregat_valid)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= execute_exception_agregat_payload_code; - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= execute_exception_agregat_payload_badAddr; + if(_zz_155_)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_119_ ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_119_ ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); end - if((CsrPlugin_exception || CsrPlugin_interruptJump))begin - case(CsrPlugin_privilege) - 2'b11 : begin - CsrPlugin_mepc <= execute_PC; - end - default : begin - end - endcase + if(_zz_156_)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= _zz_151_; + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= _zz_152_; end - if(_zz_181_)begin + if(_zz_157_)begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException); CsrPlugin_mcause_exceptionCode <= CsrPlugin_trapCause; - CsrPlugin_mtval <= CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; + CsrPlugin_mepc <= execute_PC; + if(CsrPlugin_hadException)begin + CsrPlugin_mtval <= CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; + end end default : begin end @@ -3291,61 +3183,61 @@ module VexRiscv ( end externalInterruptArray_regNext <= externalInterruptArray; if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED; + decode_to_execute_ALU_BITWISE_CTRL <= _zz_20_; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SHIFT_CTRL <= _zz_17_; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_BRANCH_CTRL <= _zz_14_; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_MEMORY_STORE <= decode_MEMORY_STORE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC2_FORCE_ZERO <= decode_SRC2_FORCE_ZERO; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_ALU_CTRL <= _zz_11_; end if((! execute_arbitration_isStuck))begin decode_to_execute_SRC_USE_SUB_LESS <= decode_SRC_USE_SUB_LESS; end if((! execute_arbitration_isStuck))begin - decode_to_execute_ALU_CTRL <= _zz_19_; - end - if((! execute_arbitration_isStuck))begin - decode_to_execute_INSTRUCTION <= decode_INSTRUCTION; + decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID; end if((! execute_arbitration_isStuck))begin decode_to_execute_CSR_READ_OPCODE <= decode_CSR_READ_OPCODE; end if((! execute_arbitration_isStuck))begin - decode_to_execute_CSR_WRITE_OPCODE <= decode_CSR_WRITE_OPCODE; - end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC2_CTRL <= _zz_16_; - end - if((! execute_arbitration_isStuck))begin - decode_to_execute_IS_CSR <= decode_IS_CSR; - end - if((! execute_arbitration_isStuck))begin - decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID; + decode_to_execute_SRC1_CTRL <= _zz_8_; end if((! execute_arbitration_isStuck))begin decode_to_execute_MEMORY_ENABLE <= decode_MEMORY_ENABLE; end if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_CSR <= decode_IS_CSR; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC2_CTRL <= _zz_5_; + end + if(((! execute_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_execute)))begin decode_to_execute_PC <= decode_PC; end if((! execute_arbitration_isStuck))begin - decode_to_execute_PREDICTION_HAD_BRANCHED2 <= decode_PREDICTION_HAD_BRANCHED2; + decode_to_execute_INSTRUCTION <= decode_INSTRUCTION; end if((! execute_arbitration_isStuck))begin - decode_to_execute_FLUSH_ALL <= decode_FLUSH_ALL; + decode_to_execute_FORMAL_PC_NEXT <= _zz_66_; end if((! execute_arbitration_isStuck))begin - decode_to_execute_ENV_CTRL <= _zz_13_; + decode_to_execute_ENV_CTRL <= _zz_2_; end if((! execute_arbitration_isStuck))begin - decode_to_execute_BRANCH_CTRL <= _zz_10_; + decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED; end if((! execute_arbitration_isStuck))begin - decode_to_execute_FORMAL_PC_NEXT <= _zz_61_; - end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SHIFT_CTRL <= _zz_8_; - end - if((! execute_arbitration_isStuck))begin - decode_to_execute_ALU_BITWISE_CTRL <= _zz_5_; - end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC1_CTRL <= _zz_2_; + decode_to_execute_CSR_WRITE_OPCODE <= decode_CSR_WRITE_OPCODE; end case(execute_CsrPlugin_csrAddress) 12'b101111000000 : begin @@ -3364,6 +3256,9 @@ module VexRiscv ( end end 12'b001101000100 : begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mip_MSIP <= _zz_199_[0]; + end end 12'b001101000011 : begin end @@ -3382,7 +3277,7 @@ module VexRiscv ( end endcase iBusWishbone_DAT_MISO_regNext <= iBusWishbone_DAT_MISO; - if(_zz_185_)begin + if(_zz_162_)begin dBus_cmd_halfPipe_regs_payload_wr <= dBus_cmd_payload_wr; dBus_cmd_halfPipe_regs_payload_address <= dBus_cmd_payload_address; dBus_cmd_halfPipe_regs_payload_data <= dBus_cmd_payload_data; diff --git a/hw/rtl/2-stage-1024-cache.yaml b/hw/rtl/2-stage-1024-cache.yaml new file mode 100644 index 0000000..b55f8e5 --- /dev/null +++ b/hw/rtl/2-stage-1024-cache.yaml @@ -0,0 +1,4 @@ +iBus: !!vexriscv.BusReport + flushInstructions: [4111, 19, 19, 19] + info: !!vexriscv.CacheReport {bytePerLine: 32, size: 2048} + kind: cached diff --git a/hw/rtl/2-stage-2048-cache-debug.v b/hw/rtl/2-stage-2048-cache-debug.v new file mode 100644 index 0000000..d043628 --- /dev/null +++ b/hw/rtl/2-stage-2048-cache-debug.v @@ -0,0 +1,3606 @@ +// Generator : SpinalHDL v1.3.3 git head : 8b8cd335eecbea3b5f1f970f218a982dbdb12d99 +// Date : 25/04/2019, 14:40:22 +// Component : VexRiscv + + +`define AluCtrlEnum_defaultEncoding_type [1:0] +`define AluCtrlEnum_defaultEncoding_ADD_SUB 2'b00 +`define AluCtrlEnum_defaultEncoding_SLT_SLTU 2'b01 +`define AluCtrlEnum_defaultEncoding_BITWISE 2'b10 + +`define Src2CtrlEnum_defaultEncoding_type [1:0] +`define Src2CtrlEnum_defaultEncoding_RS 2'b00 +`define Src2CtrlEnum_defaultEncoding_IMI 2'b01 +`define Src2CtrlEnum_defaultEncoding_IMS 2'b10 +`define Src2CtrlEnum_defaultEncoding_PC 2'b11 + +`define Src1CtrlEnum_defaultEncoding_type [1:0] +`define Src1CtrlEnum_defaultEncoding_RS 2'b00 +`define Src1CtrlEnum_defaultEncoding_IMU 2'b01 +`define Src1CtrlEnum_defaultEncoding_PC_INCREMENT 2'b10 +`define Src1CtrlEnum_defaultEncoding_URS1 2'b11 + +`define BranchCtrlEnum_defaultEncoding_type [1:0] +`define BranchCtrlEnum_defaultEncoding_INC 2'b00 +`define BranchCtrlEnum_defaultEncoding_B 2'b01 +`define BranchCtrlEnum_defaultEncoding_JAL 2'b10 +`define BranchCtrlEnum_defaultEncoding_JALR 2'b11 + +`define ShiftCtrlEnum_defaultEncoding_type [1:0] +`define ShiftCtrlEnum_defaultEncoding_DISABLE_1 2'b00 +`define ShiftCtrlEnum_defaultEncoding_SLL_1 2'b01 +`define ShiftCtrlEnum_defaultEncoding_SRL_1 2'b10 +`define ShiftCtrlEnum_defaultEncoding_SRA_1 2'b11 + +`define EnvCtrlEnum_defaultEncoding_type [1:0] +`define EnvCtrlEnum_defaultEncoding_NONE 2'b00 +`define EnvCtrlEnum_defaultEncoding_XRET 2'b01 +`define EnvCtrlEnum_defaultEncoding_ECALL 2'b10 +`define EnvCtrlEnum_defaultEncoding_EBREAK 2'b11 + +`define AluBitwiseCtrlEnum_defaultEncoding_type [1:0] +`define AluBitwiseCtrlEnum_defaultEncoding_XOR_1 2'b00 +`define AluBitwiseCtrlEnum_defaultEncoding_OR_1 2'b01 +`define AluBitwiseCtrlEnum_defaultEncoding_AND_1 2'b10 + +module InstructionCache ( + input io_flush, + input io_cpu_prefetch_isValid, + output reg io_cpu_prefetch_haltIt, + input [31:0] io_cpu_prefetch_pc, + input io_cpu_fetch_isValid, + input io_cpu_fetch_isStuck, + input io_cpu_fetch_isRemoved, + input [31:0] io_cpu_fetch_pc, + output [31:0] io_cpu_fetch_data, + input io_cpu_fetch_dataBypassValid, + input [31:0] io_cpu_fetch_dataBypass, + output io_cpu_fetch_mmuBus_cmd_isValid, + output [31:0] io_cpu_fetch_mmuBus_cmd_virtualAddress, + output io_cpu_fetch_mmuBus_cmd_bypassTranslation, + input [31:0] io_cpu_fetch_mmuBus_rsp_physicalAddress, + input io_cpu_fetch_mmuBus_rsp_isIoAccess, + input io_cpu_fetch_mmuBus_rsp_allowRead, + input io_cpu_fetch_mmuBus_rsp_allowWrite, + input io_cpu_fetch_mmuBus_rsp_allowExecute, + input io_cpu_fetch_mmuBus_rsp_exception, + input io_cpu_fetch_mmuBus_rsp_refilling, + output io_cpu_fetch_mmuBus_end, + input io_cpu_fetch_mmuBus_busy, + output [31:0] io_cpu_fetch_physicalAddress, + output io_cpu_fetch_cacheMiss, + output io_cpu_fetch_error, + output io_cpu_fetch_mmuRefilling, + output io_cpu_fetch_mmuException, + input io_cpu_fetch_isUser, + output io_cpu_fetch_haltIt, + input io_cpu_decode_isValid, + input io_cpu_decode_isStuck, + input [31:0] io_cpu_decode_pc, + output [31:0] io_cpu_decode_physicalAddress, + output [31:0] io_cpu_decode_data, + input io_cpu_fill_valid, + input [31:0] io_cpu_fill_payload, + output io_mem_cmd_valid, + input io_mem_cmd_ready, + output [31:0] io_mem_cmd_payload_address, + output [2:0] io_mem_cmd_payload_size, + input io_mem_rsp_valid, + input [31:0] io_mem_rsp_payload_data, + input io_mem_rsp_payload_error, + input clk, + input reset); + reg [22:0] _zz_10_; + reg [31:0] _zz_11_; + wire _zz_12_; + wire _zz_13_; + wire [0:0] _zz_14_; + wire [0:0] _zz_15_; + wire [22:0] _zz_16_; + reg _zz_1_; + reg _zz_2_; + reg lineLoader_fire; + reg lineLoader_valid; + reg [31:0] lineLoader_address; + reg lineLoader_hadError; + reg lineLoader_flushPending; + reg [6:0] lineLoader_flushCounter; + reg _zz_3_; + reg lineLoader_cmdSent; + reg lineLoader_wayToAllocate_willIncrement; + wire lineLoader_wayToAllocate_willClear; + wire lineLoader_wayToAllocate_willOverflowIfInc; + wire lineLoader_wayToAllocate_willOverflow; + reg [2:0] lineLoader_wordIndex; + wire lineLoader_write_tag_0_valid; + wire [5:0] lineLoader_write_tag_0_payload_address; + wire lineLoader_write_tag_0_payload_data_valid; + wire lineLoader_write_tag_0_payload_data_error; + wire [20:0] lineLoader_write_tag_0_payload_data_address; + wire lineLoader_write_data_0_valid; + wire [8:0] lineLoader_write_data_0_payload_address; + wire [31:0] lineLoader_write_data_0_payload_data; + wire _zz_4_; + wire [5:0] _zz_5_; + wire _zz_6_; + wire fetchStage_read_waysValues_0_tag_valid; + wire fetchStage_read_waysValues_0_tag_error; + wire [20:0] fetchStage_read_waysValues_0_tag_address; + wire [22:0] _zz_7_; + wire [8:0] _zz_8_; + wire _zz_9_; + wire [31:0] fetchStage_read_waysValues_0_data; + wire fetchStage_hit_hits_0; + wire fetchStage_hit_valid; + wire fetchStage_hit_error; + wire [31:0] fetchStage_hit_data; + wire [31:0] fetchStage_hit_word; + reg [22:0] ways_0_tags [0:63]; + reg [31:0] ways_0_datas [0:511]; + assign _zz_12_ = (! lineLoader_flushCounter[6]); + assign _zz_13_ = (lineLoader_flushPending && (! (lineLoader_valid || io_cpu_fetch_isValid))); + assign _zz_14_ = _zz_7_[0 : 0]; + assign _zz_15_ = _zz_7_[1 : 1]; + assign _zz_16_ = {lineLoader_write_tag_0_payload_data_address,{lineLoader_write_tag_0_payload_data_error,lineLoader_write_tag_0_payload_data_valid}}; + always @ (posedge clk) begin + if(_zz_2_) begin + ways_0_tags[lineLoader_write_tag_0_payload_address] <= _zz_16_; + end + end + + always @ (posedge clk) begin + if(_zz_6_) begin + _zz_10_ <= ways_0_tags[_zz_5_]; + end + end + + always @ (posedge clk) begin + if(_zz_1_) begin + ways_0_datas[lineLoader_write_data_0_payload_address] <= lineLoader_write_data_0_payload_data; + end + end + + always @ (posedge clk) begin + if(_zz_9_) begin + _zz_11_ <= ways_0_datas[_zz_8_]; + end + end + + always @ (*) begin + _zz_1_ = 1'b0; + if(lineLoader_write_data_0_valid)begin + _zz_1_ = 1'b1; + end + end + + always @ (*) begin + _zz_2_ = 1'b0; + if(lineLoader_write_tag_0_valid)begin + _zz_2_ = 1'b1; + end + end + + assign io_cpu_fetch_haltIt = io_cpu_fetch_mmuBus_busy; + always @ (*) begin + lineLoader_fire = 1'b0; + if(io_mem_rsp_valid)begin + if((lineLoader_wordIndex == (3'b111)))begin + lineLoader_fire = 1'b1; + end + end + end + + always @ (*) begin + io_cpu_prefetch_haltIt = (lineLoader_valid || lineLoader_flushPending); + if(_zz_12_)begin + io_cpu_prefetch_haltIt = 1'b1; + end + if((! _zz_3_))begin + io_cpu_prefetch_haltIt = 1'b1; + end + if(io_flush)begin + io_cpu_prefetch_haltIt = 1'b1; + end + end + + assign io_mem_cmd_valid = (lineLoader_valid && (! lineLoader_cmdSent)); + assign io_mem_cmd_payload_address = {lineLoader_address[31 : 5],(5'b00000)}; + assign io_mem_cmd_payload_size = (3'b101); + always @ (*) begin + lineLoader_wayToAllocate_willIncrement = 1'b0; + if(lineLoader_fire)begin + lineLoader_wayToAllocate_willIncrement = 1'b1; + end + end + + assign lineLoader_wayToAllocate_willClear = 1'b0; + assign lineLoader_wayToAllocate_willOverflowIfInc = 1'b1; + assign lineLoader_wayToAllocate_willOverflow = (lineLoader_wayToAllocate_willOverflowIfInc && lineLoader_wayToAllocate_willIncrement); + assign _zz_4_ = 1'b1; + assign lineLoader_write_tag_0_valid = ((_zz_4_ && lineLoader_fire) || (! lineLoader_flushCounter[6])); + assign lineLoader_write_tag_0_payload_address = (lineLoader_flushCounter[6] ? lineLoader_address[10 : 5] : lineLoader_flushCounter[5 : 0]); + assign lineLoader_write_tag_0_payload_data_valid = lineLoader_flushCounter[6]; + assign lineLoader_write_tag_0_payload_data_error = (lineLoader_hadError || io_mem_rsp_payload_error); + assign lineLoader_write_tag_0_payload_data_address = lineLoader_address[31 : 11]; + assign lineLoader_write_data_0_valid = (io_mem_rsp_valid && _zz_4_); + assign lineLoader_write_data_0_payload_address = {lineLoader_address[10 : 5],lineLoader_wordIndex}; + assign lineLoader_write_data_0_payload_data = io_mem_rsp_payload_data; + assign _zz_5_ = io_cpu_prefetch_pc[10 : 5]; + assign _zz_6_ = (! io_cpu_fetch_isStuck); + assign _zz_7_ = _zz_10_; + assign fetchStage_read_waysValues_0_tag_valid = _zz_14_[0]; + assign fetchStage_read_waysValues_0_tag_error = _zz_15_[0]; + assign fetchStage_read_waysValues_0_tag_address = _zz_7_[22 : 2]; + assign _zz_8_ = io_cpu_prefetch_pc[10 : 2]; + assign _zz_9_ = (! io_cpu_fetch_isStuck); + assign fetchStage_read_waysValues_0_data = _zz_11_; + assign fetchStage_hit_hits_0 = (fetchStage_read_waysValues_0_tag_valid && (fetchStage_read_waysValues_0_tag_address == io_cpu_fetch_mmuBus_rsp_physicalAddress[31 : 11])); + assign fetchStage_hit_valid = (fetchStage_hit_hits_0 != (1'b0)); + assign fetchStage_hit_error = fetchStage_read_waysValues_0_tag_error; + assign fetchStage_hit_data = fetchStage_read_waysValues_0_data; + assign fetchStage_hit_word = fetchStage_hit_data[31 : 0]; + assign io_cpu_fetch_data = (io_cpu_fetch_dataBypassValid ? io_cpu_fetch_dataBypass : fetchStage_hit_word); + assign io_cpu_fetch_mmuBus_cmd_isValid = io_cpu_fetch_isValid; + assign io_cpu_fetch_mmuBus_cmd_virtualAddress = io_cpu_fetch_pc; + assign io_cpu_fetch_mmuBus_cmd_bypassTranslation = 1'b0; + assign io_cpu_fetch_mmuBus_end = ((! io_cpu_fetch_isStuck) || io_cpu_fetch_isRemoved); + assign io_cpu_fetch_physicalAddress = io_cpu_fetch_mmuBus_rsp_physicalAddress; + assign io_cpu_fetch_cacheMiss = (! fetchStage_hit_valid); + assign io_cpu_fetch_error = fetchStage_hit_error; + assign io_cpu_fetch_mmuRefilling = io_cpu_fetch_mmuBus_rsp_refilling; + assign io_cpu_fetch_mmuException = ((! io_cpu_fetch_mmuBus_rsp_refilling) && (io_cpu_fetch_mmuBus_rsp_exception || (! io_cpu_fetch_mmuBus_rsp_allowExecute))); + always @ (posedge clk) begin + if(reset) begin + lineLoader_valid <= 1'b0; + lineLoader_hadError <= 1'b0; + lineLoader_flushPending <= 1'b1; + lineLoader_cmdSent <= 1'b0; + lineLoader_wordIndex <= (3'b000); + end else begin + if(lineLoader_fire)begin + lineLoader_valid <= 1'b0; + end + if(lineLoader_fire)begin + lineLoader_hadError <= 1'b0; + end + if(io_cpu_fill_valid)begin + lineLoader_valid <= 1'b1; + end + if(io_flush)begin + lineLoader_flushPending <= 1'b1; + end + if(_zz_13_)begin + lineLoader_flushPending <= 1'b0; + end + if((io_mem_cmd_valid && io_mem_cmd_ready))begin + lineLoader_cmdSent <= 1'b1; + end + if(lineLoader_fire)begin + lineLoader_cmdSent <= 1'b0; + end + if(io_mem_rsp_valid)begin + lineLoader_wordIndex <= (lineLoader_wordIndex + (3'b001)); + if(io_mem_rsp_payload_error)begin + lineLoader_hadError <= 1'b1; + end + end + end + end + + always @ (posedge clk) begin + if(io_cpu_fill_valid)begin + lineLoader_address <= io_cpu_fill_payload; + end + if(_zz_12_)begin + lineLoader_flushCounter <= (lineLoader_flushCounter + (7'b0000001)); + end + _zz_3_ <= lineLoader_flushCounter[6]; + if(_zz_13_)begin + lineLoader_flushCounter <= (7'b0000000); + end + end + +endmodule + +module VexRiscv ( + input [31:0] externalResetVector, + input timerInterrupt, + input softwareInterrupt, + input [31:0] externalInterruptArray, + input debug_bus_cmd_valid, + output reg debug_bus_cmd_ready, + input debug_bus_cmd_payload_wr, + input [7:0] debug_bus_cmd_payload_address, + input [31:0] debug_bus_cmd_payload_data, + output reg [31:0] debug_bus_rsp_data, + output debug_resetOut, + output reg iBusWishbone_CYC, + output reg iBusWishbone_STB, + input iBusWishbone_ACK, + output iBusWishbone_WE, + output [29:0] iBusWishbone_ADR, + input [31:0] iBusWishbone_DAT_MISO, + output [31:0] iBusWishbone_DAT_MOSI, + output [3:0] iBusWishbone_SEL, + input iBusWishbone_ERR, + output [1:0] iBusWishbone_BTE, + output [2:0] iBusWishbone_CTI, + output dBusWishbone_CYC, + output dBusWishbone_STB, + input dBusWishbone_ACK, + output dBusWishbone_WE, + output [29:0] dBusWishbone_ADR, + input [31:0] dBusWishbone_DAT_MISO, + output [31:0] dBusWishbone_DAT_MOSI, + output reg [3:0] dBusWishbone_SEL, + input dBusWishbone_ERR, + output [1:0] dBusWishbone_BTE, + output [2:0] dBusWishbone_CTI, + input clk, + input reset, + input debugReset); + wire _zz_135_; + wire _zz_136_; + wire _zz_137_; + wire _zz_138_; + wire _zz_139_; + wire [31:0] _zz_140_; + wire _zz_141_; + wire _zz_142_; + wire _zz_143_; + wire _zz_144_; + wire _zz_145_; + wire _zz_146_; + wire _zz_147_; + wire _zz_148_; + wire _zz_149_; + wire _zz_150_; + wire [31:0] _zz_151_; + reg _zz_152_; + reg [31:0] _zz_153_; + reg [31:0] _zz_154_; + reg [31:0] _zz_155_; + reg [3:0] _zz_156_; + reg [31:0] _zz_157_; + wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt; + wire IBusCachedPlugin_cache_io_cpu_fetch_error; + wire IBusCachedPlugin_cache_io_cpu_fetch_mmuRefilling; + wire IBusCachedPlugin_cache_io_cpu_fetch_mmuException; + wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_data; + wire IBusCachedPlugin_cache_io_cpu_fetch_cacheMiss; + wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress; + wire IBusCachedPlugin_cache_io_cpu_fetch_haltIt; + wire IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_isValid; + wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_virtualAddress; + wire IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_bypassTranslation; + wire IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_end; + wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_data; + wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_physicalAddress; + wire IBusCachedPlugin_cache_io_mem_cmd_valid; + wire [31:0] IBusCachedPlugin_cache_io_mem_cmd_payload_address; + wire [2:0] IBusCachedPlugin_cache_io_mem_cmd_payload_size; + wire _zz_158_; + wire _zz_159_; + wire _zz_160_; + wire _zz_161_; + wire _zz_162_; + wire _zz_163_; + wire [1:0] _zz_164_; + wire _zz_165_; + wire _zz_166_; + wire _zz_167_; + wire _zz_168_; + wire [5:0] _zz_169_; + wire _zz_170_; + wire _zz_171_; + wire [1:0] _zz_172_; + wire _zz_173_; + wire [2:0] _zz_174_; + wire [2:0] _zz_175_; + wire [31:0] _zz_176_; + wire [2:0] _zz_177_; + wire [0:0] _zz_178_; + wire [0:0] _zz_179_; + wire [0:0] _zz_180_; + wire [0:0] _zz_181_; + wire [0:0] _zz_182_; + wire [0:0] _zz_183_; + wire [0:0] _zz_184_; + wire [0:0] _zz_185_; + wire [0:0] _zz_186_; + wire [0:0] _zz_187_; + wire [2:0] _zz_188_; + wire [4:0] _zz_189_; + wire [11:0] _zz_190_; + wire [11:0] _zz_191_; + wire [31:0] _zz_192_; + wire [31:0] _zz_193_; + wire [31:0] _zz_194_; + wire [31:0] _zz_195_; + wire [31:0] _zz_196_; + wire [31:0] _zz_197_; + wire [31:0] _zz_198_; + wire [31:0] _zz_199_; + wire [32:0] _zz_200_; + wire [19:0] _zz_201_; + wire [11:0] _zz_202_; + wire [11:0] _zz_203_; + wire [1:0] _zz_204_; + wire [1:0] _zz_205_; + wire [2:0] _zz_206_; + wire [0:0] _zz_207_; + wire [0:0] _zz_208_; + wire [0:0] _zz_209_; + wire [0:0] _zz_210_; + wire [30:0] _zz_211_; + wire [30:0] _zz_212_; + wire [30:0] _zz_213_; + wire [30:0] _zz_214_; + wire [0:0] _zz_215_; + wire [0:0] _zz_216_; + wire [0:0] _zz_217_; + wire [0:0] _zz_218_; + wire [0:0] _zz_219_; + wire [0:0] _zz_220_; + wire [26:0] _zz_221_; + wire [6:0] _zz_222_; + wire [1:0] _zz_223_; + wire [31:0] _zz_224_; + wire [31:0] _zz_225_; + wire [31:0] _zz_226_; + wire [31:0] _zz_227_; + wire _zz_228_; + wire [5:0] _zz_229_; + wire [5:0] _zz_230_; + wire _zz_231_; + wire [0:0] _zz_232_; + wire [21:0] _zz_233_; + wire [31:0] _zz_234_; + wire [31:0] _zz_235_; + wire _zz_236_; + wire [0:0] _zz_237_; + wire [1:0] _zz_238_; + wire [31:0] _zz_239_; + wire [31:0] _zz_240_; + wire [0:0] _zz_241_; + wire [0:0] _zz_242_; + wire [0:0] _zz_243_; + wire [0:0] _zz_244_; + wire _zz_245_; + wire [0:0] _zz_246_; + wire [17:0] _zz_247_; + wire [31:0] _zz_248_; + wire [31:0] _zz_249_; + wire [31:0] _zz_250_; + wire [31:0] _zz_251_; + wire [31:0] _zz_252_; + wire [31:0] _zz_253_; + wire [31:0] _zz_254_; + wire _zz_255_; + wire _zz_256_; + wire [0:0] _zz_257_; + wire [0:0] _zz_258_; + wire [0:0] _zz_259_; + wire [0:0] _zz_260_; + wire _zz_261_; + wire [0:0] _zz_262_; + wire [14:0] _zz_263_; + wire [31:0] _zz_264_; + wire [31:0] _zz_265_; + wire [31:0] _zz_266_; + wire [31:0] _zz_267_; + wire [31:0] _zz_268_; + wire [0:0] _zz_269_; + wire [0:0] _zz_270_; + wire [1:0] _zz_271_; + wire [1:0] _zz_272_; + wire _zz_273_; + wire [0:0] _zz_274_; + wire [11:0] _zz_275_; + wire [31:0] _zz_276_; + wire [31:0] _zz_277_; + wire [31:0] _zz_278_; + wire [31:0] _zz_279_; + wire [31:0] _zz_280_; + wire [0:0] _zz_281_; + wire [0:0] _zz_282_; + wire [0:0] _zz_283_; + wire [0:0] _zz_284_; + wire _zz_285_; + wire [0:0] _zz_286_; + wire [8:0] _zz_287_; + wire [31:0] _zz_288_; + wire [31:0] _zz_289_; + wire [31:0] _zz_290_; + wire _zz_291_; + wire _zz_292_; + wire [1:0] _zz_293_; + wire [1:0] _zz_294_; + wire _zz_295_; + wire [0:0] _zz_296_; + wire [5:0] _zz_297_; + wire [31:0] _zz_298_; + wire [31:0] _zz_299_; + wire [31:0] _zz_300_; + wire [31:0] _zz_301_; + wire [31:0] _zz_302_; + wire [31:0] _zz_303_; + wire _zz_304_; + wire [1:0] _zz_305_; + wire [1:0] _zz_306_; + wire _zz_307_; + wire [0:0] _zz_308_; + wire [2:0] _zz_309_; + wire [31:0] _zz_310_; + wire [31:0] _zz_311_; + wire _zz_312_; + wire [0:0] _zz_313_; + wire [1:0] _zz_314_; + wire [3:0] _zz_315_; + wire [3:0] _zz_316_; + wire _zz_317_; + wire _zz_318_; + wire [31:0] _zz_319_; + wire [31:0] _zz_320_; + wire [31:0] _zz_321_; + wire [31:0] _zz_322_; + wire [31:0] _zz_323_; + wire [31:0] _zz_324_; + wire [31:0] _zz_325_; + wire _zz_326_; + wire [0:0] _zz_327_; + wire [0:0] _zz_328_; + wire _zz_329_; + wire [31:0] _zz_330_; + wire [31:0] _zz_331_; + wire [31:0] _zz_332_; + wire [31:0] _zz_333_; + wire [31:0] _zz_334_; + wire _zz_335_; + wire [0:0] _zz_336_; + wire [12:0] _zz_337_; + wire [31:0] _zz_338_; + wire [31:0] _zz_339_; + wire [31:0] _zz_340_; + wire _zz_341_; + wire [0:0] _zz_342_; + wire [6:0] _zz_343_; + wire [31:0] _zz_344_; + wire [31:0] _zz_345_; + wire [31:0] _zz_346_; + wire _zz_347_; + wire [0:0] _zz_348_; + wire [0:0] _zz_349_; + wire `AluCtrlEnum_defaultEncoding_type decode_ALU_CTRL; + wire `AluCtrlEnum_defaultEncoding_type _zz_1_; + wire `AluCtrlEnum_defaultEncoding_type _zz_2_; + wire `AluCtrlEnum_defaultEncoding_type _zz_3_; + wire decode_DO_EBREAK; + wire execute_REGFILE_WRITE_VALID; + wire `Src2CtrlEnum_defaultEncoding_type decode_SRC2_CTRL; + wire `Src2CtrlEnum_defaultEncoding_type _zz_4_; + wire `Src2CtrlEnum_defaultEncoding_type _zz_5_; + wire `Src2CtrlEnum_defaultEncoding_type _zz_6_; + wire `Src1CtrlEnum_defaultEncoding_type decode_SRC1_CTRL; + wire `Src1CtrlEnum_defaultEncoding_type _zz_7_; + wire `Src1CtrlEnum_defaultEncoding_type _zz_8_; + wire `Src1CtrlEnum_defaultEncoding_type _zz_9_; + wire decode_SRC_LESS_UNSIGNED; + wire decode_CSR_WRITE_OPCODE; + wire decode_SRC2_FORCE_ZERO; + wire decode_IS_CSR; + wire `BranchCtrlEnum_defaultEncoding_type decode_BRANCH_CTRL; + wire `BranchCtrlEnum_defaultEncoding_type _zz_10_; + wire `BranchCtrlEnum_defaultEncoding_type _zz_11_; + wire `BranchCtrlEnum_defaultEncoding_type _zz_12_; + wire decode_MEMORY_STORE; + wire `ShiftCtrlEnum_defaultEncoding_type decode_SHIFT_CTRL; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_13_; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_14_; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_15_; + wire `EnvCtrlEnum_defaultEncoding_type decode_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_16_; + wire `EnvCtrlEnum_defaultEncoding_type _zz_17_; + wire `EnvCtrlEnum_defaultEncoding_type _zz_18_; + wire decode_MEMORY_ENABLE; + wire decode_CSR_READ_OPCODE; + wire `AluBitwiseCtrlEnum_defaultEncoding_type decode_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_19_; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_20_; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_21_; + wire [31:0] execute_FORMAL_PC_NEXT; + wire [31:0] decode_FORMAL_PC_NEXT; + wire execute_DO_EBREAK; + wire decode_IS_EBREAK; + wire _zz_22_; + wire execute_CSR_READ_OPCODE; + wire execute_CSR_WRITE_OPCODE; + wire execute_IS_CSR; + wire _zz_23_; + wire _zz_24_; + wire `EnvCtrlEnum_defaultEncoding_type execute_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_25_; + wire [31:0] execute_BRANCH_CALC; + wire execute_BRANCH_DO; + wire [31:0] _zz_26_; + wire [31:0] execute_PC; + wire [31:0] execute_RS1; + wire `BranchCtrlEnum_defaultEncoding_type execute_BRANCH_CTRL; + wire `BranchCtrlEnum_defaultEncoding_type _zz_27_; + wire _zz_28_; + wire `ShiftCtrlEnum_defaultEncoding_type execute_SHIFT_CTRL; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_29_; + wire _zz_30_; + wire [31:0] _zz_31_; + wire [31:0] _zz_32_; + wire execute_SRC_LESS_UNSIGNED; + wire execute_SRC2_FORCE_ZERO; + wire execute_SRC_USE_SUB_LESS; + wire `Src2CtrlEnum_defaultEncoding_type execute_SRC2_CTRL; + wire `Src2CtrlEnum_defaultEncoding_type _zz_33_; + wire [31:0] _zz_34_; + wire `Src1CtrlEnum_defaultEncoding_type execute_SRC1_CTRL; + wire `Src1CtrlEnum_defaultEncoding_type _zz_35_; + wire [31:0] _zz_36_; + wire decode_SRC_USE_SUB_LESS; + wire decode_SRC_ADD_ZERO; + wire _zz_37_; + wire [31:0] execute_SRC_ADD_SUB; + wire execute_SRC_LESS; + wire `AluCtrlEnum_defaultEncoding_type execute_ALU_CTRL; + wire `AluCtrlEnum_defaultEncoding_type _zz_38_; + wire [31:0] _zz_39_; + wire [31:0] execute_SRC2; + wire [31:0] execute_SRC1; + wire `AluBitwiseCtrlEnum_defaultEncoding_type execute_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_40_; + reg _zz_41_; + wire [31:0] _zz_42_; + wire [31:0] _zz_43_; + reg decode_REGFILE_WRITE_VALID; + wire decode_LEGAL_INSTRUCTION; + wire decode_INSTRUCTION_READY; + wire _zz_44_; + wire _zz_45_; + wire _zz_46_; + wire _zz_47_; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_48_; + wire _zz_49_; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_50_; + wire `Src1CtrlEnum_defaultEncoding_type _zz_51_; + wire _zz_52_; + wire _zz_53_; + wire `EnvCtrlEnum_defaultEncoding_type _zz_54_; + wire _zz_55_; + wire `AluCtrlEnum_defaultEncoding_type _zz_56_; + wire `Src2CtrlEnum_defaultEncoding_type _zz_57_; + wire _zz_58_; + wire `BranchCtrlEnum_defaultEncoding_type _zz_59_; + wire _zz_60_; + reg [31:0] _zz_61_; + wire [1:0] execute_MEMORY_ADDRESS_LOW; + wire [31:0] execute_MEMORY_READ_DATA; + wire [31:0] execute_REGFILE_WRITE_DATA; + wire [31:0] _zz_62_; + wire [31:0] execute_SRC_ADD; + wire [1:0] _zz_63_; + wire [31:0] execute_RS2; + wire [31:0] execute_INSTRUCTION; + wire execute_MEMORY_STORE; + wire execute_MEMORY_ENABLE; + wire execute_ALIGNEMENT_FAULT; + wire _zz_64_; + wire decode_FLUSH_ALL; + reg IBusCachedPlugin_rsp_issueDetected; + reg _zz_65_; + reg _zz_66_; + reg _zz_67_; + reg [31:0] _zz_68_; + wire [31:0] _zz_69_; + wire [31:0] _zz_70_; + wire [31:0] _zz_71_; + wire [31:0] decode_PC /* verilator public */ ; + reg [31:0] decode_INSTRUCTION /* verilator public */ ; + reg decode_arbitration_haltItself /* verilator public */ ; + reg decode_arbitration_haltByOther; + reg decode_arbitration_removeIt; + reg decode_arbitration_flushAll /* verilator public */ ; + reg decode_arbitration_isValid /* verilator public */ ; + wire decode_arbitration_isStuck; + wire decode_arbitration_isStuckByOthers; + wire decode_arbitration_isFlushed; + wire decode_arbitration_isMoving; + wire decode_arbitration_isFiring; + reg execute_arbitration_haltItself; + reg execute_arbitration_haltByOther; + reg execute_arbitration_removeIt; + reg execute_arbitration_flushAll; + reg execute_arbitration_isValid; + wire execute_arbitration_isStuck; + wire execute_arbitration_isStuckByOthers; + wire execute_arbitration_isFlushed; + wire execute_arbitration_isMoving; + wire execute_arbitration_isFiring; + reg IBusCachedPlugin_fetcherHalt; + reg IBusCachedPlugin_fetcherflushIt; + reg IBusCachedPlugin_incomingInstruction; + wire IBusCachedPlugin_pcValids_0; + wire IBusCachedPlugin_pcValids_1; + wire IBusCachedPlugin_redoBranch_valid; + wire [31:0] IBusCachedPlugin_redoBranch_payload; + reg IBusCachedPlugin_decodeExceptionPort_valid; + reg [3:0] IBusCachedPlugin_decodeExceptionPort_payload_code; + wire [31:0] IBusCachedPlugin_decodeExceptionPort_payload_badAddr; + reg DBusSimplePlugin_memoryExceptionPort_valid; + reg [3:0] DBusSimplePlugin_memoryExceptionPort_payload_code; + wire [31:0] DBusSimplePlugin_memoryExceptionPort_payload_badAddr; + wire decodeExceptionPort_valid; + wire [3:0] decodeExceptionPort_payload_code; + wire [31:0] decodeExceptionPort_payload_badAddr; + wire BranchPlugin_jumpInterface_valid; + wire [31:0] BranchPlugin_jumpInterface_payload; + reg BranchPlugin_branchExceptionPort_valid; + wire [3:0] BranchPlugin_branchExceptionPort_payload_code; + wire [31:0] BranchPlugin_branchExceptionPort_payload_badAddr; + reg CsrPlugin_jumpInterface_valid; + reg [31:0] CsrPlugin_jumpInterface_payload; + wire CsrPlugin_exceptionPendings_0; + wire CsrPlugin_exceptionPendings_1; + wire externalInterrupt; + wire contextSwitching; + reg [1:0] CsrPlugin_privilege; + reg CsrPlugin_forceMachineWire; + reg CsrPlugin_selfException_valid; + reg [3:0] CsrPlugin_selfException_payload_code; + wire [31:0] CsrPlugin_selfException_payload_badAddr; + reg CsrPlugin_allowInterrupts; + reg CsrPlugin_allowException; + reg IBusCachedPlugin_injectionPort_valid; + reg IBusCachedPlugin_injectionPort_ready; + wire [31:0] IBusCachedPlugin_injectionPort_payload; + wire IBusCachedPlugin_jump_pcLoad_valid; + wire [31:0] IBusCachedPlugin_jump_pcLoad_payload; + wire [2:0] _zz_72_; + wire [2:0] _zz_73_; + wire _zz_74_; + wire _zz_75_; + wire IBusCachedPlugin_fetchPc_preOutput_valid; + wire IBusCachedPlugin_fetchPc_preOutput_ready; + wire [31:0] IBusCachedPlugin_fetchPc_preOutput_payload; + wire _zz_76_; + wire IBusCachedPlugin_fetchPc_output_valid; + wire IBusCachedPlugin_fetchPc_output_ready; + wire [31:0] IBusCachedPlugin_fetchPc_output_payload; + reg [31:0] IBusCachedPlugin_fetchPc_pcReg /* verilator public */ ; + reg IBusCachedPlugin_fetchPc_inc; + reg IBusCachedPlugin_fetchPc_propagatePc; + reg [31:0] IBusCachedPlugin_fetchPc_pc; + reg IBusCachedPlugin_fetchPc_samplePcNext; + reg _zz_77_; + wire IBusCachedPlugin_iBusRsp_stages_0_input_valid; + wire IBusCachedPlugin_iBusRsp_stages_0_input_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_input_payload; + wire IBusCachedPlugin_iBusRsp_stages_0_output_valid; + wire IBusCachedPlugin_iBusRsp_stages_0_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_output_payload; + reg IBusCachedPlugin_iBusRsp_stages_0_halt; + wire IBusCachedPlugin_iBusRsp_stages_0_inputSample; + wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid; + wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload; + wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_valid; + wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_payload; + reg IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt; + wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_inputSample; + wire _zz_78_; + wire _zz_79_; + wire _zz_80_; + wire _zz_81_; + reg _zz_82_; + reg IBusCachedPlugin_iBusRsp_readyForError; + wire IBusCachedPlugin_iBusRsp_decodeInput_valid; + wire IBusCachedPlugin_iBusRsp_decodeInput_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_decodeInput_payload_pc; + wire IBusCachedPlugin_iBusRsp_decodeInput_payload_rsp_error; + wire [31:0] IBusCachedPlugin_iBusRsp_decodeInput_payload_rsp_inst; + wire IBusCachedPlugin_iBusRsp_decodeInput_payload_isRvc; + reg IBusCachedPlugin_injector_nextPcCalc_valids_0; + reg IBusCachedPlugin_injector_nextPcCalc_valids_1; + reg IBusCachedPlugin_injector_decodeRemoved; + wire iBus_cmd_valid; + wire iBus_cmd_ready; + reg [31:0] iBus_cmd_payload_address; + wire [2:0] iBus_cmd_payload_size; + wire iBus_rsp_valid; + wire [31:0] iBus_rsp_payload_data; + wire iBus_rsp_payload_error; + wire IBusCachedPlugin_s0_tightlyCoupledHit; + reg IBusCachedPlugin_s1_tightlyCoupledHit; + wire IBusCachedPlugin_rsp_iBusRspOutputHalt; + reg IBusCachedPlugin_rsp_redoFetch; + wire dBus_cmd_valid; + wire dBus_cmd_ready; + wire dBus_cmd_payload_wr; + wire [31:0] dBus_cmd_payload_address; + wire [31:0] dBus_cmd_payload_data; + wire [1:0] dBus_cmd_payload_size; + wire dBus_rsp_ready; + wire dBus_rsp_error; + wire [31:0] dBus_rsp_data; + reg execute_DBusSimplePlugin_cmdSent; + reg execute_DBusSimplePlugin_skipCmd; + reg [31:0] _zz_83_; + reg [3:0] _zz_84_; + wire [3:0] execute_DBusSimplePlugin_formalMask; + reg [31:0] execute_DBusSimplePlugin_rspShifted; + wire _zz_85_; + reg [31:0] _zz_86_; + wire _zz_87_; + reg [31:0] _zz_88_; + reg [31:0] execute_DBusSimplePlugin_rspFormated; + wire [27:0] _zz_89_; + wire _zz_90_; + wire _zz_91_; + wire _zz_92_; + wire _zz_93_; + wire _zz_94_; + wire `BranchCtrlEnum_defaultEncoding_type _zz_95_; + wire `Src2CtrlEnum_defaultEncoding_type _zz_96_; + wire `AluCtrlEnum_defaultEncoding_type _zz_97_; + wire `EnvCtrlEnum_defaultEncoding_type _zz_98_; + wire `Src1CtrlEnum_defaultEncoding_type _zz_99_; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_100_; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_101_; + wire [4:0] execute_RegFilePlugin_regFileReadAddress1; + wire [4:0] execute_RegFilePlugin_regFileReadAddress2; + wire _zz_102_; + wire [31:0] execute_RegFilePlugin_rs1Data; + wire [31:0] execute_RegFilePlugin_rs2Data; + wire execute_RegFilePlugin_regFileWrite_valid /* verilator public */ ; + wire [4:0] execute_RegFilePlugin_regFileWrite_payload_address /* verilator public */ ; + wire [31:0] execute_RegFilePlugin_regFileWrite_payload_data /* verilator public */ ; + reg [31:0] execute_IntAluPlugin_bitwise; + reg [31:0] _zz_103_; + reg [31:0] _zz_104_; + wire _zz_105_; + reg [19:0] _zz_106_; + wire _zz_107_; + reg [19:0] _zz_108_; + reg [31:0] _zz_109_; + reg [31:0] execute_SrcPlugin_addSub; + wire execute_SrcPlugin_less; + reg execute_LightShifterPlugin_isActive; + wire execute_LightShifterPlugin_isShift; + reg [4:0] execute_LightShifterPlugin_amplitudeReg; + wire [4:0] execute_LightShifterPlugin_amplitude; + reg [31:0] execute_LightShifterPlugin_shiftReg; + wire [31:0] execute_LightShifterPlugin_shiftInput; + wire execute_LightShifterPlugin_done; + reg [31:0] _zz_110_; + wire execute_BranchPlugin_eq; + wire [2:0] _zz_111_; + reg _zz_112_; + reg _zz_113_; + wire [31:0] execute_BranchPlugin_branch_src1; + wire _zz_114_; + reg [10:0] _zz_115_; + wire _zz_116_; + reg [19:0] _zz_117_; + wire _zz_118_; + reg [18:0] _zz_119_; + reg [31:0] _zz_120_; + wire [31:0] execute_BranchPlugin_branch_src2; + wire [31:0] execute_BranchPlugin_branchAdder; + wire [1:0] CsrPlugin_misa_base; + wire [25:0] CsrPlugin_misa_extensions; + reg [1:0] CsrPlugin_mtvec_mode; + reg [29:0] CsrPlugin_mtvec_base; + reg [31:0] CsrPlugin_mepc; + reg CsrPlugin_mstatus_MIE; + reg CsrPlugin_mstatus_MPIE; + reg [1:0] CsrPlugin_mstatus_MPP; + reg CsrPlugin_mip_MEIP; + reg CsrPlugin_mip_MTIP; + reg CsrPlugin_mip_MSIP; + reg CsrPlugin_mie_MEIE; + reg CsrPlugin_mie_MTIE; + reg CsrPlugin_mie_MSIE; + reg [31:0] CsrPlugin_mscratch; + reg CsrPlugin_mcause_interrupt; + reg [3:0] CsrPlugin_mcause_exceptionCode; + reg [31:0] CsrPlugin_mtval; + reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000; + reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; + reg [3:0] CsrPlugin_exceptionPortCtrl_exceptionContext_code; + reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; + wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped; + wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; + wire [1:0] _zz_121_; + wire _zz_122_; + wire [2:0] _zz_123_; + wire [2:0] _zz_124_; + wire _zz_125_; + wire _zz_126_; + wire [1:0] _zz_127_; + reg CsrPlugin_interrupt; + reg [3:0] CsrPlugin_interruptCode /* verilator public */ ; + reg [1:0] CsrPlugin_interruptTargetPrivilege; + wire CsrPlugin_exception; + wire CsrPlugin_lastStageWasWfi; + reg CsrPlugin_pipelineLiberator_done; + wire CsrPlugin_interruptJump /* verilator public */ ; + reg CsrPlugin_hadException; + reg [1:0] CsrPlugin_targetPrivilege; + reg [3:0] CsrPlugin_trapCause; + reg [1:0] CsrPlugin_xtvec_mode; + reg [29:0] CsrPlugin_xtvec_base; + wire execute_CsrPlugin_inWfi /* verilator public */ ; + wire execute_CsrPlugin_blockedBySideEffects; + reg execute_CsrPlugin_illegalAccess; + reg execute_CsrPlugin_illegalInstruction; + reg [31:0] execute_CsrPlugin_readData; + wire execute_CsrPlugin_writeInstruction; + wire execute_CsrPlugin_readInstruction; + wire execute_CsrPlugin_writeEnable; + wire execute_CsrPlugin_readEnable; + wire [31:0] execute_CsrPlugin_readToWriteData; + reg [31:0] execute_CsrPlugin_writeData; + wire [11:0] execute_CsrPlugin_csrAddress; + reg [31:0] _zz_128_; + reg [31:0] externalInterruptArray_regNext; + wire [31:0] _zz_129_; + reg DebugPlugin_firstCycle; + reg DebugPlugin_secondCycle; + reg DebugPlugin_resetIt; + reg DebugPlugin_haltIt; + reg DebugPlugin_stepIt; + reg DebugPlugin_isPipBusy; + reg DebugPlugin_godmode; + reg DebugPlugin_haltedByBreak; + reg DebugPlugin_hardwareBreakpoints_0_valid; + reg [30:0] DebugPlugin_hardwareBreakpoints_0_pc; + reg DebugPlugin_hardwareBreakpoints_1_valid; + reg [30:0] DebugPlugin_hardwareBreakpoints_1_pc; + reg DebugPlugin_hardwareBreakpoints_2_valid; + reg [30:0] DebugPlugin_hardwareBreakpoints_2_pc; + reg DebugPlugin_hardwareBreakpoints_3_valid; + reg [30:0] DebugPlugin_hardwareBreakpoints_3_pc; + reg [31:0] DebugPlugin_busReadDataReg; + reg _zz_130_; + reg DebugPlugin_resetIt_regNext; + reg [31:0] decode_to_execute_INSTRUCTION; + reg [31:0] decode_to_execute_PC; + reg [31:0] decode_to_execute_FORMAL_PC_NEXT; + reg `AluBitwiseCtrlEnum_defaultEncoding_type decode_to_execute_ALU_BITWISE_CTRL; + reg decode_to_execute_CSR_READ_OPCODE; + reg decode_to_execute_MEMORY_ENABLE; + reg `EnvCtrlEnum_defaultEncoding_type decode_to_execute_ENV_CTRL; + reg decode_to_execute_SRC_USE_SUB_LESS; + reg `ShiftCtrlEnum_defaultEncoding_type decode_to_execute_SHIFT_CTRL; + reg decode_to_execute_MEMORY_STORE; + reg `BranchCtrlEnum_defaultEncoding_type decode_to_execute_BRANCH_CTRL; + reg decode_to_execute_IS_CSR; + reg decode_to_execute_SRC2_FORCE_ZERO; + reg decode_to_execute_CSR_WRITE_OPCODE; + reg decode_to_execute_SRC_LESS_UNSIGNED; + reg `Src1CtrlEnum_defaultEncoding_type decode_to_execute_SRC1_CTRL; + reg `Src2CtrlEnum_defaultEncoding_type decode_to_execute_SRC2_CTRL; + reg decode_to_execute_REGFILE_WRITE_VALID; + reg decode_to_execute_DO_EBREAK; + reg `AluCtrlEnum_defaultEncoding_type decode_to_execute_ALU_CTRL; + reg [2:0] _zz_131_; + reg [31:0] IBusCachedPlugin_injectionPort_payload_regNext; + reg [2:0] _zz_132_; + reg _zz_133_; + reg [31:0] iBusWishbone_DAT_MISO_regNext; + wire dBus_cmd_halfPipe_valid; + wire dBus_cmd_halfPipe_ready; + wire dBus_cmd_halfPipe_payload_wr; + wire [31:0] dBus_cmd_halfPipe_payload_address; + wire [31:0] dBus_cmd_halfPipe_payload_data; + wire [1:0] dBus_cmd_halfPipe_payload_size; + reg dBus_cmd_halfPipe_regs_valid; + reg dBus_cmd_halfPipe_regs_ready; + reg dBus_cmd_halfPipe_regs_payload_wr; + reg [31:0] dBus_cmd_halfPipe_regs_payload_address; + reg [31:0] dBus_cmd_halfPipe_regs_payload_data; + reg [1:0] dBus_cmd_halfPipe_regs_payload_size; + reg [3:0] _zz_134_; + `ifndef SYNTHESIS + reg [63:0] decode_ALU_CTRL_string; + reg [63:0] _zz_1__string; + reg [63:0] _zz_2__string; + reg [63:0] _zz_3__string; + reg [23:0] decode_SRC2_CTRL_string; + reg [23:0] _zz_4__string; + reg [23:0] _zz_5__string; + reg [23:0] _zz_6__string; + reg [95:0] decode_SRC1_CTRL_string; + reg [95:0] _zz_7__string; + reg [95:0] _zz_8__string; + reg [95:0] _zz_9__string; + reg [31:0] decode_BRANCH_CTRL_string; + reg [31:0] _zz_10__string; + reg [31:0] _zz_11__string; + reg [31:0] _zz_12__string; + reg [71:0] decode_SHIFT_CTRL_string; + reg [71:0] _zz_13__string; + reg [71:0] _zz_14__string; + reg [71:0] _zz_15__string; + reg [47:0] decode_ENV_CTRL_string; + reg [47:0] _zz_16__string; + reg [47:0] _zz_17__string; + reg [47:0] _zz_18__string; + reg [39:0] decode_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_19__string; + reg [39:0] _zz_20__string; + reg [39:0] _zz_21__string; + reg [47:0] execute_ENV_CTRL_string; + reg [47:0] _zz_25__string; + reg [31:0] execute_BRANCH_CTRL_string; + reg [31:0] _zz_27__string; + reg [71:0] execute_SHIFT_CTRL_string; + reg [71:0] _zz_29__string; + reg [23:0] execute_SRC2_CTRL_string; + reg [23:0] _zz_33__string; + reg [95:0] execute_SRC1_CTRL_string; + reg [95:0] _zz_35__string; + reg [63:0] execute_ALU_CTRL_string; + reg [63:0] _zz_38__string; + reg [39:0] execute_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_40__string; + reg [71:0] _zz_48__string; + reg [39:0] _zz_50__string; + reg [95:0] _zz_51__string; + reg [47:0] _zz_54__string; + reg [63:0] _zz_56__string; + reg [23:0] _zz_57__string; + reg [31:0] _zz_59__string; + reg [31:0] _zz_95__string; + reg [23:0] _zz_96__string; + reg [63:0] _zz_97__string; + reg [47:0] _zz_98__string; + reg [95:0] _zz_99__string; + reg [39:0] _zz_100__string; + reg [71:0] _zz_101__string; + reg [39:0] decode_to_execute_ALU_BITWISE_CTRL_string; + reg [47:0] decode_to_execute_ENV_CTRL_string; + reg [71:0] decode_to_execute_SHIFT_CTRL_string; + reg [31:0] decode_to_execute_BRANCH_CTRL_string; + reg [95:0] decode_to_execute_SRC1_CTRL_string; + reg [23:0] decode_to_execute_SRC2_CTRL_string; + reg [63:0] decode_to_execute_ALU_CTRL_string; + `endif + + reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; + assign _zz_158_ = ((execute_arbitration_isValid && execute_LightShifterPlugin_isShift) && (execute_SRC2[4 : 0] != (5'b00000))); + assign _zz_159_ = (! execute_arbitration_isStuckByOthers); + assign _zz_160_ = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != (2'b00)); + assign _zz_161_ = ({CsrPlugin_selfException_valid,{BranchPlugin_branchExceptionPort_valid,DBusSimplePlugin_memoryExceptionPort_valid}} != (3'b000)); + assign _zz_162_ = (CsrPlugin_hadException || CsrPlugin_interruptJump); + assign _zz_163_ = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); + assign _zz_164_ = execute_INSTRUCTION[29 : 28]; + assign _zz_165_ = (execute_arbitration_isValid && execute_DO_EBREAK); + assign _zz_166_ = (1'b0 == 1'b0); + assign _zz_167_ = (DebugPlugin_stepIt && IBusCachedPlugin_incomingInstruction); + assign _zz_168_ = (IBusCachedPlugin_fetchPc_preOutput_valid && IBusCachedPlugin_fetchPc_preOutput_ready); + assign _zz_169_ = debug_bus_cmd_payload_address[7 : 2]; + assign _zz_170_ = (iBus_cmd_valid || (_zz_132_ != (3'b000))); + assign _zz_171_ = (! dBus_cmd_halfPipe_regs_valid); + assign _zz_172_ = execute_INSTRUCTION[13 : 12]; + assign _zz_173_ = execute_INSTRUCTION[13]; + assign _zz_174_ = (_zz_72_ - (3'b001)); + assign _zz_175_ = {IBusCachedPlugin_fetchPc_inc,(2'b00)}; + assign _zz_176_ = {29'd0, _zz_175_}; + assign _zz_177_ = (execute_MEMORY_STORE ? (3'b110) : (3'b100)); + assign _zz_178_ = _zz_89_[3 : 3]; + assign _zz_179_ = _zz_89_[9 : 9]; + assign _zz_180_ = _zz_89_[12 : 12]; + assign _zz_181_ = _zz_89_[13 : 13]; + assign _zz_182_ = _zz_89_[19 : 19]; + assign _zz_183_ = _zz_89_[23 : 23]; + assign _zz_184_ = _zz_89_[24 : 24]; + assign _zz_185_ = _zz_89_[25 : 25]; + assign _zz_186_ = _zz_89_[27 : 27]; + assign _zz_187_ = execute_SRC_LESS; + assign _zz_188_ = (3'b100); + assign _zz_189_ = execute_INSTRUCTION[19 : 15]; + assign _zz_190_ = execute_INSTRUCTION[31 : 20]; + assign _zz_191_ = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; + assign _zz_192_ = ($signed(_zz_193_) + $signed(_zz_196_)); + assign _zz_193_ = ($signed(_zz_194_) + $signed(_zz_195_)); + assign _zz_194_ = execute_SRC1; + assign _zz_195_ = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); + assign _zz_196_ = (execute_SRC_USE_SUB_LESS ? _zz_197_ : _zz_198_); + assign _zz_197_ = (32'b00000000000000000000000000000001); + assign _zz_198_ = (32'b00000000000000000000000000000000); + assign _zz_199_ = (_zz_200_ >>> 1); + assign _zz_200_ = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_LightShifterPlugin_shiftInput[31]),execute_LightShifterPlugin_shiftInput}; + assign _zz_201_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_202_ = execute_INSTRUCTION[31 : 20]; + assign _zz_203_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_204_ = (_zz_121_ & (~ _zz_205_)); + assign _zz_205_ = (_zz_121_ - (2'b01)); + assign _zz_206_ = (_zz_123_ - (3'b001)); + assign _zz_207_ = debug_bus_cmd_payload_data[0 : 0]; + assign _zz_208_ = debug_bus_cmd_payload_data[0 : 0]; + assign _zz_209_ = debug_bus_cmd_payload_data[0 : 0]; + assign _zz_210_ = debug_bus_cmd_payload_data[0 : 0]; + assign _zz_211_ = (decode_PC >>> 1); + assign _zz_212_ = (decode_PC >>> 1); + assign _zz_213_ = (decode_PC >>> 1); + assign _zz_214_ = (decode_PC >>> 1); + assign _zz_215_ = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_216_ = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_217_ = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_218_ = execute_CsrPlugin_writeData[11 : 11]; + assign _zz_219_ = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_220_ = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_221_ = (iBus_cmd_payload_address >>> 5); + assign _zz_222_ = ({3'd0,_zz_134_} <<< dBus_cmd_halfPipe_payload_address[1 : 0]); + assign _zz_223_ = {_zz_75_,_zz_74_}; + assign _zz_224_ = (decode_INSTRUCTION & (32'b00000000000000000001000001010000)); + assign _zz_225_ = (32'b00000000000000000001000001010000); + assign _zz_226_ = (decode_INSTRUCTION & (32'b00000000000000000010000001010000)); + assign _zz_227_ = (32'b00000000000000000010000001010000); + assign _zz_228_ = ((decode_INSTRUCTION & (32'b00000000000000000001000001001000)) == (32'b00000000000000000001000000001000)); + assign _zz_229_ = {_zz_90_,{(_zz_234_ == _zz_235_),{_zz_236_,{_zz_237_,_zz_238_}}}}; + assign _zz_230_ = (6'b000000); + assign _zz_231_ = (_zz_92_ != (1'b0)); + assign _zz_232_ = ((_zz_239_ == _zz_240_) != (1'b0)); + assign _zz_233_ = {({_zz_241_,_zz_242_} != (2'b00)),{(_zz_243_ != _zz_244_),{_zz_245_,{_zz_246_,_zz_247_}}}}; + assign _zz_234_ = (decode_INSTRUCTION & (32'b00000000000000000001000000010000)); + assign _zz_235_ = (32'b00000000000000000001000000010000); + assign _zz_236_ = ((decode_INSTRUCTION & (32'b00000000000000000010000000010000)) == (32'b00000000000000000010000000010000)); + assign _zz_237_ = _zz_94_; + assign _zz_238_ = {(_zz_248_ == _zz_249_),(_zz_250_ == _zz_251_)}; + assign _zz_239_ = (decode_INSTRUCTION & (32'b00000000000000000111000001010100)); + assign _zz_240_ = (32'b00000000000000000101000000010000); + assign _zz_241_ = ((decode_INSTRUCTION & _zz_252_) == (32'b01000000000000000001000000010000)); + assign _zz_242_ = ((decode_INSTRUCTION & _zz_253_) == (32'b00000000000000000001000000010000)); + assign _zz_243_ = ((decode_INSTRUCTION & _zz_254_) == (32'b00000000000000000000000000010000)); + assign _zz_244_ = (1'b0); + assign _zz_245_ = ({_zz_255_,_zz_256_} != (2'b00)); + assign _zz_246_ = ({_zz_257_,_zz_258_} != (2'b00)); + assign _zz_247_ = {(_zz_259_ != _zz_260_),{_zz_261_,{_zz_262_,_zz_263_}}}; + assign _zz_248_ = (decode_INSTRUCTION & (32'b00000000000000000000000000001100)); + assign _zz_249_ = (32'b00000000000000000000000000000100); + assign _zz_250_ = (decode_INSTRUCTION & (32'b00000000000000000000000000101000)); + assign _zz_251_ = (32'b00000000000000000000000000000000); + assign _zz_252_ = (32'b01000000000000000011000001010100); + assign _zz_253_ = (32'b00000000000000000111000001010100); + assign _zz_254_ = (32'b00000000000000000000000000010000); + assign _zz_255_ = ((decode_INSTRUCTION & (32'b00000000000000000010000000010000)) == (32'b00000000000000000010000000000000)); + assign _zz_256_ = ((decode_INSTRUCTION & (32'b00000000000000000101000000000000)) == (32'b00000000000000000001000000000000)); + assign _zz_257_ = ((decode_INSTRUCTION & _zz_264_) == (32'b00000000000000000000000000100000)); + assign _zz_258_ = ((decode_INSTRUCTION & _zz_265_) == (32'b00000000000000000000000000100000)); + assign _zz_259_ = ((decode_INSTRUCTION & _zz_266_) == (32'b00000000000000000001000000000000)); + assign _zz_260_ = (1'b0); + assign _zz_261_ = ((_zz_267_ == _zz_268_) != (1'b0)); + assign _zz_262_ = ({_zz_269_,_zz_270_} != (2'b00)); + assign _zz_263_ = {(_zz_271_ != _zz_272_),{_zz_273_,{_zz_274_,_zz_275_}}}; + assign _zz_264_ = (32'b00000000000000000000000000110100); + assign _zz_265_ = (32'b00000000000000000000000001100100); + assign _zz_266_ = (32'b00000000000000000001000000000000); + assign _zz_267_ = (decode_INSTRUCTION & (32'b00000000000000000011000000000000)); + assign _zz_268_ = (32'b00000000000000000010000000000000); + assign _zz_269_ = ((decode_INSTRUCTION & _zz_276_) == (32'b00000000000000000000000000000100)); + assign _zz_270_ = _zz_93_; + assign _zz_271_ = {(_zz_277_ == _zz_278_),_zz_93_}; + assign _zz_272_ = (2'b00); + assign _zz_273_ = ((_zz_279_ == _zz_280_) != (1'b0)); + assign _zz_274_ = ({_zz_281_,_zz_282_} != (2'b00)); + assign _zz_275_ = {(_zz_283_ != _zz_284_),{_zz_285_,{_zz_286_,_zz_287_}}}; + assign _zz_276_ = (32'b00000000000000000000000000010100); + assign _zz_277_ = (decode_INSTRUCTION & (32'b00000000000000000000000001000100)); + assign _zz_278_ = (32'b00000000000000000000000000000100); + assign _zz_279_ = (decode_INSTRUCTION & (32'b00000000000000000000000001011000)); + assign _zz_280_ = (32'b00000000000000000000000000000000); + assign _zz_281_ = ((decode_INSTRUCTION & _zz_288_) == (32'b00000000000000000000000000100100)); + assign _zz_282_ = ((decode_INSTRUCTION & _zz_289_) == (32'b00000000000000000001000000010000)); + assign _zz_283_ = ((decode_INSTRUCTION & _zz_290_) == (32'b00000000000000000000000001010000)); + assign _zz_284_ = (1'b0); + assign _zz_285_ = ({_zz_92_,_zz_291_} != (2'b00)); + assign _zz_286_ = (_zz_292_ != (1'b0)); + assign _zz_287_ = {(_zz_293_ != _zz_294_),{_zz_295_,{_zz_296_,_zz_297_}}}; + assign _zz_288_ = (32'b00000000000000000000000001100100); + assign _zz_289_ = (32'b00000000000000000011000001010100); + assign _zz_290_ = (32'b00010000000000000011000001010000); + assign _zz_291_ = ((decode_INSTRUCTION & (32'b00010000010000000011000001010000)) == (32'b00010000000000000000000001010000)); + assign _zz_292_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000100000)) == (32'b00000000000000000000000000100000)); + assign _zz_293_ = {(_zz_298_ == _zz_299_),(_zz_300_ == _zz_301_)}; + assign _zz_294_ = (2'b00); + assign _zz_295_ = ((_zz_302_ == _zz_303_) != (1'b0)); + assign _zz_296_ = (_zz_304_ != (1'b0)); + assign _zz_297_ = {(_zz_305_ != _zz_306_),{_zz_307_,{_zz_308_,_zz_309_}}}; + assign _zz_298_ = (decode_INSTRUCTION & (32'b00000000000000000110000000010100)); + assign _zz_299_ = (32'b00000000000000000110000000010000); + assign _zz_300_ = (decode_INSTRUCTION & (32'b00000000000000000101000000010100)); + assign _zz_301_ = (32'b00000000000000000100000000010000); + assign _zz_302_ = (decode_INSTRUCTION & (32'b00000000000000000110000000010100)); + assign _zz_303_ = (32'b00000000000000000010000000010000); + assign _zz_304_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000000000)) == (32'b00000000000000000000000000000000)); + assign _zz_305_ = {_zz_91_,(_zz_310_ == _zz_311_)}; + assign _zz_306_ = (2'b00); + assign _zz_307_ = ({_zz_91_,_zz_312_} != (2'b00)); + assign _zz_308_ = ({_zz_313_,_zz_314_} != (3'b000)); + assign _zz_309_ = {(_zz_315_ != _zz_316_),{_zz_317_,_zz_318_}}; + assign _zz_310_ = (decode_INSTRUCTION & (32'b00000000000000000000000001110000)); + assign _zz_311_ = (32'b00000000000000000000000000100000); + assign _zz_312_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000100000)) == (32'b00000000000000000000000000000000)); + assign _zz_313_ = ((decode_INSTRUCTION & _zz_319_) == (32'b00000000000000000000000001000000)); + assign _zz_314_ = {(_zz_320_ == _zz_321_),(_zz_322_ == _zz_323_)}; + assign _zz_315_ = {(_zz_324_ == _zz_325_),{_zz_326_,{_zz_327_,_zz_328_}}}; + assign _zz_316_ = (4'b0000); + assign _zz_317_ = ({_zz_90_,_zz_329_} != (2'b00)); + assign _zz_318_ = ((_zz_330_ == _zz_331_) != (1'b0)); + assign _zz_319_ = (32'b00000000000000000000000001000100); + assign _zz_320_ = (decode_INSTRUCTION & (32'b00000000000000000010000000010100)); + assign _zz_321_ = (32'b00000000000000000010000000010000); + assign _zz_322_ = (decode_INSTRUCTION & (32'b01000000000000000100000000110100)); + assign _zz_323_ = (32'b01000000000000000000000000110000); + assign _zz_324_ = (decode_INSTRUCTION & (32'b00000000000000000000000001000100)); + assign _zz_325_ = (32'b00000000000000000000000000000000); + assign _zz_326_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000011000)) == (32'b00000000000000000000000000000000)); + assign _zz_327_ = ((decode_INSTRUCTION & (32'b00000000000000000110000000000100)) == (32'b00000000000000000010000000000000)); + assign _zz_328_ = ((decode_INSTRUCTION & (32'b00000000000000000101000000000100)) == (32'b00000000000000000001000000000000)); + assign _zz_329_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000011100)) == (32'b00000000000000000000000000000100)); + assign _zz_330_ = (decode_INSTRUCTION & (32'b00000000000000000000000001011000)); + assign _zz_331_ = (32'b00000000000000000000000001000000); + assign _zz_332_ = (32'b00000000000000000001000001111111); + assign _zz_333_ = (decode_INSTRUCTION & (32'b00000000000000000010000001111111)); + assign _zz_334_ = (32'b00000000000000000010000001110011); + assign _zz_335_ = ((decode_INSTRUCTION & (32'b00000000000000000100000001111111)) == (32'b00000000000000000100000001100011)); + assign _zz_336_ = ((decode_INSTRUCTION & (32'b00000000000000000010000001111111)) == (32'b00000000000000000010000000010011)); + assign _zz_337_ = {((decode_INSTRUCTION & (32'b00000000000000000110000000111111)) == (32'b00000000000000000000000000100011)),{((decode_INSTRUCTION & (32'b00000000000000000010000001111111)) == (32'b00000000000000000000000000000011)),{((decode_INSTRUCTION & _zz_338_) == (32'b00000000000000000000000000000011)),{(_zz_339_ == _zz_340_),{_zz_341_,{_zz_342_,_zz_343_}}}}}}; + assign _zz_338_ = (32'b00000000000000000101000001011111); + assign _zz_339_ = (decode_INSTRUCTION & (32'b00000000000000000111000001111011)); + assign _zz_340_ = (32'b00000000000000000000000001100011); + assign _zz_341_ = ((decode_INSTRUCTION & (32'b00000000000000000110000001111111)) == (32'b00000000000000000000000000001111)); + assign _zz_342_ = ((decode_INSTRUCTION & (32'b11111110000000000000000001111111)) == (32'b00000000000000000000000000110011)); + assign _zz_343_ = {((decode_INSTRUCTION & (32'b10111100000000000111000001111111)) == (32'b00000000000000000101000000010011)),{((decode_INSTRUCTION & (32'b11111100000000000011000001111111)) == (32'b00000000000000000001000000010011)),{((decode_INSTRUCTION & _zz_344_) == (32'b00000000000000000101000000110011)),{(_zz_345_ == _zz_346_),{_zz_347_,{_zz_348_,_zz_349_}}}}}}; + assign _zz_344_ = (32'b10111110000000000111000001111111); + assign _zz_345_ = (decode_INSTRUCTION & (32'b10111110000000000111000001111111)); + assign _zz_346_ = (32'b00000000000000000000000000110011); + assign _zz_347_ = ((decode_INSTRUCTION & (32'b11011111111111111111111111111111)) == (32'b00010000001000000000000001110011)); + assign _zz_348_ = ((decode_INSTRUCTION & (32'b11111111111011111111111111111111)) == (32'b00000000000000000000000001110011)); + assign _zz_349_ = ((decode_INSTRUCTION & (32'b11111111111111111111111111111111)) == (32'b00010000010100000000000001110011)); + initial begin + $readmemb("2-stage-2048-cache-debug.v_toplevel_RegFilePlugin_regFile.bin",RegFilePlugin_regFile); + end + always @ (posedge clk) begin + if(_zz_41_) begin + RegFilePlugin_regFile[execute_RegFilePlugin_regFileWrite_payload_address] <= execute_RegFilePlugin_regFileWrite_payload_data; + end + end + + always @ (posedge clk) begin + if(_zz_102_) begin + _zz_153_ <= RegFilePlugin_regFile[execute_RegFilePlugin_regFileReadAddress1]; + end + end + + always @ (posedge clk) begin + if(_zz_102_) begin + _zz_154_ <= RegFilePlugin_regFile[execute_RegFilePlugin_regFileReadAddress2]; + end + end + + InstructionCache IBusCachedPlugin_cache ( + .io_flush(_zz_135_), + .io_cpu_prefetch_isValid(_zz_136_), + .io_cpu_prefetch_haltIt(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt), + .io_cpu_prefetch_pc(IBusCachedPlugin_iBusRsp_stages_0_input_payload), + .io_cpu_fetch_isValid(_zz_137_), + .io_cpu_fetch_isStuck(_zz_138_), + .io_cpu_fetch_isRemoved(_zz_139_), + .io_cpu_fetch_pc(IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload), + .io_cpu_fetch_data(IBusCachedPlugin_cache_io_cpu_fetch_data), + .io_cpu_fetch_dataBypassValid(IBusCachedPlugin_s1_tightlyCoupledHit), + .io_cpu_fetch_dataBypass(_zz_140_), + .io_cpu_fetch_mmuBus_cmd_isValid(IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_isValid), + .io_cpu_fetch_mmuBus_cmd_virtualAddress(IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_virtualAddress), + .io_cpu_fetch_mmuBus_cmd_bypassTranslation(IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_bypassTranslation), + .io_cpu_fetch_mmuBus_rsp_physicalAddress(IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_virtualAddress), + .io_cpu_fetch_mmuBus_rsp_isIoAccess(_zz_141_), + .io_cpu_fetch_mmuBus_rsp_allowRead(_zz_142_), + .io_cpu_fetch_mmuBus_rsp_allowWrite(_zz_143_), + .io_cpu_fetch_mmuBus_rsp_allowExecute(_zz_144_), + .io_cpu_fetch_mmuBus_rsp_exception(_zz_145_), + .io_cpu_fetch_mmuBus_rsp_refilling(_zz_146_), + .io_cpu_fetch_mmuBus_end(IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_end), + .io_cpu_fetch_mmuBus_busy(_zz_147_), + .io_cpu_fetch_physicalAddress(IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress), + .io_cpu_fetch_cacheMiss(IBusCachedPlugin_cache_io_cpu_fetch_cacheMiss), + .io_cpu_fetch_error(IBusCachedPlugin_cache_io_cpu_fetch_error), + .io_cpu_fetch_mmuRefilling(IBusCachedPlugin_cache_io_cpu_fetch_mmuRefilling), + .io_cpu_fetch_mmuException(IBusCachedPlugin_cache_io_cpu_fetch_mmuException), + .io_cpu_fetch_isUser(_zz_148_), + .io_cpu_fetch_haltIt(IBusCachedPlugin_cache_io_cpu_fetch_haltIt), + .io_cpu_decode_isValid(_zz_149_), + .io_cpu_decode_isStuck(_zz_150_), + .io_cpu_decode_pc(_zz_151_), + .io_cpu_decode_physicalAddress(IBusCachedPlugin_cache_io_cpu_decode_physicalAddress), + .io_cpu_decode_data(IBusCachedPlugin_cache_io_cpu_decode_data), + .io_cpu_fill_valid(_zz_152_), + .io_cpu_fill_payload(IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress), + .io_mem_cmd_valid(IBusCachedPlugin_cache_io_mem_cmd_valid), + .io_mem_cmd_ready(iBus_cmd_ready), + .io_mem_cmd_payload_address(IBusCachedPlugin_cache_io_mem_cmd_payload_address), + .io_mem_cmd_payload_size(IBusCachedPlugin_cache_io_mem_cmd_payload_size), + .io_mem_rsp_valid(iBus_rsp_valid), + .io_mem_rsp_payload_data(iBus_rsp_payload_data), + .io_mem_rsp_payload_error(iBus_rsp_payload_error), + .clk(clk), + .reset(reset) + ); + always @(*) begin + case(_zz_223_) + 2'b00 : begin + _zz_155_ = BranchPlugin_jumpInterface_payload; + end + 2'b01 : begin + _zz_155_ = CsrPlugin_jumpInterface_payload; + end + default : begin + _zz_155_ = IBusCachedPlugin_redoBranch_payload; + end + endcase + end + + always @(*) begin + case(_zz_127_) + 2'b00 : begin + _zz_156_ = DBusSimplePlugin_memoryExceptionPort_payload_code; + _zz_157_ = DBusSimplePlugin_memoryExceptionPort_payload_badAddr; + end + 2'b01 : begin + _zz_156_ = BranchPlugin_branchExceptionPort_payload_code; + _zz_157_ = BranchPlugin_branchExceptionPort_payload_badAddr; + end + default : begin + _zz_156_ = CsrPlugin_selfException_payload_code; + _zz_157_ = CsrPlugin_selfException_payload_badAddr; + end + endcase + end + + `ifndef SYNTHESIS + always @(*) begin + case(decode_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : decode_ALU_CTRL_string = "BITWISE "; + default : decode_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(_zz_1_) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_1__string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_1__string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_1__string = "BITWISE "; + default : _zz_1__string = "????????"; + endcase + end + always @(*) begin + case(_zz_2_) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_2__string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_2__string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_2__string = "BITWISE "; + default : _zz_2__string = "????????"; + endcase + end + always @(*) begin + case(_zz_3_) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_3__string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_3__string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_3__string = "BITWISE "; + default : _zz_3__string = "????????"; + endcase + end + always @(*) begin + case(decode_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : decode_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : decode_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : decode_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : decode_SRC2_CTRL_string = "PC "; + default : decode_SRC2_CTRL_string = "???"; + endcase + end + always @(*) begin + case(_zz_4_) + `Src2CtrlEnum_defaultEncoding_RS : _zz_4__string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_4__string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_4__string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_4__string = "PC "; + default : _zz_4__string = "???"; + endcase + end + always @(*) begin + case(_zz_5_) + `Src2CtrlEnum_defaultEncoding_RS : _zz_5__string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_5__string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_5__string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_5__string = "PC "; + default : _zz_5__string = "???"; + endcase + end + always @(*) begin + case(_zz_6_) + `Src2CtrlEnum_defaultEncoding_RS : _zz_6__string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_6__string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_6__string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_6__string = "PC "; + default : _zz_6__string = "???"; + endcase + end + always @(*) begin + case(decode_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : decode_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : decode_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : decode_SRC1_CTRL_string = "URS1 "; + default : decode_SRC1_CTRL_string = "????????????"; + endcase + end + always @(*) begin + case(_zz_7_) + `Src1CtrlEnum_defaultEncoding_RS : _zz_7__string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_7__string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_7__string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_7__string = "URS1 "; + default : _zz_7__string = "????????????"; + endcase + end + always @(*) begin + case(_zz_8_) + `Src1CtrlEnum_defaultEncoding_RS : _zz_8__string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_8__string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_8__string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_8__string = "URS1 "; + default : _zz_8__string = "????????????"; + endcase + end + always @(*) begin + case(_zz_9_) + `Src1CtrlEnum_defaultEncoding_RS : _zz_9__string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_9__string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_9__string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_9__string = "URS1 "; + default : _zz_9__string = "????????????"; + endcase + end + always @(*) begin + case(decode_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : decode_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : decode_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : decode_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : decode_BRANCH_CTRL_string = "JALR"; + default : decode_BRANCH_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_10_) + `BranchCtrlEnum_defaultEncoding_INC : _zz_10__string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_10__string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_10__string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_10__string = "JALR"; + default : _zz_10__string = "????"; + endcase + end + always @(*) begin + case(_zz_11_) + `BranchCtrlEnum_defaultEncoding_INC : _zz_11__string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_11__string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_11__string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_11__string = "JALR"; + default : _zz_11__string = "????"; + endcase + end + always @(*) begin + case(_zz_12_) + `BranchCtrlEnum_defaultEncoding_INC : _zz_12__string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_12__string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_12__string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_12__string = "JALR"; + default : _zz_12__string = "????"; + endcase + end + always @(*) begin + case(decode_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 "; + default : decode_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_13_) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_13__string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_13__string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_13__string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_13__string = "SRA_1 "; + default : _zz_13__string = "?????????"; + endcase + end + always @(*) begin + case(_zz_14_) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_14__string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_14__string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_14__string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_14__string = "SRA_1 "; + default : _zz_14__string = "?????????"; + endcase + end + always @(*) begin + case(_zz_15_) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_15__string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_15__string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_15__string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_15__string = "SRA_1 "; + default : _zz_15__string = "?????????"; + endcase + end + always @(*) begin + case(decode_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : decode_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : decode_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : decode_ENV_CTRL_string = "ECALL "; + `EnvCtrlEnum_defaultEncoding_EBREAK : decode_ENV_CTRL_string = "EBREAK"; + default : decode_ENV_CTRL_string = "??????"; + endcase + end + always @(*) begin + case(_zz_16_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_16__string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_16__string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_16__string = "ECALL "; + `EnvCtrlEnum_defaultEncoding_EBREAK : _zz_16__string = "EBREAK"; + default : _zz_16__string = "??????"; + endcase + end + always @(*) begin + case(_zz_17_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_17__string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_17__string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_17__string = "ECALL "; + `EnvCtrlEnum_defaultEncoding_EBREAK : _zz_17__string = "EBREAK"; + default : _zz_17__string = "??????"; + endcase + end + always @(*) begin + case(_zz_18_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_18__string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_18__string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_18__string = "ECALL "; + `EnvCtrlEnum_defaultEncoding_EBREAK : _zz_18__string = "EBREAK"; + default : _zz_18__string = "??????"; + endcase + end + always @(*) begin + case(decode_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1"; + default : decode_ALU_BITWISE_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_19_) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_19__string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_19__string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_19__string = "AND_1"; + default : _zz_19__string = "?????"; + endcase + end + always @(*) begin + case(_zz_20_) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_20__string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_20__string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_20__string = "AND_1"; + default : _zz_20__string = "?????"; + endcase + end + always @(*) begin + case(_zz_21_) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_21__string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_21__string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_21__string = "AND_1"; + default : _zz_21__string = "?????"; + endcase + end + always @(*) begin + case(execute_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : execute_ENV_CTRL_string = "ECALL "; + `EnvCtrlEnum_defaultEncoding_EBREAK : execute_ENV_CTRL_string = "EBREAK"; + default : execute_ENV_CTRL_string = "??????"; + endcase + end + always @(*) begin + case(_zz_25_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_25__string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_25__string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_25__string = "ECALL "; + `EnvCtrlEnum_defaultEncoding_EBREAK : _zz_25__string = "EBREAK"; + default : _zz_25__string = "??????"; + endcase + end + always @(*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : execute_BRANCH_CTRL_string = "JALR"; + default : execute_BRANCH_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_27_) + `BranchCtrlEnum_defaultEncoding_INC : _zz_27__string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_27__string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_27__string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_27__string = "JALR"; + default : _zz_27__string = "????"; + endcase + end + always @(*) begin + case(execute_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : execute_SHIFT_CTRL_string = "SRA_1 "; + default : execute_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_29_) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_29__string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_29__string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_29__string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_29__string = "SRA_1 "; + default : _zz_29__string = "?????????"; + endcase + end + always @(*) begin + case(execute_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : execute_SRC2_CTRL_string = "PC "; + default : execute_SRC2_CTRL_string = "???"; + endcase + end + always @(*) begin + case(_zz_33_) + `Src2CtrlEnum_defaultEncoding_RS : _zz_33__string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_33__string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_33__string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_33__string = "PC "; + default : _zz_33__string = "???"; + endcase + end + always @(*) begin + case(execute_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : execute_SRC1_CTRL_string = "URS1 "; + default : execute_SRC1_CTRL_string = "????????????"; + endcase + end + always @(*) begin + case(_zz_35_) + `Src1CtrlEnum_defaultEncoding_RS : _zz_35__string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_35__string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_35__string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_35__string = "URS1 "; + default : _zz_35__string = "????????????"; + endcase + end + always @(*) begin + case(execute_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : execute_ALU_CTRL_string = "BITWISE "; + default : execute_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(_zz_38_) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_38__string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_38__string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_38__string = "BITWISE "; + default : _zz_38__string = "????????"; + endcase + end + always @(*) begin + case(execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : execute_ALU_BITWISE_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_40_) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_40__string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_40__string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_40__string = "AND_1"; + default : _zz_40__string = "?????"; + endcase + end + always @(*) begin + case(_zz_48_) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_48__string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_48__string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_48__string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_48__string = "SRA_1 "; + default : _zz_48__string = "?????????"; + endcase + end + always @(*) begin + case(_zz_50_) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_50__string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_50__string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_50__string = "AND_1"; + default : _zz_50__string = "?????"; + endcase + end + always @(*) begin + case(_zz_51_) + `Src1CtrlEnum_defaultEncoding_RS : _zz_51__string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_51__string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_51__string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_51__string = "URS1 "; + default : _zz_51__string = "????????????"; + endcase + end + always @(*) begin + case(_zz_54_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_54__string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_54__string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_54__string = "ECALL "; + `EnvCtrlEnum_defaultEncoding_EBREAK : _zz_54__string = "EBREAK"; + default : _zz_54__string = "??????"; + endcase + end + always @(*) begin + case(_zz_56_) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_56__string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_56__string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_56__string = "BITWISE "; + default : _zz_56__string = "????????"; + endcase + end + always @(*) begin + case(_zz_57_) + `Src2CtrlEnum_defaultEncoding_RS : _zz_57__string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_57__string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_57__string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_57__string = "PC "; + default : _zz_57__string = "???"; + endcase + end + always @(*) begin + case(_zz_59_) + `BranchCtrlEnum_defaultEncoding_INC : _zz_59__string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_59__string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_59__string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_59__string = "JALR"; + default : _zz_59__string = "????"; + endcase + end + always @(*) begin + case(_zz_95_) + `BranchCtrlEnum_defaultEncoding_INC : _zz_95__string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_95__string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_95__string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_95__string = "JALR"; + default : _zz_95__string = "????"; + endcase + end + always @(*) begin + case(_zz_96_) + `Src2CtrlEnum_defaultEncoding_RS : _zz_96__string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_96__string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_96__string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_96__string = "PC "; + default : _zz_96__string = "???"; + endcase + end + always @(*) begin + case(_zz_97_) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_97__string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_97__string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_97__string = "BITWISE "; + default : _zz_97__string = "????????"; + endcase + end + always @(*) begin + case(_zz_98_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_98__string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_98__string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_98__string = "ECALL "; + `EnvCtrlEnum_defaultEncoding_EBREAK : _zz_98__string = "EBREAK"; + default : _zz_98__string = "??????"; + endcase + end + always @(*) begin + case(_zz_99_) + `Src1CtrlEnum_defaultEncoding_RS : _zz_99__string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_99__string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_99__string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_99__string = "URS1 "; + default : _zz_99__string = "????????????"; + endcase + end + always @(*) begin + case(_zz_100_) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_100__string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_100__string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_100__string = "AND_1"; + default : _zz_100__string = "?????"; + endcase + end + always @(*) begin + case(_zz_101_) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_101__string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_101__string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_101__string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_101__string = "SRA_1 "; + default : _zz_101__string = "?????????"; + endcase + end + always @(*) begin + case(decode_to_execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : decode_to_execute_ALU_BITWISE_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(decode_to_execute_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : decode_to_execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : decode_to_execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : decode_to_execute_ENV_CTRL_string = "ECALL "; + `EnvCtrlEnum_defaultEncoding_EBREAK : decode_to_execute_ENV_CTRL_string = "EBREAK"; + default : decode_to_execute_ENV_CTRL_string = "??????"; + endcase + end + always @(*) begin + case(decode_to_execute_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; + default : decode_to_execute_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(decode_to_execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : decode_to_execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : decode_to_execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR"; + default : decode_to_execute_BRANCH_CTRL_string = "????"; + endcase + end + always @(*) begin + case(decode_to_execute_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : decode_to_execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : decode_to_execute_SRC1_CTRL_string = "URS1 "; + default : decode_to_execute_SRC1_CTRL_string = "????????????"; + endcase + end + always @(*) begin + case(decode_to_execute_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : decode_to_execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : decode_to_execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : decode_to_execute_SRC2_CTRL_string = "PC "; + default : decode_to_execute_SRC2_CTRL_string = "???"; + endcase + end + always @(*) begin + case(decode_to_execute_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE "; + default : decode_to_execute_ALU_CTRL_string = "????????"; + endcase + end + `endif + + assign decode_ALU_CTRL = _zz_1_; + assign _zz_2_ = _zz_3_; + assign decode_DO_EBREAK = _zz_22_; + assign execute_REGFILE_WRITE_VALID = decode_to_execute_REGFILE_WRITE_VALID; + assign decode_SRC2_CTRL = _zz_4_; + assign _zz_5_ = _zz_6_; + assign decode_SRC1_CTRL = _zz_7_; + assign _zz_8_ = _zz_9_; + assign decode_SRC_LESS_UNSIGNED = _zz_49_; + assign decode_CSR_WRITE_OPCODE = _zz_24_; + assign decode_SRC2_FORCE_ZERO = _zz_37_; + assign decode_IS_CSR = _zz_44_; + assign decode_BRANCH_CTRL = _zz_10_; + assign _zz_11_ = _zz_12_; + assign decode_MEMORY_STORE = _zz_55_; + assign decode_SHIFT_CTRL = _zz_13_; + assign _zz_14_ = _zz_15_; + assign decode_ENV_CTRL = _zz_16_; + assign _zz_17_ = _zz_18_; + assign decode_MEMORY_ENABLE = _zz_52_; + assign decode_CSR_READ_OPCODE = _zz_23_; + assign decode_ALU_BITWISE_CTRL = _zz_19_; + assign _zz_20_ = _zz_21_; + assign execute_FORMAL_PC_NEXT = decode_to_execute_FORMAL_PC_NEXT; + assign decode_FORMAL_PC_NEXT = _zz_69_; + assign execute_DO_EBREAK = decode_to_execute_DO_EBREAK; + assign decode_IS_EBREAK = _zz_47_; + assign execute_CSR_READ_OPCODE = decode_to_execute_CSR_READ_OPCODE; + assign execute_CSR_WRITE_OPCODE = decode_to_execute_CSR_WRITE_OPCODE; + assign execute_IS_CSR = decode_to_execute_IS_CSR; + assign execute_ENV_CTRL = _zz_25_; + assign execute_BRANCH_CALC = _zz_26_; + assign execute_BRANCH_DO = _zz_28_; + assign execute_PC = decode_to_execute_PC; + assign execute_RS1 = _zz_43_; + assign execute_BRANCH_CTRL = _zz_27_; + assign execute_SHIFT_CTRL = _zz_29_; + assign execute_SRC_LESS_UNSIGNED = decode_to_execute_SRC_LESS_UNSIGNED; + assign execute_SRC2_FORCE_ZERO = decode_to_execute_SRC2_FORCE_ZERO; + assign execute_SRC_USE_SUB_LESS = decode_to_execute_SRC_USE_SUB_LESS; + assign execute_SRC2_CTRL = _zz_33_; + assign execute_SRC1_CTRL = _zz_35_; + assign decode_SRC_USE_SUB_LESS = _zz_58_; + assign decode_SRC_ADD_ZERO = _zz_53_; + assign execute_SRC_ADD_SUB = _zz_32_; + assign execute_SRC_LESS = _zz_30_; + assign execute_ALU_CTRL = _zz_38_; + assign execute_SRC2 = _zz_34_; + assign execute_SRC1 = _zz_36_; + assign execute_ALU_BITWISE_CTRL = _zz_40_; + always @ (*) begin + _zz_41_ = 1'b0; + if(execute_RegFilePlugin_regFileWrite_valid)begin + _zz_41_ = 1'b1; + end + end + + always @ (*) begin + decode_REGFILE_WRITE_VALID = _zz_46_; + if((decode_INSTRUCTION[11 : 7] == (5'b00000)))begin + decode_REGFILE_WRITE_VALID = 1'b0; + end + end + + assign decode_LEGAL_INSTRUCTION = _zz_60_; + assign decode_INSTRUCTION_READY = 1'b1; + always @ (*) begin + _zz_61_ = execute_REGFILE_WRITE_DATA; + execute_arbitration_haltItself = 1'b0; + if(((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! dBus_cmd_ready)) && (! execute_DBusSimplePlugin_skipCmd)) && (! execute_DBusSimplePlugin_cmdSent)))begin + execute_arbitration_haltItself = 1'b1; + end + if((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! execute_MEMORY_STORE)) && (! dBus_rsp_ready)))begin + execute_arbitration_haltItself = 1'b1; + end + if((execute_arbitration_isValid && execute_MEMORY_ENABLE))begin + _zz_61_ = execute_DBusSimplePlugin_rspFormated; + end + if(_zz_158_)begin + _zz_61_ = _zz_110_; + if(_zz_159_)begin + if(! execute_LightShifterPlugin_done) begin + execute_arbitration_haltItself = 1'b1; + end + end + end + if((execute_arbitration_isValid && execute_IS_CSR))begin + _zz_61_ = execute_CsrPlugin_readData; + if(execute_CsrPlugin_blockedBySideEffects)begin + execute_arbitration_haltItself = 1'b1; + end + end + end + + assign execute_MEMORY_ADDRESS_LOW = _zz_63_; + assign execute_MEMORY_READ_DATA = _zz_62_; + assign execute_REGFILE_WRITE_DATA = _zz_39_; + assign execute_SRC_ADD = _zz_31_; + assign execute_RS2 = _zz_42_; + assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION; + assign execute_MEMORY_STORE = decode_to_execute_MEMORY_STORE; + assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE; + assign execute_ALIGNEMENT_FAULT = _zz_64_; + assign decode_FLUSH_ALL = _zz_45_; + always @ (*) begin + IBusCachedPlugin_rsp_issueDetected = _zz_65_; + _zz_66_ = _zz_67_; + IBusCachedPlugin_decodeExceptionPort_valid = 1'b0; + IBusCachedPlugin_decodeExceptionPort_payload_code = (4'bxxxx); + if(((_zz_137_ && IBusCachedPlugin_cache_io_cpu_fetch_mmuException) && (! _zz_67_)))begin + _zz_66_ = 1'b1; + IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; + IBusCachedPlugin_decodeExceptionPort_payload_code = (4'b1100); + end + if(((_zz_137_ && IBusCachedPlugin_cache_io_cpu_fetch_error) && (! _zz_65_)))begin + IBusCachedPlugin_rsp_issueDetected = 1'b1; + IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; + IBusCachedPlugin_decodeExceptionPort_payload_code = (4'b0001); + end + if(IBusCachedPlugin_fetcherHalt)begin + IBusCachedPlugin_decodeExceptionPort_valid = 1'b0; + end + end + + always @ (*) begin + _zz_65_ = _zz_66_; + _zz_67_ = 1'b0; + IBusCachedPlugin_rsp_redoFetch = 1'b0; + _zz_152_ = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_fetch_mmuRefilling)); + if(((_zz_137_ && IBusCachedPlugin_cache_io_cpu_fetch_mmuRefilling) && (! 1'b0)))begin + _zz_67_ = 1'b1; + IBusCachedPlugin_rsp_redoFetch = 1'b1; + end + if(((_zz_137_ && IBusCachedPlugin_cache_io_cpu_fetch_cacheMiss) && (! _zz_66_)))begin + _zz_65_ = 1'b1; + _zz_152_ = 1'b1; + IBusCachedPlugin_rsp_redoFetch = 1'b1; + end + if((! IBusCachedPlugin_iBusRsp_readyForError))begin + IBusCachedPlugin_rsp_redoFetch = 1'b0; + end + if((! IBusCachedPlugin_iBusRsp_readyForError))begin + _zz_152_ = 1'b0; + end + end + + always @ (*) begin + _zz_68_ = decode_FORMAL_PC_NEXT; + if(IBusCachedPlugin_redoBranch_valid)begin + _zz_68_ = IBusCachedPlugin_redoBranch_payload; + end + end + + assign decode_PC = _zz_71_; + always @ (*) begin + decode_INSTRUCTION = _zz_70_; + if((_zz_131_ != (3'b000)))begin + decode_INSTRUCTION = IBusCachedPlugin_injectionPort_payload_regNext; + end + end + + always @ (*) begin + decode_arbitration_haltItself = 1'b0; + decode_arbitration_isValid = (IBusCachedPlugin_iBusRsp_decodeInput_valid && (! IBusCachedPlugin_injector_decodeRemoved)); + IBusCachedPlugin_injectionPort_ready = 1'b0; + case(_zz_131_) + 3'b000 : begin + end + 3'b001 : begin + end + 3'b010 : begin + decode_arbitration_isValid = 1'b1; + decode_arbitration_haltItself = 1'b1; + end + 3'b011 : begin + decode_arbitration_isValid = 1'b1; + end + 3'b100 : begin + IBusCachedPlugin_injectionPort_ready = 1'b1; + end + default : begin + end + endcase + end + + always @ (*) begin + decode_arbitration_haltByOther = 1'b0; + if(CsrPlugin_interrupt)begin + decode_arbitration_haltByOther = decode_arbitration_isValid; + end + if(((execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)) != (1'b0)))begin + decode_arbitration_haltByOther = 1'b1; + end + end + + always @ (*) begin + decode_arbitration_removeIt = 1'b0; + if(_zz_160_)begin + decode_arbitration_removeIt = 1'b1; + end + if(decode_arbitration_isFlushed)begin + decode_arbitration_removeIt = 1'b1; + end + end + + always @ (*) begin + decode_arbitration_flushAll = 1'b0; + execute_arbitration_haltByOther = 1'b0; + execute_arbitration_removeIt = 1'b0; + IBusCachedPlugin_fetcherHalt = 1'b0; + IBusCachedPlugin_fetcherflushIt = 1'b0; + CsrPlugin_jumpInterface_valid = 1'b0; + CsrPlugin_jumpInterface_payload = (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx); + if(BranchPlugin_jumpInterface_valid)begin + decode_arbitration_flushAll = 1'b1; + end + CsrPlugin_exceptionPortCtrl_exceptionValids_execute = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; + if(_zz_161_)begin + decode_arbitration_flushAll = 1'b1; + execute_arbitration_removeIt = 1'b1; + CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b1; + end + if(execute_arbitration_isFlushed)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b0; + end + if(({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode} != (2'b00)))begin + IBusCachedPlugin_fetcherHalt = 1'b1; + end + if(_zz_162_)begin + IBusCachedPlugin_fetcherHalt = 1'b1; + CsrPlugin_jumpInterface_valid = 1'b1; + CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,(2'b00)}; + decode_arbitration_flushAll = 1'b1; + end + if(_zz_163_)begin + IBusCachedPlugin_fetcherHalt = 1'b1; + CsrPlugin_jumpInterface_valid = 1'b1; + decode_arbitration_flushAll = 1'b1; + case(_zz_164_) + 2'b11 : begin + CsrPlugin_jumpInterface_payload = CsrPlugin_mepc; + end + default : begin + end + endcase + end + if(_zz_165_)begin + execute_arbitration_haltByOther = 1'b1; + if(_zz_166_)begin + IBusCachedPlugin_fetcherflushIt = 1'b1; + IBusCachedPlugin_fetcherHalt = 1'b1; + end + end + if(DebugPlugin_haltIt)begin + IBusCachedPlugin_fetcherHalt = 1'b1; + end + if(_zz_167_)begin + IBusCachedPlugin_fetcherHalt = 1'b1; + end + if(execute_arbitration_isFlushed)begin + execute_arbitration_removeIt = 1'b1; + end + end + + always @ (*) begin + execute_arbitration_flushAll = 1'b0; + if(_zz_165_)begin + if(_zz_166_)begin + execute_arbitration_flushAll = 1'b1; + end + end + end + + always @ (*) begin + IBusCachedPlugin_incomingInstruction = 1'b0; + if(IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid)begin + IBusCachedPlugin_incomingInstruction = 1'b1; + end + end + + always @ (*) begin + CsrPlugin_forceMachineWire = 1'b0; + CsrPlugin_allowException = 1'b1; + if(DebugPlugin_godmode)begin + CsrPlugin_allowException = 1'b0; + CsrPlugin_forceMachineWire = 1'b1; + end + end + + always @ (*) begin + CsrPlugin_allowInterrupts = 1'b1; + if((DebugPlugin_haltIt || DebugPlugin_stepIt))begin + CsrPlugin_allowInterrupts = 1'b0; + end + end + + assign IBusCachedPlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,IBusCachedPlugin_redoBranch_valid}} != (3'b000)); + assign _zz_72_ = {IBusCachedPlugin_redoBranch_valid,{CsrPlugin_jumpInterface_valid,BranchPlugin_jumpInterface_valid}}; + assign _zz_73_ = (_zz_72_ & (~ _zz_174_)); + assign _zz_74_ = _zz_73_[1]; + assign _zz_75_ = _zz_73_[2]; + assign IBusCachedPlugin_jump_pcLoad_payload = _zz_155_; + assign _zz_76_ = (! IBusCachedPlugin_fetcherHalt); + assign IBusCachedPlugin_fetchPc_output_valid = (IBusCachedPlugin_fetchPc_preOutput_valid && _zz_76_); + assign IBusCachedPlugin_fetchPc_preOutput_ready = (IBusCachedPlugin_fetchPc_output_ready && _zz_76_); + assign IBusCachedPlugin_fetchPc_output_payload = IBusCachedPlugin_fetchPc_preOutput_payload; + always @ (*) begin + IBusCachedPlugin_fetchPc_propagatePc = 1'b0; + if((IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid && IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready))begin + IBusCachedPlugin_fetchPc_propagatePc = 1'b1; + end + end + + always @ (*) begin + IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_176_); + IBusCachedPlugin_fetchPc_samplePcNext = 1'b0; + if(IBusCachedPlugin_fetchPc_propagatePc)begin + IBusCachedPlugin_fetchPc_samplePcNext = 1'b1; + end + if(IBusCachedPlugin_jump_pcLoad_valid)begin + IBusCachedPlugin_fetchPc_samplePcNext = 1'b1; + IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_jump_pcLoad_payload; + end + if(_zz_168_)begin + IBusCachedPlugin_fetchPc_samplePcNext = 1'b1; + end + IBusCachedPlugin_fetchPc_pc[0] = 1'b0; + IBusCachedPlugin_fetchPc_pc[1] = 1'b0; + end + + assign IBusCachedPlugin_fetchPc_preOutput_valid = _zz_77_; + assign IBusCachedPlugin_fetchPc_preOutput_payload = IBusCachedPlugin_fetchPc_pc; + assign IBusCachedPlugin_iBusRsp_stages_0_input_valid = IBusCachedPlugin_fetchPc_output_valid; + assign IBusCachedPlugin_fetchPc_output_ready = IBusCachedPlugin_iBusRsp_stages_0_input_ready; + assign IBusCachedPlugin_iBusRsp_stages_0_input_payload = IBusCachedPlugin_fetchPc_output_payload; + assign IBusCachedPlugin_iBusRsp_stages_0_inputSample = 1'b1; + always @ (*) begin + IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b0; + if(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt)begin + IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b1; + end + end + + assign _zz_78_ = (! IBusCachedPlugin_iBusRsp_stages_0_halt); + assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_78_); + assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_78_); + assign IBusCachedPlugin_iBusRsp_stages_0_output_payload = IBusCachedPlugin_iBusRsp_stages_0_input_payload; + always @ (*) begin + IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt = 1'b0; + if(IBusCachedPlugin_cache_io_cpu_fetch_haltIt)begin + IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt = 1'b1; + end + if((IBusCachedPlugin_rsp_issueDetected || IBusCachedPlugin_rsp_iBusRspOutputHalt))begin + IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt = 1'b1; + end + end + + assign _zz_79_ = (! IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt); + assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready = (IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_ready && _zz_79_); + assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_valid = (IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid && _zz_79_); + assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_payload = IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload; + assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_80_; + assign _zz_80_ = ((1'b0 && (! _zz_81_)) || IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready); + assign _zz_81_ = _zz_82_; + assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid = _zz_81_; + assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload = IBusCachedPlugin_fetchPc_pcReg; + always @ (*) begin + IBusCachedPlugin_iBusRsp_readyForError = 1'b1; + if((! IBusCachedPlugin_pcValids_0))begin + IBusCachedPlugin_iBusRsp_readyForError = 1'b0; + end + end + + assign IBusCachedPlugin_pcValids_0 = IBusCachedPlugin_injector_nextPcCalc_valids_0; + assign IBusCachedPlugin_pcValids_1 = IBusCachedPlugin_injector_nextPcCalc_valids_1; + assign IBusCachedPlugin_iBusRsp_decodeInput_ready = (! decode_arbitration_isStuck); + assign _zz_71_ = IBusCachedPlugin_iBusRsp_decodeInput_payload_pc; + assign _zz_70_ = IBusCachedPlugin_iBusRsp_decodeInput_payload_rsp_inst; + assign _zz_69_ = (decode_PC + (32'b00000000000000000000000000000100)); + assign iBus_cmd_valid = IBusCachedPlugin_cache_io_mem_cmd_valid; + always @ (*) begin + iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; + iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; + end + + assign iBus_cmd_payload_size = IBusCachedPlugin_cache_io_mem_cmd_payload_size; + assign IBusCachedPlugin_s0_tightlyCoupledHit = 1'b0; + assign _zz_136_ = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); + assign _zz_139_ = (IBusCachedPlugin_jump_pcLoad_valid || IBusCachedPlugin_fetcherflushIt); + assign _zz_140_ = (32'b00000000000000000000000000000000); + assign _zz_137_ = (IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); + assign _zz_138_ = (! IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready); + assign _zz_148_ = (CsrPlugin_privilege == (2'b00)); + assign IBusCachedPlugin_rsp_iBusRspOutputHalt = 1'b0; + assign IBusCachedPlugin_decodeExceptionPort_payload_badAddr = {IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload[31 : 2],(2'b00)}; + assign IBusCachedPlugin_redoBranch_valid = IBusCachedPlugin_rsp_redoFetch; + assign IBusCachedPlugin_redoBranch_payload = IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload; + assign IBusCachedPlugin_iBusRsp_decodeInput_valid = IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_valid; + assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_ready = IBusCachedPlugin_iBusRsp_decodeInput_ready; + assign IBusCachedPlugin_iBusRsp_decodeInput_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_fetch_data; + assign IBusCachedPlugin_iBusRsp_decodeInput_payload_pc = IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_payload; + assign _zz_144_ = 1'b1; + assign _zz_142_ = 1'b1; + assign _zz_143_ = 1'b1; + assign _zz_141_ = 1'b0; + assign _zz_145_ = 1'b0; + assign _zz_146_ = 1'b0; + assign _zz_147_ = 1'b0; + assign _zz_135_ = (decode_arbitration_isValid && decode_FLUSH_ALL); + assign _zz_64_ = (((dBus_cmd_payload_size == (2'b10)) && (dBus_cmd_payload_address[1 : 0] != (2'b00))) || ((dBus_cmd_payload_size == (2'b01)) && (dBus_cmd_payload_address[0 : 0] != (1'b0)))); + always @ (*) begin + execute_DBusSimplePlugin_skipCmd = 1'b0; + if(execute_ALIGNEMENT_FAULT)begin + execute_DBusSimplePlugin_skipCmd = 1'b1; + end + end + + assign dBus_cmd_valid = (((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! execute_arbitration_isStuckByOthers)) && (! execute_arbitration_isFlushed)) && (! execute_DBusSimplePlugin_skipCmd)) && (! execute_DBusSimplePlugin_cmdSent)); + assign dBus_cmd_payload_wr = execute_MEMORY_STORE; + assign dBus_cmd_payload_size = execute_INSTRUCTION[13 : 12]; + always @ (*) begin + case(dBus_cmd_payload_size) + 2'b00 : begin + _zz_83_ = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; + end + 2'b01 : begin + _zz_83_ = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; + end + default : begin + _zz_83_ = execute_RS2[31 : 0]; + end + endcase + end + + assign dBus_cmd_payload_data = _zz_83_; + assign _zz_63_ = dBus_cmd_payload_address[1 : 0]; + always @ (*) begin + case(dBus_cmd_payload_size) + 2'b00 : begin + _zz_84_ = (4'b0001); + end + 2'b01 : begin + _zz_84_ = (4'b0011); + end + default : begin + _zz_84_ = (4'b1111); + end + endcase + end + + assign execute_DBusSimplePlugin_formalMask = (_zz_84_ <<< dBus_cmd_payload_address[1 : 0]); + assign dBus_cmd_payload_address = execute_SRC_ADD; + assign _zz_62_ = dBus_rsp_data; + always @ (*) begin + DBusSimplePlugin_memoryExceptionPort_valid = 1'b0; + DBusSimplePlugin_memoryExceptionPort_payload_code = (4'bxxxx); + if(execute_ALIGNEMENT_FAULT)begin + DBusSimplePlugin_memoryExceptionPort_payload_code = {1'd0, _zz_177_}; + DBusSimplePlugin_memoryExceptionPort_valid = 1'b1; + end + if((! ((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (1'b0 || (! execute_arbitration_isStuckByOthers)))))begin + DBusSimplePlugin_memoryExceptionPort_valid = 1'b0; + end + end + + assign DBusSimplePlugin_memoryExceptionPort_payload_badAddr = execute_REGFILE_WRITE_DATA; + always @ (*) begin + execute_DBusSimplePlugin_rspShifted = execute_MEMORY_READ_DATA; + case(execute_MEMORY_ADDRESS_LOW) + 2'b01 : begin + execute_DBusSimplePlugin_rspShifted[7 : 0] = execute_MEMORY_READ_DATA[15 : 8]; + end + 2'b10 : begin + execute_DBusSimplePlugin_rspShifted[15 : 0] = execute_MEMORY_READ_DATA[31 : 16]; + end + 2'b11 : begin + execute_DBusSimplePlugin_rspShifted[7 : 0] = execute_MEMORY_READ_DATA[31 : 24]; + end + default : begin + end + endcase + end + + assign _zz_85_ = (execute_DBusSimplePlugin_rspShifted[7] && (! execute_INSTRUCTION[14])); + always @ (*) begin + _zz_86_[31] = _zz_85_; + _zz_86_[30] = _zz_85_; + _zz_86_[29] = _zz_85_; + _zz_86_[28] = _zz_85_; + _zz_86_[27] = _zz_85_; + _zz_86_[26] = _zz_85_; + _zz_86_[25] = _zz_85_; + _zz_86_[24] = _zz_85_; + _zz_86_[23] = _zz_85_; + _zz_86_[22] = _zz_85_; + _zz_86_[21] = _zz_85_; + _zz_86_[20] = _zz_85_; + _zz_86_[19] = _zz_85_; + _zz_86_[18] = _zz_85_; + _zz_86_[17] = _zz_85_; + _zz_86_[16] = _zz_85_; + _zz_86_[15] = _zz_85_; + _zz_86_[14] = _zz_85_; + _zz_86_[13] = _zz_85_; + _zz_86_[12] = _zz_85_; + _zz_86_[11] = _zz_85_; + _zz_86_[10] = _zz_85_; + _zz_86_[9] = _zz_85_; + _zz_86_[8] = _zz_85_; + _zz_86_[7 : 0] = execute_DBusSimplePlugin_rspShifted[7 : 0]; + end + + assign _zz_87_ = (execute_DBusSimplePlugin_rspShifted[15] && (! execute_INSTRUCTION[14])); + always @ (*) begin + _zz_88_[31] = _zz_87_; + _zz_88_[30] = _zz_87_; + _zz_88_[29] = _zz_87_; + _zz_88_[28] = _zz_87_; + _zz_88_[27] = _zz_87_; + _zz_88_[26] = _zz_87_; + _zz_88_[25] = _zz_87_; + _zz_88_[24] = _zz_87_; + _zz_88_[23] = _zz_87_; + _zz_88_[22] = _zz_87_; + _zz_88_[21] = _zz_87_; + _zz_88_[20] = _zz_87_; + _zz_88_[19] = _zz_87_; + _zz_88_[18] = _zz_87_; + _zz_88_[17] = _zz_87_; + _zz_88_[16] = _zz_87_; + _zz_88_[15 : 0] = execute_DBusSimplePlugin_rspShifted[15 : 0]; + end + + always @ (*) begin + case(_zz_172_) + 2'b00 : begin + execute_DBusSimplePlugin_rspFormated = _zz_86_; + end + 2'b01 : begin + execute_DBusSimplePlugin_rspFormated = _zz_88_; + end + default : begin + execute_DBusSimplePlugin_rspFormated = execute_DBusSimplePlugin_rspShifted; + end + endcase + end + + assign _zz_90_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001001000)) == (32'b00000000000000000000000001001000)); + assign _zz_91_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000000100)) == (32'b00000000000000000000000000000100)); + assign _zz_92_ = ((decode_INSTRUCTION & (32'b00010000000100000011000001010000)) == (32'b00000000000100000000000001010000)); + assign _zz_93_ = ((decode_INSTRUCTION & (32'b00000000000000000100000001010000)) == (32'b00000000000000000100000001010000)); + assign _zz_94_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001010000)) == (32'b00000000000000000000000000010000)); + assign _zz_89_ = {({(_zz_224_ == _zz_225_),(_zz_226_ == _zz_227_)} != (2'b00)),{(_zz_94_ != (1'b0)),{(_zz_228_ != (1'b0)),{(_zz_229_ != _zz_230_),{_zz_231_,{_zz_232_,_zz_233_}}}}}}; + assign _zz_60_ = ({((decode_INSTRUCTION & (32'b00000000000000000000000001011111)) == (32'b00000000000000000000000000010111)),{((decode_INSTRUCTION & (32'b00000000000000000000000001111111)) == (32'b00000000000000000000000001101111)),{((decode_INSTRUCTION & (32'b00000000000000000001000001101111)) == (32'b00000000000000000000000000000011)),{((decode_INSTRUCTION & _zz_332_) == (32'b00000000000000000001000001110011)),{(_zz_333_ == _zz_334_),{_zz_335_,{_zz_336_,_zz_337_}}}}}}} != (20'b00000000000000000000)); + assign _zz_95_ = _zz_89_[1 : 0]; + assign _zz_59_ = _zz_95_; + assign _zz_58_ = _zz_178_[0]; + assign _zz_96_ = _zz_89_[5 : 4]; + assign _zz_57_ = _zz_96_; + assign _zz_97_ = _zz_89_[8 : 7]; + assign _zz_56_ = _zz_97_; + assign _zz_55_ = _zz_179_[0]; + assign _zz_98_ = _zz_89_[11 : 10]; + assign _zz_54_ = _zz_98_; + assign _zz_53_ = _zz_180_[0]; + assign _zz_52_ = _zz_181_[0]; + assign _zz_99_ = _zz_89_[15 : 14]; + assign _zz_51_ = _zz_99_; + assign _zz_100_ = _zz_89_[17 : 16]; + assign _zz_50_ = _zz_100_; + assign _zz_49_ = _zz_182_[0]; + assign _zz_101_ = _zz_89_[22 : 21]; + assign _zz_48_ = _zz_101_; + assign _zz_47_ = _zz_183_[0]; + assign _zz_46_ = _zz_184_[0]; + assign _zz_45_ = _zz_185_[0]; + assign _zz_44_ = _zz_186_[0]; + assign decodeExceptionPort_valid = ((decode_arbitration_isValid && decode_INSTRUCTION_READY) && (! decode_LEGAL_INSTRUCTION)); + assign decodeExceptionPort_payload_code = (4'b0010); + assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION; + assign execute_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION[19 : 15]; + assign execute_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION[24 : 20]; + assign _zz_102_ = (! execute_arbitration_isStuck); + assign execute_RegFilePlugin_rs1Data = _zz_153_; + assign execute_RegFilePlugin_rs2Data = _zz_154_; + assign _zz_43_ = execute_RegFilePlugin_rs1Data; + assign _zz_42_ = execute_RegFilePlugin_rs2Data; + assign execute_RegFilePlugin_regFileWrite_valid = (execute_REGFILE_WRITE_VALID && execute_arbitration_isFiring); + assign execute_RegFilePlugin_regFileWrite_payload_address = execute_INSTRUCTION[11 : 7]; + assign execute_RegFilePlugin_regFileWrite_payload_data = _zz_61_; + always @ (*) begin + case(execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : begin + execute_IntAluPlugin_bitwise = (execute_SRC1 & execute_SRC2); + end + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : begin + execute_IntAluPlugin_bitwise = (execute_SRC1 | execute_SRC2); + end + default : begin + execute_IntAluPlugin_bitwise = (execute_SRC1 ^ execute_SRC2); + end + endcase + end + + always @ (*) begin + case(execute_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_BITWISE : begin + _zz_103_ = execute_IntAluPlugin_bitwise; + end + `AluCtrlEnum_defaultEncoding_SLT_SLTU : begin + _zz_103_ = {31'd0, _zz_187_}; + end + default : begin + _zz_103_ = execute_SRC_ADD_SUB; + end + endcase + end + + assign _zz_39_ = _zz_103_; + assign _zz_37_ = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS)); + always @ (*) begin + case(execute_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : begin + _zz_104_ = execute_RS1; + end + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : begin + _zz_104_ = {29'd0, _zz_188_}; + end + `Src1CtrlEnum_defaultEncoding_IMU : begin + _zz_104_ = {execute_INSTRUCTION[31 : 12],(12'b000000000000)}; + end + default : begin + _zz_104_ = {27'd0, _zz_189_}; + end + endcase + end + + assign _zz_36_ = _zz_104_; + assign _zz_105_ = _zz_190_[11]; + always @ (*) begin + _zz_106_[19] = _zz_105_; + _zz_106_[18] = _zz_105_; + _zz_106_[17] = _zz_105_; + _zz_106_[16] = _zz_105_; + _zz_106_[15] = _zz_105_; + _zz_106_[14] = _zz_105_; + _zz_106_[13] = _zz_105_; + _zz_106_[12] = _zz_105_; + _zz_106_[11] = _zz_105_; + _zz_106_[10] = _zz_105_; + _zz_106_[9] = _zz_105_; + _zz_106_[8] = _zz_105_; + _zz_106_[7] = _zz_105_; + _zz_106_[6] = _zz_105_; + _zz_106_[5] = _zz_105_; + _zz_106_[4] = _zz_105_; + _zz_106_[3] = _zz_105_; + _zz_106_[2] = _zz_105_; + _zz_106_[1] = _zz_105_; + _zz_106_[0] = _zz_105_; + end + + assign _zz_107_ = _zz_191_[11]; + always @ (*) begin + _zz_108_[19] = _zz_107_; + _zz_108_[18] = _zz_107_; + _zz_108_[17] = _zz_107_; + _zz_108_[16] = _zz_107_; + _zz_108_[15] = _zz_107_; + _zz_108_[14] = _zz_107_; + _zz_108_[13] = _zz_107_; + _zz_108_[12] = _zz_107_; + _zz_108_[11] = _zz_107_; + _zz_108_[10] = _zz_107_; + _zz_108_[9] = _zz_107_; + _zz_108_[8] = _zz_107_; + _zz_108_[7] = _zz_107_; + _zz_108_[6] = _zz_107_; + _zz_108_[5] = _zz_107_; + _zz_108_[4] = _zz_107_; + _zz_108_[3] = _zz_107_; + _zz_108_[2] = _zz_107_; + _zz_108_[1] = _zz_107_; + _zz_108_[0] = _zz_107_; + end + + always @ (*) begin + case(execute_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : begin + _zz_109_ = execute_RS2; + end + `Src2CtrlEnum_defaultEncoding_IMI : begin + _zz_109_ = {_zz_106_,execute_INSTRUCTION[31 : 20]}; + end + `Src2CtrlEnum_defaultEncoding_IMS : begin + _zz_109_ = {_zz_108_,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; + end + default : begin + _zz_109_ = execute_PC; + end + endcase + end + + assign _zz_34_ = _zz_109_; + always @ (*) begin + execute_SrcPlugin_addSub = _zz_192_; + if(execute_SRC2_FORCE_ZERO)begin + execute_SrcPlugin_addSub = execute_SRC1; + end + end + + assign execute_SrcPlugin_less = ((execute_SRC1[31] == execute_SRC2[31]) ? execute_SrcPlugin_addSub[31] : (execute_SRC_LESS_UNSIGNED ? execute_SRC2[31] : execute_SRC1[31])); + assign _zz_32_ = execute_SrcPlugin_addSub; + assign _zz_31_ = execute_SrcPlugin_addSub; + assign _zz_30_ = execute_SrcPlugin_less; + assign execute_LightShifterPlugin_isShift = (execute_SHIFT_CTRL != `ShiftCtrlEnum_defaultEncoding_DISABLE_1); + assign execute_LightShifterPlugin_amplitude = (execute_LightShifterPlugin_isActive ? execute_LightShifterPlugin_amplitudeReg : execute_SRC2[4 : 0]); + assign execute_LightShifterPlugin_shiftInput = (execute_LightShifterPlugin_isActive ? execute_LightShifterPlugin_shiftReg : execute_SRC1); + assign execute_LightShifterPlugin_done = (execute_LightShifterPlugin_amplitude[4 : 1] == (4'b0000)); + always @ (*) begin + case(execute_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_SLL_1 : begin + _zz_110_ = (execute_LightShifterPlugin_shiftInput <<< 1); + end + default : begin + _zz_110_ = _zz_199_; + end + endcase + end + + assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2); + assign _zz_111_ = execute_INSTRUCTION[14 : 12]; + always @ (*) begin + if((_zz_111_ == (3'b000))) begin + _zz_112_ = execute_BranchPlugin_eq; + end else if((_zz_111_ == (3'b001))) begin + _zz_112_ = (! execute_BranchPlugin_eq); + end else if((((_zz_111_ & (3'b101)) == (3'b101)))) begin + _zz_112_ = (! execute_SRC_LESS); + end else begin + _zz_112_ = execute_SRC_LESS; + end + end + + always @ (*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : begin + _zz_113_ = 1'b0; + end + `BranchCtrlEnum_defaultEncoding_JAL : begin + _zz_113_ = 1'b1; + end + `BranchCtrlEnum_defaultEncoding_JALR : begin + _zz_113_ = 1'b1; + end + default : begin + _zz_113_ = _zz_112_; + end + endcase + end + + assign _zz_28_ = _zz_113_; + assign execute_BranchPlugin_branch_src1 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JALR) ? execute_RS1 : execute_PC); + assign _zz_114_ = _zz_201_[19]; + always @ (*) begin + _zz_115_[10] = _zz_114_; + _zz_115_[9] = _zz_114_; + _zz_115_[8] = _zz_114_; + _zz_115_[7] = _zz_114_; + _zz_115_[6] = _zz_114_; + _zz_115_[5] = _zz_114_; + _zz_115_[4] = _zz_114_; + _zz_115_[3] = _zz_114_; + _zz_115_[2] = _zz_114_; + _zz_115_[1] = _zz_114_; + _zz_115_[0] = _zz_114_; + end + + assign _zz_116_ = _zz_202_[11]; + always @ (*) begin + _zz_117_[19] = _zz_116_; + _zz_117_[18] = _zz_116_; + _zz_117_[17] = _zz_116_; + _zz_117_[16] = _zz_116_; + _zz_117_[15] = _zz_116_; + _zz_117_[14] = _zz_116_; + _zz_117_[13] = _zz_116_; + _zz_117_[12] = _zz_116_; + _zz_117_[11] = _zz_116_; + _zz_117_[10] = _zz_116_; + _zz_117_[9] = _zz_116_; + _zz_117_[8] = _zz_116_; + _zz_117_[7] = _zz_116_; + _zz_117_[6] = _zz_116_; + _zz_117_[5] = _zz_116_; + _zz_117_[4] = _zz_116_; + _zz_117_[3] = _zz_116_; + _zz_117_[2] = _zz_116_; + _zz_117_[1] = _zz_116_; + _zz_117_[0] = _zz_116_; + end + + assign _zz_118_ = _zz_203_[11]; + always @ (*) begin + _zz_119_[18] = _zz_118_; + _zz_119_[17] = _zz_118_; + _zz_119_[16] = _zz_118_; + _zz_119_[15] = _zz_118_; + _zz_119_[14] = _zz_118_; + _zz_119_[13] = _zz_118_; + _zz_119_[12] = _zz_118_; + _zz_119_[11] = _zz_118_; + _zz_119_[10] = _zz_118_; + _zz_119_[9] = _zz_118_; + _zz_119_[8] = _zz_118_; + _zz_119_[7] = _zz_118_; + _zz_119_[6] = _zz_118_; + _zz_119_[5] = _zz_118_; + _zz_119_[4] = _zz_118_; + _zz_119_[3] = _zz_118_; + _zz_119_[2] = _zz_118_; + _zz_119_[1] = _zz_118_; + _zz_119_[0] = _zz_118_; + end + + always @ (*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_JAL : begin + _zz_120_ = {{_zz_115_,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; + end + `BranchCtrlEnum_defaultEncoding_JALR : begin + _zz_120_ = {_zz_117_,execute_INSTRUCTION[31 : 20]}; + end + default : begin + _zz_120_ = {{_zz_119_,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; + end + endcase + end + + assign execute_BranchPlugin_branch_src2 = _zz_120_; + assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2); + assign _zz_26_ = {execute_BranchPlugin_branchAdder[31 : 1],(1'b0)}; + assign BranchPlugin_jumpInterface_valid = ((execute_arbitration_isValid && (! execute_arbitration_isStuckByOthers)) && execute_BRANCH_DO); + assign BranchPlugin_jumpInterface_payload = execute_BRANCH_CALC; + always @ (*) begin + BranchPlugin_branchExceptionPort_valid = ((execute_arbitration_isValid && execute_BRANCH_DO) && BranchPlugin_jumpInterface_payload[1]); + if(1'b0)begin + BranchPlugin_branchExceptionPort_valid = 1'b0; + end + end + + assign BranchPlugin_branchExceptionPort_payload_code = (4'b0000); + assign BranchPlugin_branchExceptionPort_payload_badAddr = BranchPlugin_jumpInterface_payload; + always @ (*) begin + CsrPlugin_privilege = (2'b11); + if(CsrPlugin_forceMachineWire)begin + CsrPlugin_privilege = (2'b11); + end + end + + assign CsrPlugin_misa_base = (2'b01); + assign CsrPlugin_misa_extensions = (26'b00000000000000000000000000); + assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = (2'b11); + assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege); + assign _zz_121_ = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; + assign _zz_122_ = _zz_204_[0]; + assign _zz_123_ = {CsrPlugin_selfException_valid,{BranchPlugin_branchExceptionPort_valid,DBusSimplePlugin_memoryExceptionPort_valid}}; + assign _zz_124_ = (_zz_123_ & (~ _zz_206_)); + assign _zz_125_ = _zz_124_[1]; + assign _zz_126_ = _zz_124_[2]; + assign _zz_127_ = {_zz_126_,_zz_125_}; + always @ (*) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; + if(_zz_160_)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b1; + end + if(decode_arbitration_isFlushed)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b0; + end + end + + assign CsrPlugin_exceptionPendings_0 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; + assign CsrPlugin_exceptionPendings_1 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; + always @ (*) begin + CsrPlugin_interrupt = 1'b0; + CsrPlugin_interruptCode = (4'bxxxx); + CsrPlugin_interruptTargetPrivilege = (2'bxx); + if((CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < (2'b11))))begin + if((((CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE) && 1'b1) && (! 1'b0)))begin + CsrPlugin_interrupt = 1'b1; + CsrPlugin_interruptCode = (4'b0111); + CsrPlugin_interruptTargetPrivilege = (2'b11); + end + if((((CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE) && 1'b1) && (! 1'b0)))begin + CsrPlugin_interrupt = 1'b1; + CsrPlugin_interruptCode = (4'b0011); + CsrPlugin_interruptTargetPrivilege = (2'b11); + end + if((((CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE) && 1'b1) && (! 1'b0)))begin + CsrPlugin_interrupt = 1'b1; + CsrPlugin_interruptCode = (4'b1011); + CsrPlugin_interruptTargetPrivilege = (2'b11); + end + end + if((! CsrPlugin_allowInterrupts))begin + CsrPlugin_interrupt = 1'b0; + end + end + + assign CsrPlugin_exception = (CsrPlugin_exceptionPortCtrl_exceptionValids_execute && CsrPlugin_allowException); + assign CsrPlugin_lastStageWasWfi = 1'b0; + always @ (*) begin + CsrPlugin_pipelineLiberator_done = ((! (execute_arbitration_isValid != (1'b0))) && IBusCachedPlugin_pcValids_1); + if((CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute != (1'b0)))begin + CsrPlugin_pipelineLiberator_done = 1'b0; + end + if(CsrPlugin_hadException)begin + CsrPlugin_pipelineLiberator_done = 1'b0; + end + end + + assign CsrPlugin_interruptJump = (CsrPlugin_interrupt && CsrPlugin_pipelineLiberator_done); + always @ (*) begin + CsrPlugin_targetPrivilege = CsrPlugin_interruptTargetPrivilege; + if(CsrPlugin_hadException)begin + CsrPlugin_targetPrivilege = CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; + end + end + + always @ (*) begin + CsrPlugin_trapCause = CsrPlugin_interruptCode; + if(CsrPlugin_hadException)begin + CsrPlugin_trapCause = CsrPlugin_exceptionPortCtrl_exceptionContext_code; + end + end + + always @ (*) begin + CsrPlugin_xtvec_mode = (2'bxx); + CsrPlugin_xtvec_base = (30'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx); + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_xtvec_mode = CsrPlugin_mtvec_mode; + CsrPlugin_xtvec_base = CsrPlugin_mtvec_base; + end + default : begin + end + endcase + end + + assign contextSwitching = CsrPlugin_jumpInterface_valid; + assign _zz_24_ = (! (((decode_INSTRUCTION[14 : 13] == (2'b01)) && (decode_INSTRUCTION[19 : 15] == (5'b00000))) || ((decode_INSTRUCTION[14 : 13] == (2'b11)) && (decode_INSTRUCTION[19 : 15] == (5'b00000))))); + assign _zz_23_ = (decode_INSTRUCTION[13 : 7] != (7'b0100000)); + assign execute_CsrPlugin_inWfi = 1'b0; + assign execute_CsrPlugin_blockedBySideEffects = 1'b0; + always @ (*) begin + execute_CsrPlugin_illegalAccess = 1'b1; + execute_CsrPlugin_readData = (32'b00000000000000000000000000000000); + case(execute_CsrPlugin_csrAddress) + 12'b101111000000 : begin + execute_CsrPlugin_illegalAccess = 1'b0; + execute_CsrPlugin_readData[31 : 0] = _zz_128_; + end + 12'b001100000000 : begin + execute_CsrPlugin_illegalAccess = 1'b0; + execute_CsrPlugin_readData[12 : 11] = CsrPlugin_mstatus_MPP; + execute_CsrPlugin_readData[7 : 7] = CsrPlugin_mstatus_MPIE; + execute_CsrPlugin_readData[3 : 3] = CsrPlugin_mstatus_MIE; + end + 12'b001101000001 : begin + execute_CsrPlugin_illegalAccess = 1'b0; + execute_CsrPlugin_readData[31 : 0] = CsrPlugin_mepc; + end + 12'b001100000101 : begin + if(execute_CSR_WRITE_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + 12'b001101000100 : begin + execute_CsrPlugin_illegalAccess = 1'b0; + execute_CsrPlugin_readData[11 : 11] = CsrPlugin_mip_MEIP; + execute_CsrPlugin_readData[7 : 7] = CsrPlugin_mip_MTIP; + execute_CsrPlugin_readData[3 : 3] = CsrPlugin_mip_MSIP; + end + 12'b001101000011 : begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + execute_CsrPlugin_readData[31 : 0] = CsrPlugin_mtval; + end + 12'b111111000000 : begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + execute_CsrPlugin_readData[31 : 0] = _zz_129_; + end + 12'b001101000000 : begin + execute_CsrPlugin_illegalAccess = 1'b0; + execute_CsrPlugin_readData[31 : 0] = CsrPlugin_mscratch; + end + 12'b001100000100 : begin + execute_CsrPlugin_illegalAccess = 1'b0; + execute_CsrPlugin_readData[11 : 11] = CsrPlugin_mie_MEIE; + execute_CsrPlugin_readData[7 : 7] = CsrPlugin_mie_MTIE; + execute_CsrPlugin_readData[3 : 3] = CsrPlugin_mie_MSIE; + end + 12'b001101000010 : begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + execute_CsrPlugin_readData[31 : 31] = CsrPlugin_mcause_interrupt; + execute_CsrPlugin_readData[3 : 0] = CsrPlugin_mcause_exceptionCode; + end + default : begin + end + endcase + if((CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]))begin + execute_CsrPlugin_illegalAccess = 1'b1; + end + if(((! execute_arbitration_isValid) || (! execute_IS_CSR)))begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + + always @ (*) begin + execute_CsrPlugin_illegalInstruction = 1'b0; + if((execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)))begin + if((CsrPlugin_privilege < execute_INSTRUCTION[29 : 28]))begin + execute_CsrPlugin_illegalInstruction = 1'b1; + end + end + end + + always @ (*) begin + CsrPlugin_selfException_valid = 1'b0; + CsrPlugin_selfException_payload_code = (4'bxxxx); + if((execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)))begin + CsrPlugin_selfException_valid = 1'b1; + case(CsrPlugin_privilege) + 2'b00 : begin + CsrPlugin_selfException_payload_code = (4'b1000); + end + default : begin + CsrPlugin_selfException_payload_code = (4'b1011); + end + endcase + end + if((execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_EBREAK)))begin + CsrPlugin_selfException_valid = 1'b1; + CsrPlugin_selfException_payload_code = (4'b0011); + end + end + + assign CsrPlugin_selfException_payload_badAddr = execute_INSTRUCTION; + assign execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); + assign execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); + assign execute_CsrPlugin_writeEnable = ((execute_CsrPlugin_writeInstruction && (! execute_CsrPlugin_blockedBySideEffects)) && (! execute_arbitration_isStuckByOthers)); + assign execute_CsrPlugin_readEnable = ((execute_CsrPlugin_readInstruction && (! execute_CsrPlugin_blockedBySideEffects)) && (! execute_arbitration_isStuckByOthers)); + assign execute_CsrPlugin_readToWriteData = execute_CsrPlugin_readData; + always @ (*) begin + case(_zz_173_) + 1'b0 : begin + execute_CsrPlugin_writeData = execute_SRC1; + end + default : begin + execute_CsrPlugin_writeData = (execute_INSTRUCTION[12] ? (execute_CsrPlugin_readToWriteData & (~ execute_SRC1)) : (execute_CsrPlugin_readToWriteData | execute_SRC1)); + end + endcase + end + + assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20]; + assign _zz_129_ = (_zz_128_ & externalInterruptArray_regNext); + assign externalInterrupt = (_zz_129_ != (32'b00000000000000000000000000000000)); + always @ (*) begin + debug_bus_cmd_ready = 1'b1; + IBusCachedPlugin_injectionPort_valid = 1'b0; + if(debug_bus_cmd_valid)begin + case(_zz_169_) + 6'b000000 : begin + end + 6'b000001 : begin + if(debug_bus_cmd_payload_wr)begin + IBusCachedPlugin_injectionPort_valid = 1'b1; + debug_bus_cmd_ready = IBusCachedPlugin_injectionPort_ready; + end + end + 6'b010000 : begin + end + 6'b010001 : begin + end + 6'b010010 : begin + end + 6'b010011 : begin + end + default : begin + end + endcase + end + end + + always @ (*) begin + debug_bus_rsp_data = DebugPlugin_busReadDataReg; + if((! _zz_130_))begin + debug_bus_rsp_data[0] = DebugPlugin_resetIt; + debug_bus_rsp_data[1] = DebugPlugin_haltIt; + debug_bus_rsp_data[2] = DebugPlugin_isPipBusy; + debug_bus_rsp_data[3] = DebugPlugin_haltedByBreak; + debug_bus_rsp_data[4] = DebugPlugin_stepIt; + end + end + + assign IBusCachedPlugin_injectionPort_payload = debug_bus_cmd_payload_data; + assign _zz_22_ = ((! DebugPlugin_haltIt) && (decode_IS_EBREAK || ((((1'b0 || (DebugPlugin_hardwareBreakpoints_0_valid && (DebugPlugin_hardwareBreakpoints_0_pc == _zz_211_))) || (DebugPlugin_hardwareBreakpoints_1_valid && (DebugPlugin_hardwareBreakpoints_1_pc == _zz_212_))) || (DebugPlugin_hardwareBreakpoints_2_valid && (DebugPlugin_hardwareBreakpoints_2_pc == _zz_213_))) || (DebugPlugin_hardwareBreakpoints_3_valid && (DebugPlugin_hardwareBreakpoints_3_pc == _zz_214_))))); + assign debug_resetOut = DebugPlugin_resetIt_regNext; + assign _zz_21_ = decode_ALU_BITWISE_CTRL; + assign _zz_19_ = _zz_50_; + assign _zz_40_ = decode_to_execute_ALU_BITWISE_CTRL; + assign _zz_18_ = decode_ENV_CTRL; + assign _zz_16_ = _zz_54_; + assign _zz_25_ = decode_to_execute_ENV_CTRL; + assign _zz_15_ = decode_SHIFT_CTRL; + assign _zz_13_ = _zz_48_; + assign _zz_29_ = decode_to_execute_SHIFT_CTRL; + assign _zz_12_ = decode_BRANCH_CTRL; + assign _zz_10_ = _zz_59_; + assign _zz_27_ = decode_to_execute_BRANCH_CTRL; + assign _zz_9_ = decode_SRC1_CTRL; + assign _zz_7_ = _zz_51_; + assign _zz_35_ = decode_to_execute_SRC1_CTRL; + assign _zz_6_ = decode_SRC2_CTRL; + assign _zz_4_ = _zz_57_; + assign _zz_33_ = decode_to_execute_SRC2_CTRL; + assign _zz_3_ = decode_ALU_CTRL; + assign _zz_1_ = _zz_56_; + assign _zz_38_ = decode_to_execute_ALU_CTRL; + assign decode_arbitration_isFlushed = ({execute_arbitration_flushAll,decode_arbitration_flushAll} != (2'b00)); + assign execute_arbitration_isFlushed = (execute_arbitration_flushAll != (1'b0)); + assign decode_arbitration_isStuckByOthers = (decode_arbitration_haltByOther || (1'b0 || execute_arbitration_isStuck)); + assign decode_arbitration_isStuck = (decode_arbitration_haltItself || decode_arbitration_isStuckByOthers); + assign decode_arbitration_isMoving = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)); + assign decode_arbitration_isFiring = ((decode_arbitration_isValid && (! decode_arbitration_isStuck)) && (! decode_arbitration_removeIt)); + assign execute_arbitration_isStuckByOthers = (execute_arbitration_haltByOther || 1'b0); + assign execute_arbitration_isStuck = (execute_arbitration_haltItself || execute_arbitration_isStuckByOthers); + assign execute_arbitration_isMoving = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)); + assign execute_arbitration_isFiring = ((execute_arbitration_isValid && (! execute_arbitration_isStuck)) && (! execute_arbitration_removeIt)); + assign iBusWishbone_ADR = {_zz_221_,_zz_132_}; + assign iBusWishbone_CTI = ((_zz_132_ == (3'b111)) ? (3'b111) : (3'b010)); + assign iBusWishbone_BTE = (2'b00); + assign iBusWishbone_SEL = (4'b1111); + assign iBusWishbone_WE = 1'b0; + assign iBusWishbone_DAT_MOSI = (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx); + always @ (*) begin + iBusWishbone_CYC = 1'b0; + iBusWishbone_STB = 1'b0; + if(_zz_170_)begin + iBusWishbone_CYC = 1'b1; + iBusWishbone_STB = 1'b1; + end + end + + assign iBus_cmd_ready = (iBus_cmd_valid && iBusWishbone_ACK); + assign iBus_rsp_valid = _zz_133_; + assign iBus_rsp_payload_data = iBusWishbone_DAT_MISO_regNext; + assign iBus_rsp_payload_error = 1'b0; + assign dBus_cmd_halfPipe_valid = dBus_cmd_halfPipe_regs_valid; + assign dBus_cmd_halfPipe_payload_wr = dBus_cmd_halfPipe_regs_payload_wr; + assign dBus_cmd_halfPipe_payload_address = dBus_cmd_halfPipe_regs_payload_address; + assign dBus_cmd_halfPipe_payload_data = dBus_cmd_halfPipe_regs_payload_data; + assign dBus_cmd_halfPipe_payload_size = dBus_cmd_halfPipe_regs_payload_size; + assign dBus_cmd_ready = dBus_cmd_halfPipe_regs_ready; + assign dBusWishbone_ADR = (dBus_cmd_halfPipe_payload_address >>> 2); + assign dBusWishbone_CTI = (3'b000); + assign dBusWishbone_BTE = (2'b00); + always @ (*) begin + case(dBus_cmd_halfPipe_payload_size) + 2'b00 : begin + _zz_134_ = (4'b0001); + end + 2'b01 : begin + _zz_134_ = (4'b0011); + end + default : begin + _zz_134_ = (4'b1111); + end + endcase + end + + always @ (*) begin + dBusWishbone_SEL = _zz_222_[3:0]; + if((! dBus_cmd_halfPipe_payload_wr))begin + dBusWishbone_SEL = (4'b1111); + end + end + + assign dBusWishbone_WE = dBus_cmd_halfPipe_payload_wr; + assign dBusWishbone_DAT_MOSI = dBus_cmd_halfPipe_payload_data; + assign dBus_cmd_halfPipe_ready = (dBus_cmd_halfPipe_valid && dBusWishbone_ACK); + assign dBusWishbone_CYC = dBus_cmd_halfPipe_valid; + assign dBusWishbone_STB = dBus_cmd_halfPipe_valid; + assign dBus_rsp_ready = ((dBus_cmd_halfPipe_valid && (! dBusWishbone_WE)) && dBusWishbone_ACK); + assign dBus_rsp_data = dBusWishbone_DAT_MISO; + assign dBus_rsp_error = 1'b0; + always @ (posedge clk) begin + if(reset) begin + IBusCachedPlugin_fetchPc_pcReg <= externalResetVector; + IBusCachedPlugin_fetchPc_inc <= 1'b0; + _zz_77_ <= 1'b0; + _zz_82_ <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; + IBusCachedPlugin_injector_decodeRemoved <= 1'b0; + execute_DBusSimplePlugin_cmdSent <= 1'b0; + execute_LightShifterPlugin_isActive <= 1'b0; + CsrPlugin_mstatus_MIE <= 1'b0; + CsrPlugin_mstatus_MPIE <= 1'b0; + CsrPlugin_mstatus_MPP <= (2'b11); + CsrPlugin_mie_MEIE <= 1'b0; + CsrPlugin_mie_MTIE <= 1'b0; + CsrPlugin_mie_MSIE <= 1'b0; + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= 1'b0; + CsrPlugin_hadException <= 1'b0; + _zz_128_ <= (32'b00000000000000000000000000000000); + execute_arbitration_isValid <= 1'b0; + _zz_131_ <= (3'b000); + _zz_132_ <= (3'b000); + _zz_133_ <= 1'b0; + dBus_cmd_halfPipe_regs_valid <= 1'b0; + dBus_cmd_halfPipe_regs_ready <= 1'b1; + end else begin + if(IBusCachedPlugin_fetchPc_propagatePc)begin + IBusCachedPlugin_fetchPc_inc <= 1'b0; + end + if(IBusCachedPlugin_jump_pcLoad_valid)begin + IBusCachedPlugin_fetchPc_inc <= 1'b0; + end + if(_zz_168_)begin + IBusCachedPlugin_fetchPc_inc <= 1'b1; + end + if(IBusCachedPlugin_fetchPc_samplePcNext)begin + IBusCachedPlugin_fetchPc_pcReg <= IBusCachedPlugin_fetchPc_pc; + end + _zz_77_ <= 1'b1; + if((IBusCachedPlugin_jump_pcLoad_valid || IBusCachedPlugin_fetcherflushIt))begin + _zz_82_ <= 1'b0; + end + if(_zz_80_)begin + _zz_82_ <= IBusCachedPlugin_iBusRsp_stages_0_output_valid; + end + if((IBusCachedPlugin_jump_pcLoad_valid || IBusCachedPlugin_fetcherflushIt))begin + IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; + end + if((! (! IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready)))begin + IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b1; + end + if((IBusCachedPlugin_jump_pcLoad_valid || IBusCachedPlugin_fetcherflushIt))begin + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; + end + if((! execute_arbitration_isStuck))begin + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= IBusCachedPlugin_injector_nextPcCalc_valids_0; + end + if((IBusCachedPlugin_jump_pcLoad_valid || IBusCachedPlugin_fetcherflushIt))begin + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; + end + if(decode_arbitration_removeIt)begin + IBusCachedPlugin_injector_decodeRemoved <= 1'b1; + end + if((IBusCachedPlugin_jump_pcLoad_valid || IBusCachedPlugin_fetcherflushIt))begin + IBusCachedPlugin_injector_decodeRemoved <= 1'b0; + end + if((dBus_cmd_valid && dBus_cmd_ready))begin + execute_DBusSimplePlugin_cmdSent <= 1'b1; + end + if((! execute_arbitration_isStuck))begin + execute_DBusSimplePlugin_cmdSent <= 1'b0; + end + if(_zz_158_)begin + if(_zz_159_)begin + execute_LightShifterPlugin_isActive <= 1'b1; + if(execute_LightShifterPlugin_done)begin + execute_LightShifterPlugin_isActive <= 1'b0; + end + end + end + if(execute_arbitration_removeIt)begin + execute_LightShifterPlugin_isActive <= 1'b0; + end + if((! decode_arbitration_isStuck))begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; + end else begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= CsrPlugin_exceptionPortCtrl_exceptionValids_decode; + end + if((! execute_arbitration_isStuck))begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= (CsrPlugin_exceptionPortCtrl_exceptionValids_decode && (! decode_arbitration_isStuck)); + end else begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= 1'b0; + end + CsrPlugin_hadException <= CsrPlugin_exception; + if(_zz_162_)begin + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_mstatus_MIE <= 1'b0; + CsrPlugin_mstatus_MPIE <= CsrPlugin_mstatus_MIE; + CsrPlugin_mstatus_MPP <= CsrPlugin_privilege; + end + default : begin + end + endcase + end + if(_zz_163_)begin + case(_zz_164_) + 2'b11 : begin + CsrPlugin_mstatus_MPP <= (2'b00); + CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE; + CsrPlugin_mstatus_MPIE <= 1'b1; + end + default : begin + end + endcase + end + if(((! execute_arbitration_isStuck) || execute_arbitration_removeIt))begin + execute_arbitration_isValid <= 1'b0; + end + if(((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)))begin + execute_arbitration_isValid <= decode_arbitration_isValid; + end + case(_zz_131_) + 3'b000 : begin + if(IBusCachedPlugin_injectionPort_valid)begin + _zz_131_ <= (3'b001); + end + end + 3'b001 : begin + _zz_131_ <= (3'b010); + end + 3'b010 : begin + _zz_131_ <= (3'b011); + end + 3'b011 : begin + if((! decode_arbitration_isStuck))begin + _zz_131_ <= (3'b100); + end + end + 3'b100 : begin + _zz_131_ <= (3'b000); + end + default : begin + end + endcase + case(execute_CsrPlugin_csrAddress) + 12'b101111000000 : begin + if(execute_CsrPlugin_writeEnable)begin + _zz_128_ <= execute_CsrPlugin_writeData[31 : 0]; + end + end + 12'b001100000000 : begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11]; + CsrPlugin_mstatus_MPIE <= _zz_215_[0]; + CsrPlugin_mstatus_MIE <= _zz_216_[0]; + end + end + 12'b001101000001 : begin + end + 12'b001100000101 : begin + end + 12'b001101000100 : begin + end + 12'b001101000011 : begin + end + 12'b111111000000 : begin + end + 12'b001101000000 : begin + end + 12'b001100000100 : begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mie_MEIE <= _zz_218_[0]; + CsrPlugin_mie_MTIE <= _zz_219_[0]; + CsrPlugin_mie_MSIE <= _zz_220_[0]; + end + end + 12'b001101000010 : begin + end + default : begin + end + endcase + if(_zz_170_)begin + if(iBusWishbone_ACK)begin + _zz_132_ <= (_zz_132_ + (3'b001)); + end + end + _zz_133_ <= (iBusWishbone_CYC && iBusWishbone_ACK); + if(_zz_171_)begin + dBus_cmd_halfPipe_regs_valid <= dBus_cmd_valid; + dBus_cmd_halfPipe_regs_ready <= (! dBus_cmd_valid); + end else begin + dBus_cmd_halfPipe_regs_valid <= (! dBus_cmd_halfPipe_ready); + dBus_cmd_halfPipe_regs_ready <= dBus_cmd_halfPipe_ready; + end + end + end + + always @ (posedge clk) begin + if(IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready)begin + IBusCachedPlugin_s1_tightlyCoupledHit <= IBusCachedPlugin_s0_tightlyCoupledHit; + end + if((! execute_arbitration_isStuckByOthers))begin + execute_LightShifterPlugin_shiftReg <= _zz_61_; + end + if(_zz_158_)begin + if(_zz_159_)begin + execute_LightShifterPlugin_amplitudeReg <= (execute_LightShifterPlugin_amplitude - (5'b00001)); + end + end + CsrPlugin_mip_MEIP <= externalInterrupt; + CsrPlugin_mip_MTIP <= timerInterrupt; + CsrPlugin_mip_MSIP <= softwareInterrupt; + CsrPlugin_mcycle <= (CsrPlugin_mcycle + (64'b0000000000000000000000000000000000000000000000000000000000000001)); + if(execute_arbitration_isFiring)begin + CsrPlugin_minstret <= (CsrPlugin_minstret + (64'b0000000000000000000000000000000000000000000000000000000000000001)); + end + if(_zz_160_)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_122_ ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_122_ ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); + end + if(_zz_161_)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= _zz_156_; + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= _zz_157_; + end + if(_zz_162_)begin + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException); + CsrPlugin_mcause_exceptionCode <= CsrPlugin_trapCause; + CsrPlugin_mepc <= execute_PC; + if(CsrPlugin_hadException)begin + CsrPlugin_mtval <= CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; + end + end + default : begin + end + endcase + end + externalInterruptArray_regNext <= externalInterruptArray; + if((! execute_arbitration_isStuck))begin + decode_to_execute_INSTRUCTION <= decode_INSTRUCTION; + end + if(((! execute_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_execute)))begin + decode_to_execute_PC <= decode_PC; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_FORMAL_PC_NEXT <= _zz_68_; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_ALU_BITWISE_CTRL <= _zz_20_; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_CSR_READ_OPCODE <= decode_CSR_READ_OPCODE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_MEMORY_ENABLE <= decode_MEMORY_ENABLE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_ENV_CTRL <= _zz_17_; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC_USE_SUB_LESS <= decode_SRC_USE_SUB_LESS; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SHIFT_CTRL <= _zz_14_; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_MEMORY_STORE <= decode_MEMORY_STORE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_BRANCH_CTRL <= _zz_11_; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_CSR <= decode_IS_CSR; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC2_FORCE_ZERO <= decode_SRC2_FORCE_ZERO; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_CSR_WRITE_OPCODE <= decode_CSR_WRITE_OPCODE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC1_CTRL <= _zz_8_; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC2_CTRL <= _zz_5_; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_DO_EBREAK <= decode_DO_EBREAK; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_ALU_CTRL <= _zz_2_; + end + case(execute_CsrPlugin_csrAddress) + 12'b101111000000 : begin + end + 12'b001100000000 : begin + end + 12'b001101000001 : begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mepc <= execute_CsrPlugin_writeData[31 : 0]; + end + end + 12'b001100000101 : begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mtvec_base <= execute_CsrPlugin_writeData[31 : 2]; + CsrPlugin_mtvec_mode <= execute_CsrPlugin_writeData[1 : 0]; + end + end + 12'b001101000100 : begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mip_MSIP <= _zz_217_[0]; + end + end + 12'b001101000011 : begin + end + 12'b111111000000 : begin + end + 12'b001101000000 : begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mscratch <= execute_CsrPlugin_writeData[31 : 0]; + end + end + 12'b001100000100 : begin + end + 12'b001101000010 : begin + end + default : begin + end + endcase + iBusWishbone_DAT_MISO_regNext <= iBusWishbone_DAT_MISO; + if(_zz_171_)begin + dBus_cmd_halfPipe_regs_payload_wr <= dBus_cmd_payload_wr; + dBus_cmd_halfPipe_regs_payload_address <= dBus_cmd_payload_address; + dBus_cmd_halfPipe_regs_payload_data <= dBus_cmd_payload_data; + dBus_cmd_halfPipe_regs_payload_size <= dBus_cmd_payload_size; + end + end + + always @ (posedge clk) begin + DebugPlugin_firstCycle <= 1'b0; + if(debug_bus_cmd_ready)begin + DebugPlugin_firstCycle <= 1'b1; + end + DebugPlugin_secondCycle <= DebugPlugin_firstCycle; + DebugPlugin_isPipBusy <= (({execute_arbitration_isValid,decode_arbitration_isValid} != (2'b00)) || IBusCachedPlugin_incomingInstruction); + if(execute_arbitration_isValid)begin + DebugPlugin_busReadDataReg <= _zz_61_; + end + _zz_130_ <= debug_bus_cmd_payload_address[2]; + if(debug_bus_cmd_valid)begin + case(_zz_169_) + 6'b000000 : begin + end + 6'b000001 : begin + end + 6'b010000 : begin + if(debug_bus_cmd_payload_wr)begin + DebugPlugin_hardwareBreakpoints_0_pc <= debug_bus_cmd_payload_data[31 : 1]; + end + end + 6'b010001 : begin + if(debug_bus_cmd_payload_wr)begin + DebugPlugin_hardwareBreakpoints_1_pc <= debug_bus_cmd_payload_data[31 : 1]; + end + end + 6'b010010 : begin + if(debug_bus_cmd_payload_wr)begin + DebugPlugin_hardwareBreakpoints_2_pc <= debug_bus_cmd_payload_data[31 : 1]; + end + end + 6'b010011 : begin + if(debug_bus_cmd_payload_wr)begin + DebugPlugin_hardwareBreakpoints_3_pc <= debug_bus_cmd_payload_data[31 : 1]; + end + end + default : begin + end + endcase + end + if(_zz_165_)begin + DebugPlugin_busReadDataReg <= execute_PC; + end + DebugPlugin_resetIt_regNext <= DebugPlugin_resetIt; + end + + always @ (posedge clk) begin + if(debugReset) begin + DebugPlugin_resetIt <= 1'b0; + DebugPlugin_haltIt <= 1'b0; + DebugPlugin_stepIt <= 1'b0; + DebugPlugin_godmode <= 1'b0; + DebugPlugin_haltedByBreak <= 1'b0; + DebugPlugin_hardwareBreakpoints_0_valid <= 1'b0; + DebugPlugin_hardwareBreakpoints_1_valid <= 1'b0; + DebugPlugin_hardwareBreakpoints_2_valid <= 1'b0; + DebugPlugin_hardwareBreakpoints_3_valid <= 1'b0; + end else begin + if((DebugPlugin_haltIt && (! DebugPlugin_isPipBusy)))begin + DebugPlugin_godmode <= 1'b1; + end + if(debug_bus_cmd_valid)begin + case(_zz_169_) + 6'b000000 : begin + if(debug_bus_cmd_payload_wr)begin + DebugPlugin_stepIt <= debug_bus_cmd_payload_data[4]; + if(debug_bus_cmd_payload_data[16])begin + DebugPlugin_resetIt <= 1'b1; + end + if(debug_bus_cmd_payload_data[24])begin + DebugPlugin_resetIt <= 1'b0; + end + if(debug_bus_cmd_payload_data[17])begin + DebugPlugin_haltIt <= 1'b1; + end + if(debug_bus_cmd_payload_data[25])begin + DebugPlugin_haltIt <= 1'b0; + end + if(debug_bus_cmd_payload_data[25])begin + DebugPlugin_haltedByBreak <= 1'b0; + end + if(debug_bus_cmd_payload_data[25])begin + DebugPlugin_godmode <= 1'b0; + end + end + end + 6'b000001 : begin + end + 6'b010000 : begin + if(debug_bus_cmd_payload_wr)begin + DebugPlugin_hardwareBreakpoints_0_valid <= _zz_207_[0]; + end + end + 6'b010001 : begin + if(debug_bus_cmd_payload_wr)begin + DebugPlugin_hardwareBreakpoints_1_valid <= _zz_208_[0]; + end + end + 6'b010010 : begin + if(debug_bus_cmd_payload_wr)begin + DebugPlugin_hardwareBreakpoints_2_valid <= _zz_209_[0]; + end + end + 6'b010011 : begin + if(debug_bus_cmd_payload_wr)begin + DebugPlugin_hardwareBreakpoints_3_valid <= _zz_210_[0]; + end + end + default : begin + end + endcase + end + if(_zz_165_)begin + if(_zz_166_)begin + DebugPlugin_haltIt <= 1'b1; + DebugPlugin_haltedByBreak <= 1'b1; + end + end + if(_zz_167_)begin + if(decode_arbitration_isValid)begin + DebugPlugin_haltIt <= 1'b1; + end + end + end + end + + always @ (posedge clk) begin + IBusCachedPlugin_injectionPort_payload_regNext <= IBusCachedPlugin_injectionPort_payload; + end + +endmodule + diff --git a/hw/rtl/2-stage-2048-cache-debug.v_toplevel_RegFilePlugin_regFile.bin b/hw/rtl/2-stage-2048-cache-debug.v_toplevel_RegFilePlugin_regFile.bin new file mode 100644 index 0000000000000000000000000000000000000000..4c177b2156e519e76ef33fcac7621445a9beb984 GIT binary patch literal 1056 fcmXpozz?|aOB)!BDu9I0XgG|919Dy&Cg}kHTp__h literal 0 HcmV?d00001 diff --git a/hw/rtl/2-stage-2048-cache-debug.yaml b/hw/rtl/2-stage-2048-cache-debug.yaml new file mode 100644 index 0000000..db67c22 --- /dev/null +++ b/hw/rtl/2-stage-2048-cache-debug.yaml @@ -0,0 +1,5 @@ +debug: !!vexriscv.DebugReport {hardwareBreakpointCount: 4} +iBus: !!vexriscv.BusReport + flushInstructions: [4111, 19, 19, 19] + info: !!vexriscv.CacheReport {bytePerLine: 32, size: 2048} + kind: cached diff --git a/hw/rtl/2-stage-2048-cache.v b/hw/rtl/2-stage-2048-cache.v new file mode 100644 index 0000000..d6d5c1a --- /dev/null +++ b/hw/rtl/2-stage-2048-cache.v @@ -0,0 +1,3289 @@ +// Generator : SpinalHDL v1.3.3 git head : 8b8cd335eecbea3b5f1f970f218a982dbdb12d99 +// Date : 25/04/2019, 14:40:23 +// Component : VexRiscv + + +`define EnvCtrlEnum_defaultEncoding_type [1:0] +`define EnvCtrlEnum_defaultEncoding_NONE 2'b00 +`define EnvCtrlEnum_defaultEncoding_XRET 2'b01 +`define EnvCtrlEnum_defaultEncoding_ECALL 2'b10 +`define EnvCtrlEnum_defaultEncoding_EBREAK 2'b11 + +`define Src2CtrlEnum_defaultEncoding_type [1:0] +`define Src2CtrlEnum_defaultEncoding_RS 2'b00 +`define Src2CtrlEnum_defaultEncoding_IMI 2'b01 +`define Src2CtrlEnum_defaultEncoding_IMS 2'b10 +`define Src2CtrlEnum_defaultEncoding_PC 2'b11 + +`define Src1CtrlEnum_defaultEncoding_type [1:0] +`define Src1CtrlEnum_defaultEncoding_RS 2'b00 +`define Src1CtrlEnum_defaultEncoding_IMU 2'b01 +`define Src1CtrlEnum_defaultEncoding_PC_INCREMENT 2'b10 +`define Src1CtrlEnum_defaultEncoding_URS1 2'b11 + +`define AluCtrlEnum_defaultEncoding_type [1:0] +`define AluCtrlEnum_defaultEncoding_ADD_SUB 2'b00 +`define AluCtrlEnum_defaultEncoding_SLT_SLTU 2'b01 +`define AluCtrlEnum_defaultEncoding_BITWISE 2'b10 + +`define BranchCtrlEnum_defaultEncoding_type [1:0] +`define BranchCtrlEnum_defaultEncoding_INC 2'b00 +`define BranchCtrlEnum_defaultEncoding_B 2'b01 +`define BranchCtrlEnum_defaultEncoding_JAL 2'b10 +`define BranchCtrlEnum_defaultEncoding_JALR 2'b11 + +`define ShiftCtrlEnum_defaultEncoding_type [1:0] +`define ShiftCtrlEnum_defaultEncoding_DISABLE_1 2'b00 +`define ShiftCtrlEnum_defaultEncoding_SLL_1 2'b01 +`define ShiftCtrlEnum_defaultEncoding_SRL_1 2'b10 +`define ShiftCtrlEnum_defaultEncoding_SRA_1 2'b11 + +`define AluBitwiseCtrlEnum_defaultEncoding_type [1:0] +`define AluBitwiseCtrlEnum_defaultEncoding_XOR_1 2'b00 +`define AluBitwiseCtrlEnum_defaultEncoding_OR_1 2'b01 +`define AluBitwiseCtrlEnum_defaultEncoding_AND_1 2'b10 + +module InstructionCache ( + input io_flush, + input io_cpu_prefetch_isValid, + output reg io_cpu_prefetch_haltIt, + input [31:0] io_cpu_prefetch_pc, + input io_cpu_fetch_isValid, + input io_cpu_fetch_isStuck, + input io_cpu_fetch_isRemoved, + input [31:0] io_cpu_fetch_pc, + output [31:0] io_cpu_fetch_data, + input io_cpu_fetch_dataBypassValid, + input [31:0] io_cpu_fetch_dataBypass, + output io_cpu_fetch_mmuBus_cmd_isValid, + output [31:0] io_cpu_fetch_mmuBus_cmd_virtualAddress, + output io_cpu_fetch_mmuBus_cmd_bypassTranslation, + input [31:0] io_cpu_fetch_mmuBus_rsp_physicalAddress, + input io_cpu_fetch_mmuBus_rsp_isIoAccess, + input io_cpu_fetch_mmuBus_rsp_allowRead, + input io_cpu_fetch_mmuBus_rsp_allowWrite, + input io_cpu_fetch_mmuBus_rsp_allowExecute, + input io_cpu_fetch_mmuBus_rsp_exception, + input io_cpu_fetch_mmuBus_rsp_refilling, + output io_cpu_fetch_mmuBus_end, + input io_cpu_fetch_mmuBus_busy, + output [31:0] io_cpu_fetch_physicalAddress, + output io_cpu_fetch_cacheMiss, + output io_cpu_fetch_error, + output io_cpu_fetch_mmuRefilling, + output io_cpu_fetch_mmuException, + input io_cpu_fetch_isUser, + output io_cpu_fetch_haltIt, + input io_cpu_decode_isValid, + input io_cpu_decode_isStuck, + input [31:0] io_cpu_decode_pc, + output [31:0] io_cpu_decode_physicalAddress, + output [31:0] io_cpu_decode_data, + input io_cpu_fill_valid, + input [31:0] io_cpu_fill_payload, + output io_mem_cmd_valid, + input io_mem_cmd_ready, + output [31:0] io_mem_cmd_payload_address, + output [2:0] io_mem_cmd_payload_size, + input io_mem_rsp_valid, + input [31:0] io_mem_rsp_payload_data, + input io_mem_rsp_payload_error, + input clk, + input reset); + reg [22:0] _zz_10_; + reg [31:0] _zz_11_; + wire _zz_12_; + wire _zz_13_; + wire [0:0] _zz_14_; + wire [0:0] _zz_15_; + wire [22:0] _zz_16_; + reg _zz_1_; + reg _zz_2_; + reg lineLoader_fire; + reg lineLoader_valid; + reg [31:0] lineLoader_address; + reg lineLoader_hadError; + reg lineLoader_flushPending; + reg [6:0] lineLoader_flushCounter; + reg _zz_3_; + reg lineLoader_cmdSent; + reg lineLoader_wayToAllocate_willIncrement; + wire lineLoader_wayToAllocate_willClear; + wire lineLoader_wayToAllocate_willOverflowIfInc; + wire lineLoader_wayToAllocate_willOverflow; + reg [2:0] lineLoader_wordIndex; + wire lineLoader_write_tag_0_valid; + wire [5:0] lineLoader_write_tag_0_payload_address; + wire lineLoader_write_tag_0_payload_data_valid; + wire lineLoader_write_tag_0_payload_data_error; + wire [20:0] lineLoader_write_tag_0_payload_data_address; + wire lineLoader_write_data_0_valid; + wire [8:0] lineLoader_write_data_0_payload_address; + wire [31:0] lineLoader_write_data_0_payload_data; + wire _zz_4_; + wire [5:0] _zz_5_; + wire _zz_6_; + wire fetchStage_read_waysValues_0_tag_valid; + wire fetchStage_read_waysValues_0_tag_error; + wire [20:0] fetchStage_read_waysValues_0_tag_address; + wire [22:0] _zz_7_; + wire [8:0] _zz_8_; + wire _zz_9_; + wire [31:0] fetchStage_read_waysValues_0_data; + wire fetchStage_hit_hits_0; + wire fetchStage_hit_valid; + wire fetchStage_hit_error; + wire [31:0] fetchStage_hit_data; + wire [31:0] fetchStage_hit_word; + reg [22:0] ways_0_tags [0:63]; + reg [31:0] ways_0_datas [0:511]; + assign _zz_12_ = (! lineLoader_flushCounter[6]); + assign _zz_13_ = (lineLoader_flushPending && (! (lineLoader_valid || io_cpu_fetch_isValid))); + assign _zz_14_ = _zz_7_[0 : 0]; + assign _zz_15_ = _zz_7_[1 : 1]; + assign _zz_16_ = {lineLoader_write_tag_0_payload_data_address,{lineLoader_write_tag_0_payload_data_error,lineLoader_write_tag_0_payload_data_valid}}; + always @ (posedge clk) begin + if(_zz_2_) begin + ways_0_tags[lineLoader_write_tag_0_payload_address] <= _zz_16_; + end + end + + always @ (posedge clk) begin + if(_zz_6_) begin + _zz_10_ <= ways_0_tags[_zz_5_]; + end + end + + always @ (posedge clk) begin + if(_zz_1_) begin + ways_0_datas[lineLoader_write_data_0_payload_address] <= lineLoader_write_data_0_payload_data; + end + end + + always @ (posedge clk) begin + if(_zz_9_) begin + _zz_11_ <= ways_0_datas[_zz_8_]; + end + end + + always @ (*) begin + _zz_1_ = 1'b0; + if(lineLoader_write_data_0_valid)begin + _zz_1_ = 1'b1; + end + end + + always @ (*) begin + _zz_2_ = 1'b0; + if(lineLoader_write_tag_0_valid)begin + _zz_2_ = 1'b1; + end + end + + assign io_cpu_fetch_haltIt = io_cpu_fetch_mmuBus_busy; + always @ (*) begin + lineLoader_fire = 1'b0; + if(io_mem_rsp_valid)begin + if((lineLoader_wordIndex == (3'b111)))begin + lineLoader_fire = 1'b1; + end + end + end + + always @ (*) begin + io_cpu_prefetch_haltIt = (lineLoader_valid || lineLoader_flushPending); + if(_zz_12_)begin + io_cpu_prefetch_haltIt = 1'b1; + end + if((! _zz_3_))begin + io_cpu_prefetch_haltIt = 1'b1; + end + if(io_flush)begin + io_cpu_prefetch_haltIt = 1'b1; + end + end + + assign io_mem_cmd_valid = (lineLoader_valid && (! lineLoader_cmdSent)); + assign io_mem_cmd_payload_address = {lineLoader_address[31 : 5],(5'b00000)}; + assign io_mem_cmd_payload_size = (3'b101); + always @ (*) begin + lineLoader_wayToAllocate_willIncrement = 1'b0; + if(lineLoader_fire)begin + lineLoader_wayToAllocate_willIncrement = 1'b1; + end + end + + assign lineLoader_wayToAllocate_willClear = 1'b0; + assign lineLoader_wayToAllocate_willOverflowIfInc = 1'b1; + assign lineLoader_wayToAllocate_willOverflow = (lineLoader_wayToAllocate_willOverflowIfInc && lineLoader_wayToAllocate_willIncrement); + assign _zz_4_ = 1'b1; + assign lineLoader_write_tag_0_valid = ((_zz_4_ && lineLoader_fire) || (! lineLoader_flushCounter[6])); + assign lineLoader_write_tag_0_payload_address = (lineLoader_flushCounter[6] ? lineLoader_address[10 : 5] : lineLoader_flushCounter[5 : 0]); + assign lineLoader_write_tag_0_payload_data_valid = lineLoader_flushCounter[6]; + assign lineLoader_write_tag_0_payload_data_error = (lineLoader_hadError || io_mem_rsp_payload_error); + assign lineLoader_write_tag_0_payload_data_address = lineLoader_address[31 : 11]; + assign lineLoader_write_data_0_valid = (io_mem_rsp_valid && _zz_4_); + assign lineLoader_write_data_0_payload_address = {lineLoader_address[10 : 5],lineLoader_wordIndex}; + assign lineLoader_write_data_0_payload_data = io_mem_rsp_payload_data; + assign _zz_5_ = io_cpu_prefetch_pc[10 : 5]; + assign _zz_6_ = (! io_cpu_fetch_isStuck); + assign _zz_7_ = _zz_10_; + assign fetchStage_read_waysValues_0_tag_valid = _zz_14_[0]; + assign fetchStage_read_waysValues_0_tag_error = _zz_15_[0]; + assign fetchStage_read_waysValues_0_tag_address = _zz_7_[22 : 2]; + assign _zz_8_ = io_cpu_prefetch_pc[10 : 2]; + assign _zz_9_ = (! io_cpu_fetch_isStuck); + assign fetchStage_read_waysValues_0_data = _zz_11_; + assign fetchStage_hit_hits_0 = (fetchStage_read_waysValues_0_tag_valid && (fetchStage_read_waysValues_0_tag_address == io_cpu_fetch_mmuBus_rsp_physicalAddress[31 : 11])); + assign fetchStage_hit_valid = (fetchStage_hit_hits_0 != (1'b0)); + assign fetchStage_hit_error = fetchStage_read_waysValues_0_tag_error; + assign fetchStage_hit_data = fetchStage_read_waysValues_0_data; + assign fetchStage_hit_word = fetchStage_hit_data[31 : 0]; + assign io_cpu_fetch_data = (io_cpu_fetch_dataBypassValid ? io_cpu_fetch_dataBypass : fetchStage_hit_word); + assign io_cpu_fetch_mmuBus_cmd_isValid = io_cpu_fetch_isValid; + assign io_cpu_fetch_mmuBus_cmd_virtualAddress = io_cpu_fetch_pc; + assign io_cpu_fetch_mmuBus_cmd_bypassTranslation = 1'b0; + assign io_cpu_fetch_mmuBus_end = ((! io_cpu_fetch_isStuck) || io_cpu_fetch_isRemoved); + assign io_cpu_fetch_physicalAddress = io_cpu_fetch_mmuBus_rsp_physicalAddress; + assign io_cpu_fetch_cacheMiss = (! fetchStage_hit_valid); + assign io_cpu_fetch_error = fetchStage_hit_error; + assign io_cpu_fetch_mmuRefilling = io_cpu_fetch_mmuBus_rsp_refilling; + assign io_cpu_fetch_mmuException = ((! io_cpu_fetch_mmuBus_rsp_refilling) && (io_cpu_fetch_mmuBus_rsp_exception || (! io_cpu_fetch_mmuBus_rsp_allowExecute))); + always @ (posedge clk) begin + if(reset) begin + lineLoader_valid <= 1'b0; + lineLoader_hadError <= 1'b0; + lineLoader_flushPending <= 1'b1; + lineLoader_cmdSent <= 1'b0; + lineLoader_wordIndex <= (3'b000); + end else begin + if(lineLoader_fire)begin + lineLoader_valid <= 1'b0; + end + if(lineLoader_fire)begin + lineLoader_hadError <= 1'b0; + end + if(io_cpu_fill_valid)begin + lineLoader_valid <= 1'b1; + end + if(io_flush)begin + lineLoader_flushPending <= 1'b1; + end + if(_zz_13_)begin + lineLoader_flushPending <= 1'b0; + end + if((io_mem_cmd_valid && io_mem_cmd_ready))begin + lineLoader_cmdSent <= 1'b1; + end + if(lineLoader_fire)begin + lineLoader_cmdSent <= 1'b0; + end + if(io_mem_rsp_valid)begin + lineLoader_wordIndex <= (lineLoader_wordIndex + (3'b001)); + if(io_mem_rsp_payload_error)begin + lineLoader_hadError <= 1'b1; + end + end + end + end + + always @ (posedge clk) begin + if(io_cpu_fill_valid)begin + lineLoader_address <= io_cpu_fill_payload; + end + if(_zz_12_)begin + lineLoader_flushCounter <= (lineLoader_flushCounter + (7'b0000001)); + end + _zz_3_ <= lineLoader_flushCounter[6]; + if(_zz_13_)begin + lineLoader_flushCounter <= (7'b0000000); + end + end + +endmodule + +module VexRiscv ( + input [31:0] externalResetVector, + input timerInterrupt, + input softwareInterrupt, + input [31:0] externalInterruptArray, + output reg iBusWishbone_CYC, + output reg iBusWishbone_STB, + input iBusWishbone_ACK, + output iBusWishbone_WE, + output [29:0] iBusWishbone_ADR, + input [31:0] iBusWishbone_DAT_MISO, + output [31:0] iBusWishbone_DAT_MOSI, + output [3:0] iBusWishbone_SEL, + input iBusWishbone_ERR, + output [1:0] iBusWishbone_BTE, + output [2:0] iBusWishbone_CTI, + output dBusWishbone_CYC, + output dBusWishbone_STB, + input dBusWishbone_ACK, + output dBusWishbone_WE, + output [29:0] dBusWishbone_ADR, + input [31:0] dBusWishbone_DAT_MISO, + output [31:0] dBusWishbone_DAT_MOSI, + output reg [3:0] dBusWishbone_SEL, + input dBusWishbone_ERR, + output [1:0] dBusWishbone_BTE, + output [2:0] dBusWishbone_CTI, + input clk, + input reset); + wire _zz_130_; + wire _zz_131_; + wire _zz_132_; + wire _zz_133_; + wire _zz_134_; + wire [31:0] _zz_135_; + wire _zz_136_; + wire _zz_137_; + wire _zz_138_; + wire _zz_139_; + wire _zz_140_; + wire _zz_141_; + wire _zz_142_; + wire _zz_143_; + wire _zz_144_; + wire _zz_145_; + wire [31:0] _zz_146_; + reg _zz_147_; + reg [31:0] _zz_148_; + reg [31:0] _zz_149_; + reg [31:0] _zz_150_; + reg [3:0] _zz_151_; + reg [31:0] _zz_152_; + wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt; + wire IBusCachedPlugin_cache_io_cpu_fetch_error; + wire IBusCachedPlugin_cache_io_cpu_fetch_mmuRefilling; + wire IBusCachedPlugin_cache_io_cpu_fetch_mmuException; + wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_data; + wire IBusCachedPlugin_cache_io_cpu_fetch_cacheMiss; + wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress; + wire IBusCachedPlugin_cache_io_cpu_fetch_haltIt; + wire IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_isValid; + wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_virtualAddress; + wire IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_bypassTranslation; + wire IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_end; + wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_data; + wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_physicalAddress; + wire IBusCachedPlugin_cache_io_mem_cmd_valid; + wire [31:0] IBusCachedPlugin_cache_io_mem_cmd_payload_address; + wire [2:0] IBusCachedPlugin_cache_io_mem_cmd_payload_size; + wire _zz_153_; + wire _zz_154_; + wire _zz_155_; + wire _zz_156_; + wire _zz_157_; + wire _zz_158_; + wire [1:0] _zz_159_; + wire _zz_160_; + wire _zz_161_; + wire _zz_162_; + wire [1:0] _zz_163_; + wire _zz_164_; + wire [2:0] _zz_165_; + wire [2:0] _zz_166_; + wire [31:0] _zz_167_; + wire [2:0] _zz_168_; + wire [0:0] _zz_169_; + wire [0:0] _zz_170_; + wire [0:0] _zz_171_; + wire [0:0] _zz_172_; + wire [0:0] _zz_173_; + wire [0:0] _zz_174_; + wire [0:0] _zz_175_; + wire [0:0] _zz_176_; + wire [0:0] _zz_177_; + wire [2:0] _zz_178_; + wire [4:0] _zz_179_; + wire [11:0] _zz_180_; + wire [11:0] _zz_181_; + wire [31:0] _zz_182_; + wire [31:0] _zz_183_; + wire [31:0] _zz_184_; + wire [31:0] _zz_185_; + wire [31:0] _zz_186_; + wire [31:0] _zz_187_; + wire [31:0] _zz_188_; + wire [31:0] _zz_189_; + wire [32:0] _zz_190_; + wire [19:0] _zz_191_; + wire [11:0] _zz_192_; + wire [11:0] _zz_193_; + wire [1:0] _zz_194_; + wire [1:0] _zz_195_; + wire [2:0] _zz_196_; + wire [0:0] _zz_197_; + wire [0:0] _zz_198_; + wire [0:0] _zz_199_; + wire [0:0] _zz_200_; + wire [0:0] _zz_201_; + wire [0:0] _zz_202_; + wire [26:0] _zz_203_; + wire [6:0] _zz_204_; + wire [1:0] _zz_205_; + wire _zz_206_; + wire _zz_207_; + wire [0:0] _zz_208_; + wire [4:0] _zz_209_; + wire [0:0] _zz_210_; + wire [0:0] _zz_211_; + wire _zz_212_; + wire [0:0] _zz_213_; + wire [20:0] _zz_214_; + wire [31:0] _zz_215_; + wire [31:0] _zz_216_; + wire _zz_217_; + wire [0:0] _zz_218_; + wire [1:0] _zz_219_; + wire [31:0] _zz_220_; + wire [31:0] _zz_221_; + wire [31:0] _zz_222_; + wire [0:0] _zz_223_; + wire [1:0] _zz_224_; + wire [1:0] _zz_225_; + wire [1:0] _zz_226_; + wire _zz_227_; + wire [0:0] _zz_228_; + wire [17:0] _zz_229_; + wire [31:0] _zz_230_; + wire _zz_231_; + wire _zz_232_; + wire [31:0] _zz_233_; + wire [31:0] _zz_234_; + wire _zz_235_; + wire _zz_236_; + wire _zz_237_; + wire _zz_238_; + wire _zz_239_; + wire [0:0] _zz_240_; + wire [0:0] _zz_241_; + wire _zz_242_; + wire [0:0] _zz_243_; + wire [15:0] _zz_244_; + wire [31:0] _zz_245_; + wire [31:0] _zz_246_; + wire [31:0] _zz_247_; + wire [31:0] _zz_248_; + wire [31:0] _zz_249_; + wire [31:0] _zz_250_; + wire [31:0] _zz_251_; + wire [31:0] _zz_252_; + wire [31:0] _zz_253_; + wire [0:0] _zz_254_; + wire [0:0] _zz_255_; + wire [1:0] _zz_256_; + wire [1:0] _zz_257_; + wire _zz_258_; + wire [0:0] _zz_259_; + wire [13:0] _zz_260_; + wire [31:0] _zz_261_; + wire [31:0] _zz_262_; + wire [31:0] _zz_263_; + wire _zz_264_; + wire [0:0] _zz_265_; + wire [1:0] _zz_266_; + wire [0:0] _zz_267_; + wire [0:0] _zz_268_; + wire [1:0] _zz_269_; + wire [1:0] _zz_270_; + wire _zz_271_; + wire [0:0] _zz_272_; + wire [10:0] _zz_273_; + wire [31:0] _zz_274_; + wire [31:0] _zz_275_; + wire [31:0] _zz_276_; + wire _zz_277_; + wire _zz_278_; + wire [31:0] _zz_279_; + wire [31:0] _zz_280_; + wire [31:0] _zz_281_; + wire [31:0] _zz_282_; + wire _zz_283_; + wire _zz_284_; + wire [0:0] _zz_285_; + wire [0:0] _zz_286_; + wire _zz_287_; + wire [0:0] _zz_288_; + wire [8:0] _zz_289_; + wire [31:0] _zz_290_; + wire _zz_291_; + wire _zz_292_; + wire [0:0] _zz_293_; + wire [0:0] _zz_294_; + wire [0:0] _zz_295_; + wire [0:0] _zz_296_; + wire _zz_297_; + wire [0:0] _zz_298_; + wire [5:0] _zz_299_; + wire [31:0] _zz_300_; + wire [31:0] _zz_301_; + wire [31:0] _zz_302_; + wire [31:0] _zz_303_; + wire [31:0] _zz_304_; + wire [0:0] _zz_305_; + wire [0:0] _zz_306_; + wire [1:0] _zz_307_; + wire [1:0] _zz_308_; + wire _zz_309_; + wire [0:0] _zz_310_; + wire [2:0] _zz_311_; + wire [31:0] _zz_312_; + wire [31:0] _zz_313_; + wire _zz_314_; + wire _zz_315_; + wire _zz_316_; + wire [0:0] _zz_317_; + wire [0:0] _zz_318_; + wire [1:0] _zz_319_; + wire [1:0] _zz_320_; + wire [31:0] _zz_321_; + wire [31:0] _zz_322_; + wire [31:0] _zz_323_; + wire _zz_324_; + wire [0:0] _zz_325_; + wire [12:0] _zz_326_; + wire [31:0] _zz_327_; + wire [31:0] _zz_328_; + wire [31:0] _zz_329_; + wire _zz_330_; + wire [0:0] _zz_331_; + wire [6:0] _zz_332_; + wire [31:0] _zz_333_; + wire [31:0] _zz_334_; + wire [31:0] _zz_335_; + wire _zz_336_; + wire [0:0] _zz_337_; + wire [0:0] _zz_338_; + wire decode_CSR_WRITE_OPCODE; + wire decode_SRC_LESS_UNSIGNED; + wire `EnvCtrlEnum_defaultEncoding_type decode_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_1_; + wire `EnvCtrlEnum_defaultEncoding_type _zz_2_; + wire `EnvCtrlEnum_defaultEncoding_type _zz_3_; + wire [31:0] execute_FORMAL_PC_NEXT; + wire [31:0] decode_FORMAL_PC_NEXT; + wire `Src2CtrlEnum_defaultEncoding_type decode_SRC2_CTRL; + wire `Src2CtrlEnum_defaultEncoding_type _zz_4_; + wire `Src2CtrlEnum_defaultEncoding_type _zz_5_; + wire `Src2CtrlEnum_defaultEncoding_type _zz_6_; + wire decode_IS_CSR; + wire decode_MEMORY_ENABLE; + wire `Src1CtrlEnum_defaultEncoding_type decode_SRC1_CTRL; + wire `Src1CtrlEnum_defaultEncoding_type _zz_7_; + wire `Src1CtrlEnum_defaultEncoding_type _zz_8_; + wire `Src1CtrlEnum_defaultEncoding_type _zz_9_; + wire decode_CSR_READ_OPCODE; + wire execute_REGFILE_WRITE_VALID; + wire `AluCtrlEnum_defaultEncoding_type decode_ALU_CTRL; + wire `AluCtrlEnum_defaultEncoding_type _zz_10_; + wire `AluCtrlEnum_defaultEncoding_type _zz_11_; + wire `AluCtrlEnum_defaultEncoding_type _zz_12_; + wire decode_SRC2_FORCE_ZERO; + wire decode_MEMORY_STORE; + wire `BranchCtrlEnum_defaultEncoding_type decode_BRANCH_CTRL; + wire `BranchCtrlEnum_defaultEncoding_type _zz_13_; + wire `BranchCtrlEnum_defaultEncoding_type _zz_14_; + wire `BranchCtrlEnum_defaultEncoding_type _zz_15_; + wire `ShiftCtrlEnum_defaultEncoding_type decode_SHIFT_CTRL; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_16_; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_17_; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_18_; + wire `AluBitwiseCtrlEnum_defaultEncoding_type decode_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_19_; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_20_; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_21_; + wire execute_CSR_READ_OPCODE; + wire execute_CSR_WRITE_OPCODE; + wire execute_IS_CSR; + wire _zz_22_; + wire _zz_23_; + wire `EnvCtrlEnum_defaultEncoding_type execute_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_24_; + wire [31:0] execute_BRANCH_CALC; + wire execute_BRANCH_DO; + wire [31:0] _zz_25_; + wire [31:0] execute_PC; + wire [31:0] execute_RS1; + wire `BranchCtrlEnum_defaultEncoding_type execute_BRANCH_CTRL; + wire `BranchCtrlEnum_defaultEncoding_type _zz_26_; + wire _zz_27_; + wire `ShiftCtrlEnum_defaultEncoding_type execute_SHIFT_CTRL; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_28_; + wire _zz_29_; + wire [31:0] _zz_30_; + wire [31:0] _zz_31_; + wire execute_SRC_LESS_UNSIGNED; + wire execute_SRC2_FORCE_ZERO; + wire execute_SRC_USE_SUB_LESS; + wire `Src2CtrlEnum_defaultEncoding_type execute_SRC2_CTRL; + wire `Src2CtrlEnum_defaultEncoding_type _zz_32_; + wire [31:0] _zz_33_; + wire `Src1CtrlEnum_defaultEncoding_type execute_SRC1_CTRL; + wire `Src1CtrlEnum_defaultEncoding_type _zz_34_; + wire [31:0] _zz_35_; + wire decode_SRC_USE_SUB_LESS; + wire decode_SRC_ADD_ZERO; + wire _zz_36_; + wire [31:0] execute_SRC_ADD_SUB; + wire execute_SRC_LESS; + wire `AluCtrlEnum_defaultEncoding_type execute_ALU_CTRL; + wire `AluCtrlEnum_defaultEncoding_type _zz_37_; + wire [31:0] _zz_38_; + wire [31:0] execute_SRC2; + wire [31:0] execute_SRC1; + wire `AluBitwiseCtrlEnum_defaultEncoding_type execute_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_39_; + reg _zz_40_; + wire [31:0] _zz_41_; + wire [31:0] _zz_42_; + reg decode_REGFILE_WRITE_VALID; + wire decode_LEGAL_INSTRUCTION; + wire decode_INSTRUCTION_READY; + wire _zz_43_; + wire _zz_44_; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_45_; + wire _zz_46_; + wire _zz_47_; + wire _zz_48_; + wire _zz_49_; + wire `Src1CtrlEnum_defaultEncoding_type _zz_50_; + wire `BranchCtrlEnum_defaultEncoding_type _zz_51_; + wire `EnvCtrlEnum_defaultEncoding_type _zz_52_; + wire `AluCtrlEnum_defaultEncoding_type _zz_53_; + wire _zz_54_; + wire `Src2CtrlEnum_defaultEncoding_type _zz_55_; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_56_; + wire _zz_57_; + wire _zz_58_; + reg [31:0] _zz_59_; + wire [1:0] execute_MEMORY_ADDRESS_LOW; + wire [31:0] execute_MEMORY_READ_DATA; + wire [31:0] execute_REGFILE_WRITE_DATA; + wire [31:0] _zz_60_; + wire [31:0] execute_SRC_ADD; + wire [1:0] _zz_61_; + wire [31:0] execute_RS2; + wire [31:0] execute_INSTRUCTION; + wire execute_MEMORY_STORE; + wire execute_MEMORY_ENABLE; + wire execute_ALIGNEMENT_FAULT; + wire _zz_62_; + wire decode_FLUSH_ALL; + reg IBusCachedPlugin_rsp_issueDetected; + reg _zz_63_; + reg _zz_64_; + reg _zz_65_; + reg [31:0] _zz_66_; + wire [31:0] _zz_67_; + wire [31:0] _zz_68_; + wire [31:0] _zz_69_; + wire [31:0] decode_PC /* verilator public */ ; + wire [31:0] decode_INSTRUCTION /* verilator public */ ; + wire decode_arbitration_haltItself /* verilator public */ ; + reg decode_arbitration_haltByOther; + reg decode_arbitration_removeIt; + reg decode_arbitration_flushAll /* verilator public */ ; + wire decode_arbitration_isValid /* verilator public */ ; + wire decode_arbitration_isStuck; + wire decode_arbitration_isStuckByOthers; + wire decode_arbitration_isFlushed; + wire decode_arbitration_isMoving; + wire decode_arbitration_isFiring; + reg execute_arbitration_haltItself; + wire execute_arbitration_haltByOther; + reg execute_arbitration_removeIt; + wire execute_arbitration_flushAll; + reg execute_arbitration_isValid; + wire execute_arbitration_isStuck; + wire execute_arbitration_isStuckByOthers; + wire execute_arbitration_isFlushed; + wire execute_arbitration_isMoving; + wire execute_arbitration_isFiring; + reg IBusCachedPlugin_fetcherHalt; + wire IBusCachedPlugin_fetcherflushIt; + reg IBusCachedPlugin_incomingInstruction; + wire IBusCachedPlugin_pcValids_0; + wire IBusCachedPlugin_pcValids_1; + wire IBusCachedPlugin_redoBranch_valid; + wire [31:0] IBusCachedPlugin_redoBranch_payload; + reg IBusCachedPlugin_decodeExceptionPort_valid; + reg [3:0] IBusCachedPlugin_decodeExceptionPort_payload_code; + wire [31:0] IBusCachedPlugin_decodeExceptionPort_payload_badAddr; + reg DBusSimplePlugin_memoryExceptionPort_valid; + reg [3:0] DBusSimplePlugin_memoryExceptionPort_payload_code; + wire [31:0] DBusSimplePlugin_memoryExceptionPort_payload_badAddr; + wire decodeExceptionPort_valid; + wire [3:0] decodeExceptionPort_payload_code; + wire [31:0] decodeExceptionPort_payload_badAddr; + wire BranchPlugin_jumpInterface_valid; + wire [31:0] BranchPlugin_jumpInterface_payload; + reg BranchPlugin_branchExceptionPort_valid; + wire [3:0] BranchPlugin_branchExceptionPort_payload_code; + wire [31:0] BranchPlugin_branchExceptionPort_payload_badAddr; + reg CsrPlugin_jumpInterface_valid; + reg [31:0] CsrPlugin_jumpInterface_payload; + wire CsrPlugin_exceptionPendings_0; + wire CsrPlugin_exceptionPendings_1; + wire externalInterrupt; + wire contextSwitching; + reg [1:0] CsrPlugin_privilege; + wire CsrPlugin_forceMachineWire; + reg CsrPlugin_selfException_valid; + reg [3:0] CsrPlugin_selfException_payload_code; + wire [31:0] CsrPlugin_selfException_payload_badAddr; + wire CsrPlugin_allowInterrupts; + wire CsrPlugin_allowException; + wire IBusCachedPlugin_jump_pcLoad_valid; + wire [31:0] IBusCachedPlugin_jump_pcLoad_payload; + wire [2:0] _zz_70_; + wire [2:0] _zz_71_; + wire _zz_72_; + wire _zz_73_; + wire IBusCachedPlugin_fetchPc_preOutput_valid; + wire IBusCachedPlugin_fetchPc_preOutput_ready; + wire [31:0] IBusCachedPlugin_fetchPc_preOutput_payload; + wire _zz_74_; + wire IBusCachedPlugin_fetchPc_output_valid; + wire IBusCachedPlugin_fetchPc_output_ready; + wire [31:0] IBusCachedPlugin_fetchPc_output_payload; + reg [31:0] IBusCachedPlugin_fetchPc_pcReg /* verilator public */ ; + reg IBusCachedPlugin_fetchPc_inc; + reg IBusCachedPlugin_fetchPc_propagatePc; + reg [31:0] IBusCachedPlugin_fetchPc_pc; + reg IBusCachedPlugin_fetchPc_samplePcNext; + reg _zz_75_; + wire IBusCachedPlugin_iBusRsp_stages_0_input_valid; + wire IBusCachedPlugin_iBusRsp_stages_0_input_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_input_payload; + wire IBusCachedPlugin_iBusRsp_stages_0_output_valid; + wire IBusCachedPlugin_iBusRsp_stages_0_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_output_payload; + reg IBusCachedPlugin_iBusRsp_stages_0_halt; + wire IBusCachedPlugin_iBusRsp_stages_0_inputSample; + wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid; + wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload; + wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_valid; + wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_payload; + reg IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt; + wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_inputSample; + wire _zz_76_; + wire _zz_77_; + wire _zz_78_; + wire _zz_79_; + reg _zz_80_; + reg IBusCachedPlugin_iBusRsp_readyForError; + wire IBusCachedPlugin_iBusRsp_decodeInput_valid; + wire IBusCachedPlugin_iBusRsp_decodeInput_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_decodeInput_payload_pc; + wire IBusCachedPlugin_iBusRsp_decodeInput_payload_rsp_error; + wire [31:0] IBusCachedPlugin_iBusRsp_decodeInput_payload_rsp_inst; + wire IBusCachedPlugin_iBusRsp_decodeInput_payload_isRvc; + reg IBusCachedPlugin_injector_nextPcCalc_valids_0; + reg IBusCachedPlugin_injector_nextPcCalc_valids_1; + reg IBusCachedPlugin_injector_decodeRemoved; + wire iBus_cmd_valid; + wire iBus_cmd_ready; + reg [31:0] iBus_cmd_payload_address; + wire [2:0] iBus_cmd_payload_size; + wire iBus_rsp_valid; + wire [31:0] iBus_rsp_payload_data; + wire iBus_rsp_payload_error; + wire IBusCachedPlugin_s0_tightlyCoupledHit; + reg IBusCachedPlugin_s1_tightlyCoupledHit; + wire IBusCachedPlugin_rsp_iBusRspOutputHalt; + reg IBusCachedPlugin_rsp_redoFetch; + wire dBus_cmd_valid; + wire dBus_cmd_ready; + wire dBus_cmd_payload_wr; + wire [31:0] dBus_cmd_payload_address; + wire [31:0] dBus_cmd_payload_data; + wire [1:0] dBus_cmd_payload_size; + wire dBus_rsp_ready; + wire dBus_rsp_error; + wire [31:0] dBus_rsp_data; + reg execute_DBusSimplePlugin_cmdSent; + reg execute_DBusSimplePlugin_skipCmd; + reg [31:0] _zz_81_; + reg [3:0] _zz_82_; + wire [3:0] execute_DBusSimplePlugin_formalMask; + reg [31:0] execute_DBusSimplePlugin_rspShifted; + wire _zz_83_; + reg [31:0] _zz_84_; + wire _zz_85_; + reg [31:0] _zz_86_; + reg [31:0] execute_DBusSimplePlugin_rspFormated; + wire [26:0] _zz_87_; + wire _zz_88_; + wire _zz_89_; + wire _zz_90_; + wire _zz_91_; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_92_; + wire `Src2CtrlEnum_defaultEncoding_type _zz_93_; + wire `AluCtrlEnum_defaultEncoding_type _zz_94_; + wire `EnvCtrlEnum_defaultEncoding_type _zz_95_; + wire `BranchCtrlEnum_defaultEncoding_type _zz_96_; + wire `Src1CtrlEnum_defaultEncoding_type _zz_97_; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_98_; + wire [4:0] execute_RegFilePlugin_regFileReadAddress1; + wire [4:0] execute_RegFilePlugin_regFileReadAddress2; + wire _zz_99_; + wire [31:0] execute_RegFilePlugin_rs1Data; + wire [31:0] execute_RegFilePlugin_rs2Data; + wire execute_RegFilePlugin_regFileWrite_valid /* verilator public */ ; + wire [4:0] execute_RegFilePlugin_regFileWrite_payload_address /* verilator public */ ; + wire [31:0] execute_RegFilePlugin_regFileWrite_payload_data /* verilator public */ ; + reg [31:0] execute_IntAluPlugin_bitwise; + reg [31:0] _zz_100_; + reg [31:0] _zz_101_; + wire _zz_102_; + reg [19:0] _zz_103_; + wire _zz_104_; + reg [19:0] _zz_105_; + reg [31:0] _zz_106_; + reg [31:0] execute_SrcPlugin_addSub; + wire execute_SrcPlugin_less; + reg execute_LightShifterPlugin_isActive; + wire execute_LightShifterPlugin_isShift; + reg [4:0] execute_LightShifterPlugin_amplitudeReg; + wire [4:0] execute_LightShifterPlugin_amplitude; + reg [31:0] execute_LightShifterPlugin_shiftReg; + wire [31:0] execute_LightShifterPlugin_shiftInput; + wire execute_LightShifterPlugin_done; + reg [31:0] _zz_107_; + wire execute_BranchPlugin_eq; + wire [2:0] _zz_108_; + reg _zz_109_; + reg _zz_110_; + wire [31:0] execute_BranchPlugin_branch_src1; + wire _zz_111_; + reg [10:0] _zz_112_; + wire _zz_113_; + reg [19:0] _zz_114_; + wire _zz_115_; + reg [18:0] _zz_116_; + reg [31:0] _zz_117_; + wire [31:0] execute_BranchPlugin_branch_src2; + wire [31:0] execute_BranchPlugin_branchAdder; + wire [1:0] CsrPlugin_misa_base; + wire [25:0] CsrPlugin_misa_extensions; + reg [1:0] CsrPlugin_mtvec_mode; + reg [29:0] CsrPlugin_mtvec_base; + reg [31:0] CsrPlugin_mepc; + reg CsrPlugin_mstatus_MIE; + reg CsrPlugin_mstatus_MPIE; + reg [1:0] CsrPlugin_mstatus_MPP; + reg CsrPlugin_mip_MEIP; + reg CsrPlugin_mip_MTIP; + reg CsrPlugin_mip_MSIP; + reg CsrPlugin_mie_MEIE; + reg CsrPlugin_mie_MTIE; + reg CsrPlugin_mie_MSIE; + reg [31:0] CsrPlugin_mscratch; + reg CsrPlugin_mcause_interrupt; + reg [3:0] CsrPlugin_mcause_exceptionCode; + reg [31:0] CsrPlugin_mtval; + reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000; + reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; + reg [3:0] CsrPlugin_exceptionPortCtrl_exceptionContext_code; + reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; + wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped; + wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; + wire [1:0] _zz_118_; + wire _zz_119_; + wire [2:0] _zz_120_; + wire [2:0] _zz_121_; + wire _zz_122_; + wire _zz_123_; + wire [1:0] _zz_124_; + reg CsrPlugin_interrupt; + reg [3:0] CsrPlugin_interruptCode /* verilator public */ ; + reg [1:0] CsrPlugin_interruptTargetPrivilege; + wire CsrPlugin_exception; + wire CsrPlugin_lastStageWasWfi; + reg CsrPlugin_pipelineLiberator_done; + wire CsrPlugin_interruptJump /* verilator public */ ; + reg CsrPlugin_hadException; + reg [1:0] CsrPlugin_targetPrivilege; + reg [3:0] CsrPlugin_trapCause; + reg [1:0] CsrPlugin_xtvec_mode; + reg [29:0] CsrPlugin_xtvec_base; + wire execute_CsrPlugin_inWfi /* verilator public */ ; + wire execute_CsrPlugin_blockedBySideEffects; + reg execute_CsrPlugin_illegalAccess; + reg execute_CsrPlugin_illegalInstruction; + reg [31:0] execute_CsrPlugin_readData; + wire execute_CsrPlugin_writeInstruction; + wire execute_CsrPlugin_readInstruction; + wire execute_CsrPlugin_writeEnable; + wire execute_CsrPlugin_readEnable; + wire [31:0] execute_CsrPlugin_readToWriteData; + reg [31:0] execute_CsrPlugin_writeData; + wire [11:0] execute_CsrPlugin_csrAddress; + reg [31:0] _zz_125_; + reg [31:0] externalInterruptArray_regNext; + wire [31:0] _zz_126_; + reg `AluBitwiseCtrlEnum_defaultEncoding_type decode_to_execute_ALU_BITWISE_CTRL; + reg `ShiftCtrlEnum_defaultEncoding_type decode_to_execute_SHIFT_CTRL; + reg `BranchCtrlEnum_defaultEncoding_type decode_to_execute_BRANCH_CTRL; + reg decode_to_execute_MEMORY_STORE; + reg decode_to_execute_SRC2_FORCE_ZERO; + reg `AluCtrlEnum_defaultEncoding_type decode_to_execute_ALU_CTRL; + reg decode_to_execute_SRC_USE_SUB_LESS; + reg decode_to_execute_REGFILE_WRITE_VALID; + reg decode_to_execute_CSR_READ_OPCODE; + reg `Src1CtrlEnum_defaultEncoding_type decode_to_execute_SRC1_CTRL; + reg decode_to_execute_MEMORY_ENABLE; + reg decode_to_execute_IS_CSR; + reg `Src2CtrlEnum_defaultEncoding_type decode_to_execute_SRC2_CTRL; + reg [31:0] decode_to_execute_PC; + reg [31:0] decode_to_execute_INSTRUCTION; + reg [31:0] decode_to_execute_FORMAL_PC_NEXT; + reg `EnvCtrlEnum_defaultEncoding_type decode_to_execute_ENV_CTRL; + reg decode_to_execute_SRC_LESS_UNSIGNED; + reg decode_to_execute_CSR_WRITE_OPCODE; + reg [2:0] _zz_127_; + reg _zz_128_; + reg [31:0] iBusWishbone_DAT_MISO_regNext; + wire dBus_cmd_halfPipe_valid; + wire dBus_cmd_halfPipe_ready; + wire dBus_cmd_halfPipe_payload_wr; + wire [31:0] dBus_cmd_halfPipe_payload_address; + wire [31:0] dBus_cmd_halfPipe_payload_data; + wire [1:0] dBus_cmd_halfPipe_payload_size; + reg dBus_cmd_halfPipe_regs_valid; + reg dBus_cmd_halfPipe_regs_ready; + reg dBus_cmd_halfPipe_regs_payload_wr; + reg [31:0] dBus_cmd_halfPipe_regs_payload_address; + reg [31:0] dBus_cmd_halfPipe_regs_payload_data; + reg [1:0] dBus_cmd_halfPipe_regs_payload_size; + reg [3:0] _zz_129_; + `ifndef SYNTHESIS + reg [47:0] decode_ENV_CTRL_string; + reg [47:0] _zz_1__string; + reg [47:0] _zz_2__string; + reg [47:0] _zz_3__string; + reg [23:0] decode_SRC2_CTRL_string; + reg [23:0] _zz_4__string; + reg [23:0] _zz_5__string; + reg [23:0] _zz_6__string; + reg [95:0] decode_SRC1_CTRL_string; + reg [95:0] _zz_7__string; + reg [95:0] _zz_8__string; + reg [95:0] _zz_9__string; + reg [63:0] decode_ALU_CTRL_string; + reg [63:0] _zz_10__string; + reg [63:0] _zz_11__string; + reg [63:0] _zz_12__string; + reg [31:0] decode_BRANCH_CTRL_string; + reg [31:0] _zz_13__string; + reg [31:0] _zz_14__string; + reg [31:0] _zz_15__string; + reg [71:0] decode_SHIFT_CTRL_string; + reg [71:0] _zz_16__string; + reg [71:0] _zz_17__string; + reg [71:0] _zz_18__string; + reg [39:0] decode_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_19__string; + reg [39:0] _zz_20__string; + reg [39:0] _zz_21__string; + reg [47:0] execute_ENV_CTRL_string; + reg [47:0] _zz_24__string; + reg [31:0] execute_BRANCH_CTRL_string; + reg [31:0] _zz_26__string; + reg [71:0] execute_SHIFT_CTRL_string; + reg [71:0] _zz_28__string; + reg [23:0] execute_SRC2_CTRL_string; + reg [23:0] _zz_32__string; + reg [95:0] execute_SRC1_CTRL_string; + reg [95:0] _zz_34__string; + reg [63:0] execute_ALU_CTRL_string; + reg [63:0] _zz_37__string; + reg [39:0] execute_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_39__string; + reg [39:0] _zz_45__string; + reg [95:0] _zz_50__string; + reg [31:0] _zz_51__string; + reg [47:0] _zz_52__string; + reg [63:0] _zz_53__string; + reg [23:0] _zz_55__string; + reg [71:0] _zz_56__string; + reg [71:0] _zz_92__string; + reg [23:0] _zz_93__string; + reg [63:0] _zz_94__string; + reg [47:0] _zz_95__string; + reg [31:0] _zz_96__string; + reg [95:0] _zz_97__string; + reg [39:0] _zz_98__string; + reg [39:0] decode_to_execute_ALU_BITWISE_CTRL_string; + reg [71:0] decode_to_execute_SHIFT_CTRL_string; + reg [31:0] decode_to_execute_BRANCH_CTRL_string; + reg [63:0] decode_to_execute_ALU_CTRL_string; + reg [95:0] decode_to_execute_SRC1_CTRL_string; + reg [23:0] decode_to_execute_SRC2_CTRL_string; + reg [47:0] decode_to_execute_ENV_CTRL_string; + `endif + + reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; + assign _zz_153_ = ((execute_arbitration_isValid && execute_LightShifterPlugin_isShift) && (execute_SRC2[4 : 0] != (5'b00000))); + assign _zz_154_ = (! execute_arbitration_isStuckByOthers); + assign _zz_155_ = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != (2'b00)); + assign _zz_156_ = ({CsrPlugin_selfException_valid,{BranchPlugin_branchExceptionPort_valid,DBusSimplePlugin_memoryExceptionPort_valid}} != (3'b000)); + assign _zz_157_ = (CsrPlugin_hadException || CsrPlugin_interruptJump); + assign _zz_158_ = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); + assign _zz_159_ = execute_INSTRUCTION[29 : 28]; + assign _zz_160_ = (IBusCachedPlugin_fetchPc_preOutput_valid && IBusCachedPlugin_fetchPc_preOutput_ready); + assign _zz_161_ = (iBus_cmd_valid || (_zz_127_ != (3'b000))); + assign _zz_162_ = (! dBus_cmd_halfPipe_regs_valid); + assign _zz_163_ = execute_INSTRUCTION[13 : 12]; + assign _zz_164_ = execute_INSTRUCTION[13]; + assign _zz_165_ = (_zz_70_ - (3'b001)); + assign _zz_166_ = {IBusCachedPlugin_fetchPc_inc,(2'b00)}; + assign _zz_167_ = {29'd0, _zz_166_}; + assign _zz_168_ = (execute_MEMORY_STORE ? (3'b110) : (3'b100)); + assign _zz_169_ = _zz_87_[0 : 0]; + assign _zz_170_ = _zz_87_[7 : 7]; + assign _zz_171_ = _zz_87_[18 : 18]; + assign _zz_172_ = _zz_87_[19 : 19]; + assign _zz_173_ = _zz_87_[20 : 20]; + assign _zz_174_ = _zz_87_[21 : 21]; + assign _zz_175_ = _zz_87_[24 : 24]; + assign _zz_176_ = _zz_87_[25 : 25]; + assign _zz_177_ = execute_SRC_LESS; + assign _zz_178_ = (3'b100); + assign _zz_179_ = execute_INSTRUCTION[19 : 15]; + assign _zz_180_ = execute_INSTRUCTION[31 : 20]; + assign _zz_181_ = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; + assign _zz_182_ = ($signed(_zz_183_) + $signed(_zz_186_)); + assign _zz_183_ = ($signed(_zz_184_) + $signed(_zz_185_)); + assign _zz_184_ = execute_SRC1; + assign _zz_185_ = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); + assign _zz_186_ = (execute_SRC_USE_SUB_LESS ? _zz_187_ : _zz_188_); + assign _zz_187_ = (32'b00000000000000000000000000000001); + assign _zz_188_ = (32'b00000000000000000000000000000000); + assign _zz_189_ = (_zz_190_ >>> 1); + assign _zz_190_ = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_LightShifterPlugin_shiftInput[31]),execute_LightShifterPlugin_shiftInput}; + assign _zz_191_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_192_ = execute_INSTRUCTION[31 : 20]; + assign _zz_193_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_194_ = (_zz_118_ & (~ _zz_195_)); + assign _zz_195_ = (_zz_118_ - (2'b01)); + assign _zz_196_ = (_zz_120_ - (3'b001)); + assign _zz_197_ = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_198_ = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_199_ = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_200_ = execute_CsrPlugin_writeData[11 : 11]; + assign _zz_201_ = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_202_ = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_203_ = (iBus_cmd_payload_address >>> 5); + assign _zz_204_ = ({3'd0,_zz_129_} <<< dBus_cmd_halfPipe_payload_address[1 : 0]); + assign _zz_205_ = {_zz_73_,_zz_72_}; + assign _zz_206_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001100100)) == (32'b00000000000000000000000000100100)); + assign _zz_207_ = ((decode_INSTRUCTION & (32'b00000000000000000011000001010100)) == (32'b00000000000000000001000000010000)); + assign _zz_208_ = _zz_89_; + assign _zz_209_ = {(_zz_215_ == _zz_216_),{_zz_217_,{_zz_218_,_zz_219_}}}; + assign _zz_210_ = ((decode_INSTRUCTION & _zz_220_) == (32'b00000000000000000001000000000000)); + assign _zz_211_ = (1'b0); + assign _zz_212_ = ((_zz_221_ == _zz_222_) != (1'b0)); + assign _zz_213_ = ({_zz_223_,_zz_224_} != (3'b000)); + assign _zz_214_ = {(_zz_225_ != _zz_226_),{_zz_227_,{_zz_228_,_zz_229_}}}; + assign _zz_215_ = (decode_INSTRUCTION & (32'b00000000000000000001000000010000)); + assign _zz_216_ = (32'b00000000000000000001000000010000); + assign _zz_217_ = ((decode_INSTRUCTION & _zz_230_) == (32'b00000000000000000010000000010000)); + assign _zz_218_ = _zz_91_; + assign _zz_219_ = {_zz_231_,_zz_232_}; + assign _zz_220_ = (32'b00000000000000000001000000000000); + assign _zz_221_ = (decode_INSTRUCTION & (32'b00000000000000000011000000000000)); + assign _zz_222_ = (32'b00000000000000000010000000000000); + assign _zz_223_ = (_zz_233_ == _zz_234_); + assign _zz_224_ = {_zz_235_,_zz_236_}; + assign _zz_225_ = {_zz_237_,_zz_238_}; + assign _zz_226_ = (2'b00); + assign _zz_227_ = (_zz_239_ != (1'b0)); + assign _zz_228_ = (_zz_240_ != _zz_241_); + assign _zz_229_ = {_zz_242_,{_zz_243_,_zz_244_}}; + assign _zz_230_ = (32'b00000000000000000010000000010000); + assign _zz_231_ = ((decode_INSTRUCTION & _zz_245_) == (32'b00000000000000000000000000000100)); + assign _zz_232_ = ((decode_INSTRUCTION & _zz_246_) == (32'b00000000000000000000000000000000)); + assign _zz_233_ = (decode_INSTRUCTION & (32'b00000000000000000000000001000100)); + assign _zz_234_ = (32'b00000000000000000000000001000000); + assign _zz_235_ = ((decode_INSTRUCTION & _zz_247_) == (32'b00000000000000000010000000010000)); + assign _zz_236_ = ((decode_INSTRUCTION & _zz_248_) == (32'b01000000000000000000000000110000)); + assign _zz_237_ = ((decode_INSTRUCTION & _zz_249_) == (32'b00000000000000000010000000000000)); + assign _zz_238_ = ((decode_INSTRUCTION & _zz_250_) == (32'b00000000000000000001000000000000)); + assign _zz_239_ = ((decode_INSTRUCTION & _zz_251_) == (32'b00000000000000000000000000100000)); + assign _zz_240_ = (_zz_252_ == _zz_253_); + assign _zz_241_ = (1'b0); + assign _zz_242_ = ({_zz_254_,_zz_255_} != (2'b00)); + assign _zz_243_ = (_zz_256_ != _zz_257_); + assign _zz_244_ = {_zz_258_,{_zz_259_,_zz_260_}}; + assign _zz_245_ = (32'b00000000000000000000000000001100); + assign _zz_246_ = (32'b00000000000000000000000000101000); + assign _zz_247_ = (32'b00000000000000000010000000010100); + assign _zz_248_ = (32'b01000000000000000100000000110100); + assign _zz_249_ = (32'b00000000000000000010000000010000); + assign _zz_250_ = (32'b00000000000000000101000000000000); + assign _zz_251_ = (32'b00000000000000000000000000100000); + assign _zz_252_ = (decode_INSTRUCTION & (32'b00000000000000000000000001011000)); + assign _zz_253_ = (32'b00000000000000000000000000000000); + assign _zz_254_ = ((decode_INSTRUCTION & _zz_261_) == (32'b00000000000000000000000000000100)); + assign _zz_255_ = _zz_90_; + assign _zz_256_ = {(_zz_262_ == _zz_263_),_zz_90_}; + assign _zz_257_ = (2'b00); + assign _zz_258_ = ({_zz_264_,{_zz_265_,_zz_266_}} != (4'b0000)); + assign _zz_259_ = ({_zz_267_,_zz_268_} != (2'b00)); + assign _zz_260_ = {(_zz_269_ != _zz_270_),{_zz_271_,{_zz_272_,_zz_273_}}}; + assign _zz_261_ = (32'b00000000000000000000000000010100); + assign _zz_262_ = (decode_INSTRUCTION & (32'b00000000000000000000000001000100)); + assign _zz_263_ = (32'b00000000000000000000000000000100); + assign _zz_264_ = ((decode_INSTRUCTION & _zz_274_) == (32'b00000000000000000000000000000000)); + assign _zz_265_ = (_zz_275_ == _zz_276_); + assign _zz_266_ = {_zz_277_,_zz_278_}; + assign _zz_267_ = (_zz_279_ == _zz_280_); + assign _zz_268_ = (_zz_281_ == _zz_282_); + assign _zz_269_ = {_zz_89_,_zz_283_}; + assign _zz_270_ = (2'b00); + assign _zz_271_ = (_zz_284_ != (1'b0)); + assign _zz_272_ = (_zz_285_ != _zz_286_); + assign _zz_273_ = {_zz_287_,{_zz_288_,_zz_289_}}; + assign _zz_274_ = (32'b00000000000000000000000001000100); + assign _zz_275_ = (decode_INSTRUCTION & (32'b00000000000000000000000000011000)); + assign _zz_276_ = (32'b00000000000000000000000000000000); + assign _zz_277_ = ((decode_INSTRUCTION & (32'b00000000000000000110000000000100)) == (32'b00000000000000000010000000000000)); + assign _zz_278_ = ((decode_INSTRUCTION & (32'b00000000000000000101000000000100)) == (32'b00000000000000000001000000000000)); + assign _zz_279_ = (decode_INSTRUCTION & (32'b00000000000000000000000000110100)); + assign _zz_280_ = (32'b00000000000000000000000000100000); + assign _zz_281_ = (decode_INSTRUCTION & (32'b00000000000000000000000001100100)); + assign _zz_282_ = (32'b00000000000000000000000000100000); + assign _zz_283_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000011100)) == (32'b00000000000000000000000000000100)); + assign _zz_284_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001011000)) == (32'b00000000000000000000000001000000)); + assign _zz_285_ = ((decode_INSTRUCTION & _zz_290_) == (32'b00000000000000000000000001010000)); + assign _zz_286_ = (1'b0); + assign _zz_287_ = ({_zz_291_,_zz_292_} != (2'b00)); + assign _zz_288_ = ({_zz_293_,_zz_294_} != (2'b00)); + assign _zz_289_ = {(_zz_295_ != _zz_296_),{_zz_297_,{_zz_298_,_zz_299_}}}; + assign _zz_290_ = (32'b00010000000000000011000001010000); + assign _zz_291_ = ((decode_INSTRUCTION & (32'b00010000000100000011000001010000)) == (32'b00000000000100000000000001010000)); + assign _zz_292_ = ((decode_INSTRUCTION & (32'b00010000010000000011000001010000)) == (32'b00010000000000000000000001010000)); + assign _zz_293_ = ((decode_INSTRUCTION & _zz_300_) == (32'b00000000000000000110000000010000)); + assign _zz_294_ = ((decode_INSTRUCTION & _zz_301_) == (32'b00000000000000000100000000010000)); + assign _zz_295_ = ((decode_INSTRUCTION & _zz_302_) == (32'b00000000000000000010000000010000)); + assign _zz_296_ = (1'b0); + assign _zz_297_ = ((_zz_303_ == _zz_304_) != (1'b0)); + assign _zz_298_ = ({_zz_305_,_zz_306_} != (2'b00)); + assign _zz_299_ = {(_zz_307_ != _zz_308_),{_zz_309_,{_zz_310_,_zz_311_}}}; + assign _zz_300_ = (32'b00000000000000000110000000010100); + assign _zz_301_ = (32'b00000000000000000101000000010100); + assign _zz_302_ = (32'b00000000000000000110000000010100); + assign _zz_303_ = (decode_INSTRUCTION & (32'b00000000000000000001000001001000)); + assign _zz_304_ = (32'b00000000000000000001000000001000); + assign _zz_305_ = _zz_88_; + assign _zz_306_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001110000)) == (32'b00000000000000000000000000100000)); + assign _zz_307_ = {_zz_88_,((decode_INSTRUCTION & _zz_312_) == (32'b00000000000000000000000000000000))}; + assign _zz_308_ = (2'b00); + assign _zz_309_ = (((decode_INSTRUCTION & _zz_313_) == (32'b00000000000000000101000000010000)) != (1'b0)); + assign _zz_310_ = ({_zz_314_,_zz_315_} != (2'b00)); + assign _zz_311_ = {(_zz_316_ != (1'b0)),{(_zz_317_ != _zz_318_),(_zz_319_ != _zz_320_)}}; + assign _zz_312_ = (32'b00000000000000000000000000100000); + assign _zz_313_ = (32'b00000000000000000111000001010100); + assign _zz_314_ = ((decode_INSTRUCTION & (32'b01000000000000000011000001010100)) == (32'b01000000000000000001000000010000)); + assign _zz_315_ = ((decode_INSTRUCTION & (32'b00000000000000000111000001010100)) == (32'b00000000000000000001000000010000)); + assign _zz_316_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000010000)) == (32'b00000000000000000000000000010000)); + assign _zz_317_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000000000)) == (32'b00000000000000000000000000000000)); + assign _zz_318_ = (1'b0); + assign _zz_319_ = {((decode_INSTRUCTION & (32'b00000000000000000001000001010000)) == (32'b00000000000000000001000001010000)),((decode_INSTRUCTION & (32'b00000000000000000010000001010000)) == (32'b00000000000000000010000001010000))}; + assign _zz_320_ = (2'b00); + assign _zz_321_ = (32'b00000000000000000001000001111111); + assign _zz_322_ = (decode_INSTRUCTION & (32'b00000000000000000010000001111111)); + assign _zz_323_ = (32'b00000000000000000010000001110011); + assign _zz_324_ = ((decode_INSTRUCTION & (32'b00000000000000000100000001111111)) == (32'b00000000000000000100000001100011)); + assign _zz_325_ = ((decode_INSTRUCTION & (32'b00000000000000000010000001111111)) == (32'b00000000000000000010000000010011)); + assign _zz_326_ = {((decode_INSTRUCTION & (32'b00000000000000000110000000111111)) == (32'b00000000000000000000000000100011)),{((decode_INSTRUCTION & (32'b00000000000000000010000001111111)) == (32'b00000000000000000000000000000011)),{((decode_INSTRUCTION & _zz_327_) == (32'b00000000000000000000000000000011)),{(_zz_328_ == _zz_329_),{_zz_330_,{_zz_331_,_zz_332_}}}}}}; + assign _zz_327_ = (32'b00000000000000000101000001011111); + assign _zz_328_ = (decode_INSTRUCTION & (32'b00000000000000000111000001111011)); + assign _zz_329_ = (32'b00000000000000000000000001100011); + assign _zz_330_ = ((decode_INSTRUCTION & (32'b00000000000000000110000001111111)) == (32'b00000000000000000000000000001111)); + assign _zz_331_ = ((decode_INSTRUCTION & (32'b11111110000000000000000001111111)) == (32'b00000000000000000000000000110011)); + assign _zz_332_ = {((decode_INSTRUCTION & (32'b10111100000000000111000001111111)) == (32'b00000000000000000101000000010011)),{((decode_INSTRUCTION & (32'b11111100000000000011000001111111)) == (32'b00000000000000000001000000010011)),{((decode_INSTRUCTION & _zz_333_) == (32'b00000000000000000101000000110011)),{(_zz_334_ == _zz_335_),{_zz_336_,{_zz_337_,_zz_338_}}}}}}; + assign _zz_333_ = (32'b10111110000000000111000001111111); + assign _zz_334_ = (decode_INSTRUCTION & (32'b10111110000000000111000001111111)); + assign _zz_335_ = (32'b00000000000000000000000000110011); + assign _zz_336_ = ((decode_INSTRUCTION & (32'b11011111111111111111111111111111)) == (32'b00010000001000000000000001110011)); + assign _zz_337_ = ((decode_INSTRUCTION & (32'b11111111111011111111111111111111)) == (32'b00000000000000000000000001110011)); + assign _zz_338_ = ((decode_INSTRUCTION & (32'b11111111111111111111111111111111)) == (32'b00010000010100000000000001110011)); + initial begin + $readmemb("2-stage-2048-cache.v_toplevel_RegFilePlugin_regFile.bin",RegFilePlugin_regFile); + end + always @ (posedge clk) begin + if(_zz_40_) begin + RegFilePlugin_regFile[execute_RegFilePlugin_regFileWrite_payload_address] <= execute_RegFilePlugin_regFileWrite_payload_data; + end + end + + always @ (posedge clk) begin + if(_zz_99_) begin + _zz_148_ <= RegFilePlugin_regFile[execute_RegFilePlugin_regFileReadAddress1]; + end + end + + always @ (posedge clk) begin + if(_zz_99_) begin + _zz_149_ <= RegFilePlugin_regFile[execute_RegFilePlugin_regFileReadAddress2]; + end + end + + InstructionCache IBusCachedPlugin_cache ( + .io_flush(_zz_130_), + .io_cpu_prefetch_isValid(_zz_131_), + .io_cpu_prefetch_haltIt(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt), + .io_cpu_prefetch_pc(IBusCachedPlugin_iBusRsp_stages_0_input_payload), + .io_cpu_fetch_isValid(_zz_132_), + .io_cpu_fetch_isStuck(_zz_133_), + .io_cpu_fetch_isRemoved(_zz_134_), + .io_cpu_fetch_pc(IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload), + .io_cpu_fetch_data(IBusCachedPlugin_cache_io_cpu_fetch_data), + .io_cpu_fetch_dataBypassValid(IBusCachedPlugin_s1_tightlyCoupledHit), + .io_cpu_fetch_dataBypass(_zz_135_), + .io_cpu_fetch_mmuBus_cmd_isValid(IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_isValid), + .io_cpu_fetch_mmuBus_cmd_virtualAddress(IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_virtualAddress), + .io_cpu_fetch_mmuBus_cmd_bypassTranslation(IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_bypassTranslation), + .io_cpu_fetch_mmuBus_rsp_physicalAddress(IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_virtualAddress), + .io_cpu_fetch_mmuBus_rsp_isIoAccess(_zz_136_), + .io_cpu_fetch_mmuBus_rsp_allowRead(_zz_137_), + .io_cpu_fetch_mmuBus_rsp_allowWrite(_zz_138_), + .io_cpu_fetch_mmuBus_rsp_allowExecute(_zz_139_), + .io_cpu_fetch_mmuBus_rsp_exception(_zz_140_), + .io_cpu_fetch_mmuBus_rsp_refilling(_zz_141_), + .io_cpu_fetch_mmuBus_end(IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_end), + .io_cpu_fetch_mmuBus_busy(_zz_142_), + .io_cpu_fetch_physicalAddress(IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress), + .io_cpu_fetch_cacheMiss(IBusCachedPlugin_cache_io_cpu_fetch_cacheMiss), + .io_cpu_fetch_error(IBusCachedPlugin_cache_io_cpu_fetch_error), + .io_cpu_fetch_mmuRefilling(IBusCachedPlugin_cache_io_cpu_fetch_mmuRefilling), + .io_cpu_fetch_mmuException(IBusCachedPlugin_cache_io_cpu_fetch_mmuException), + .io_cpu_fetch_isUser(_zz_143_), + .io_cpu_fetch_haltIt(IBusCachedPlugin_cache_io_cpu_fetch_haltIt), + .io_cpu_decode_isValid(_zz_144_), + .io_cpu_decode_isStuck(_zz_145_), + .io_cpu_decode_pc(_zz_146_), + .io_cpu_decode_physicalAddress(IBusCachedPlugin_cache_io_cpu_decode_physicalAddress), + .io_cpu_decode_data(IBusCachedPlugin_cache_io_cpu_decode_data), + .io_cpu_fill_valid(_zz_147_), + .io_cpu_fill_payload(IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress), + .io_mem_cmd_valid(IBusCachedPlugin_cache_io_mem_cmd_valid), + .io_mem_cmd_ready(iBus_cmd_ready), + .io_mem_cmd_payload_address(IBusCachedPlugin_cache_io_mem_cmd_payload_address), + .io_mem_cmd_payload_size(IBusCachedPlugin_cache_io_mem_cmd_payload_size), + .io_mem_rsp_valid(iBus_rsp_valid), + .io_mem_rsp_payload_data(iBus_rsp_payload_data), + .io_mem_rsp_payload_error(iBus_rsp_payload_error), + .clk(clk), + .reset(reset) + ); + always @(*) begin + case(_zz_205_) + 2'b00 : begin + _zz_150_ = BranchPlugin_jumpInterface_payload; + end + 2'b01 : begin + _zz_150_ = CsrPlugin_jumpInterface_payload; + end + default : begin + _zz_150_ = IBusCachedPlugin_redoBranch_payload; + end + endcase + end + + always @(*) begin + case(_zz_124_) + 2'b00 : begin + _zz_151_ = DBusSimplePlugin_memoryExceptionPort_payload_code; + _zz_152_ = DBusSimplePlugin_memoryExceptionPort_payload_badAddr; + end + 2'b01 : begin + _zz_151_ = BranchPlugin_branchExceptionPort_payload_code; + _zz_152_ = BranchPlugin_branchExceptionPort_payload_badAddr; + end + default : begin + _zz_151_ = CsrPlugin_selfException_payload_code; + _zz_152_ = CsrPlugin_selfException_payload_badAddr; + end + endcase + end + + `ifndef SYNTHESIS + always @(*) begin + case(decode_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : decode_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : decode_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : decode_ENV_CTRL_string = "ECALL "; + `EnvCtrlEnum_defaultEncoding_EBREAK : decode_ENV_CTRL_string = "EBREAK"; + default : decode_ENV_CTRL_string = "??????"; + endcase + end + always @(*) begin + case(_zz_1_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_1__string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_1__string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_1__string = "ECALL "; + `EnvCtrlEnum_defaultEncoding_EBREAK : _zz_1__string = "EBREAK"; + default : _zz_1__string = "??????"; + endcase + end + always @(*) begin + case(_zz_2_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_2__string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_2__string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_2__string = "ECALL "; + `EnvCtrlEnum_defaultEncoding_EBREAK : _zz_2__string = "EBREAK"; + default : _zz_2__string = "??????"; + endcase + end + always @(*) begin + case(_zz_3_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_3__string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_3__string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_3__string = "ECALL "; + `EnvCtrlEnum_defaultEncoding_EBREAK : _zz_3__string = "EBREAK"; + default : _zz_3__string = "??????"; + endcase + end + always @(*) begin + case(decode_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : decode_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : decode_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : decode_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : decode_SRC2_CTRL_string = "PC "; + default : decode_SRC2_CTRL_string = "???"; + endcase + end + always @(*) begin + case(_zz_4_) + `Src2CtrlEnum_defaultEncoding_RS : _zz_4__string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_4__string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_4__string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_4__string = "PC "; + default : _zz_4__string = "???"; + endcase + end + always @(*) begin + case(_zz_5_) + `Src2CtrlEnum_defaultEncoding_RS : _zz_5__string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_5__string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_5__string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_5__string = "PC "; + default : _zz_5__string = "???"; + endcase + end + always @(*) begin + case(_zz_6_) + `Src2CtrlEnum_defaultEncoding_RS : _zz_6__string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_6__string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_6__string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_6__string = "PC "; + default : _zz_6__string = "???"; + endcase + end + always @(*) begin + case(decode_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : decode_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : decode_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : decode_SRC1_CTRL_string = "URS1 "; + default : decode_SRC1_CTRL_string = "????????????"; + endcase + end + always @(*) begin + case(_zz_7_) + `Src1CtrlEnum_defaultEncoding_RS : _zz_7__string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_7__string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_7__string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_7__string = "URS1 "; + default : _zz_7__string = "????????????"; + endcase + end + always @(*) begin + case(_zz_8_) + `Src1CtrlEnum_defaultEncoding_RS : _zz_8__string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_8__string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_8__string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_8__string = "URS1 "; + default : _zz_8__string = "????????????"; + endcase + end + always @(*) begin + case(_zz_9_) + `Src1CtrlEnum_defaultEncoding_RS : _zz_9__string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_9__string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_9__string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_9__string = "URS1 "; + default : _zz_9__string = "????????????"; + endcase + end + always @(*) begin + case(decode_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : decode_ALU_CTRL_string = "BITWISE "; + default : decode_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(_zz_10_) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_10__string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_10__string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_10__string = "BITWISE "; + default : _zz_10__string = "????????"; + endcase + end + always @(*) begin + case(_zz_11_) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_11__string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_11__string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_11__string = "BITWISE "; + default : _zz_11__string = "????????"; + endcase + end + always @(*) begin + case(_zz_12_) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_12__string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_12__string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_12__string = "BITWISE "; + default : _zz_12__string = "????????"; + endcase + end + always @(*) begin + case(decode_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : decode_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : decode_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : decode_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : decode_BRANCH_CTRL_string = "JALR"; + default : decode_BRANCH_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_13_) + `BranchCtrlEnum_defaultEncoding_INC : _zz_13__string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_13__string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_13__string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_13__string = "JALR"; + default : _zz_13__string = "????"; + endcase + end + always @(*) begin + case(_zz_14_) + `BranchCtrlEnum_defaultEncoding_INC : _zz_14__string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_14__string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_14__string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_14__string = "JALR"; + default : _zz_14__string = "????"; + endcase + end + always @(*) begin + case(_zz_15_) + `BranchCtrlEnum_defaultEncoding_INC : _zz_15__string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_15__string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_15__string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_15__string = "JALR"; + default : _zz_15__string = "????"; + endcase + end + always @(*) begin + case(decode_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 "; + default : decode_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_16_) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_16__string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_16__string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_16__string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_16__string = "SRA_1 "; + default : _zz_16__string = "?????????"; + endcase + end + always @(*) begin + case(_zz_17_) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_17__string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_17__string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_17__string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_17__string = "SRA_1 "; + default : _zz_17__string = "?????????"; + endcase + end + always @(*) begin + case(_zz_18_) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_18__string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_18__string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_18__string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_18__string = "SRA_1 "; + default : _zz_18__string = "?????????"; + endcase + end + always @(*) begin + case(decode_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1"; + default : decode_ALU_BITWISE_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_19_) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_19__string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_19__string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_19__string = "AND_1"; + default : _zz_19__string = "?????"; + endcase + end + always @(*) begin + case(_zz_20_) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_20__string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_20__string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_20__string = "AND_1"; + default : _zz_20__string = "?????"; + endcase + end + always @(*) begin + case(_zz_21_) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_21__string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_21__string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_21__string = "AND_1"; + default : _zz_21__string = "?????"; + endcase + end + always @(*) begin + case(execute_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : execute_ENV_CTRL_string = "ECALL "; + `EnvCtrlEnum_defaultEncoding_EBREAK : execute_ENV_CTRL_string = "EBREAK"; + default : execute_ENV_CTRL_string = "??????"; + endcase + end + always @(*) begin + case(_zz_24_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_24__string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_24__string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_24__string = "ECALL "; + `EnvCtrlEnum_defaultEncoding_EBREAK : _zz_24__string = "EBREAK"; + default : _zz_24__string = "??????"; + endcase + end + always @(*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : execute_BRANCH_CTRL_string = "JALR"; + default : execute_BRANCH_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_26_) + `BranchCtrlEnum_defaultEncoding_INC : _zz_26__string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_26__string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_26__string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_26__string = "JALR"; + default : _zz_26__string = "????"; + endcase + end + always @(*) begin + case(execute_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : execute_SHIFT_CTRL_string = "SRA_1 "; + default : execute_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_28_) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_28__string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_28__string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_28__string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_28__string = "SRA_1 "; + default : _zz_28__string = "?????????"; + endcase + end + always @(*) begin + case(execute_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : execute_SRC2_CTRL_string = "PC "; + default : execute_SRC2_CTRL_string = "???"; + endcase + end + always @(*) begin + case(_zz_32_) + `Src2CtrlEnum_defaultEncoding_RS : _zz_32__string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_32__string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_32__string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_32__string = "PC "; + default : _zz_32__string = "???"; + endcase + end + always @(*) begin + case(execute_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : execute_SRC1_CTRL_string = "URS1 "; + default : execute_SRC1_CTRL_string = "????????????"; + endcase + end + always @(*) begin + case(_zz_34_) + `Src1CtrlEnum_defaultEncoding_RS : _zz_34__string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_34__string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_34__string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_34__string = "URS1 "; + default : _zz_34__string = "????????????"; + endcase + end + always @(*) begin + case(execute_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : execute_ALU_CTRL_string = "BITWISE "; + default : execute_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(_zz_37_) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_37__string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_37__string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_37__string = "BITWISE "; + default : _zz_37__string = "????????"; + endcase + end + always @(*) begin + case(execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : execute_ALU_BITWISE_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_39_) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_39__string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_39__string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_39__string = "AND_1"; + default : _zz_39__string = "?????"; + endcase + end + always @(*) begin + case(_zz_45_) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_45__string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_45__string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_45__string = "AND_1"; + default : _zz_45__string = "?????"; + endcase + end + always @(*) begin + case(_zz_50_) + `Src1CtrlEnum_defaultEncoding_RS : _zz_50__string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_50__string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_50__string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_50__string = "URS1 "; + default : _zz_50__string = "????????????"; + endcase + end + always @(*) begin + case(_zz_51_) + `BranchCtrlEnum_defaultEncoding_INC : _zz_51__string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_51__string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_51__string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_51__string = "JALR"; + default : _zz_51__string = "????"; + endcase + end + always @(*) begin + case(_zz_52_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_52__string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_52__string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_52__string = "ECALL "; + `EnvCtrlEnum_defaultEncoding_EBREAK : _zz_52__string = "EBREAK"; + default : _zz_52__string = "??????"; + endcase + end + always @(*) begin + case(_zz_53_) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_53__string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_53__string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_53__string = "BITWISE "; + default : _zz_53__string = "????????"; + endcase + end + always @(*) begin + case(_zz_55_) + `Src2CtrlEnum_defaultEncoding_RS : _zz_55__string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_55__string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_55__string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_55__string = "PC "; + default : _zz_55__string = "???"; + endcase + end + always @(*) begin + case(_zz_56_) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_56__string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_56__string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_56__string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_56__string = "SRA_1 "; + default : _zz_56__string = "?????????"; + endcase + end + always @(*) begin + case(_zz_92_) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_92__string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_92__string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_92__string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_92__string = "SRA_1 "; + default : _zz_92__string = "?????????"; + endcase + end + always @(*) begin + case(_zz_93_) + `Src2CtrlEnum_defaultEncoding_RS : _zz_93__string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_93__string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_93__string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_93__string = "PC "; + default : _zz_93__string = "???"; + endcase + end + always @(*) begin + case(_zz_94_) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_94__string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_94__string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_94__string = "BITWISE "; + default : _zz_94__string = "????????"; + endcase + end + always @(*) begin + case(_zz_95_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_95__string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_95__string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_95__string = "ECALL "; + `EnvCtrlEnum_defaultEncoding_EBREAK : _zz_95__string = "EBREAK"; + default : _zz_95__string = "??????"; + endcase + end + always @(*) begin + case(_zz_96_) + `BranchCtrlEnum_defaultEncoding_INC : _zz_96__string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_96__string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_96__string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_96__string = "JALR"; + default : _zz_96__string = "????"; + endcase + end + always @(*) begin + case(_zz_97_) + `Src1CtrlEnum_defaultEncoding_RS : _zz_97__string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_97__string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_97__string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_97__string = "URS1 "; + default : _zz_97__string = "????????????"; + endcase + end + always @(*) begin + case(_zz_98_) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_98__string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_98__string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_98__string = "AND_1"; + default : _zz_98__string = "?????"; + endcase + end + always @(*) begin + case(decode_to_execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : decode_to_execute_ALU_BITWISE_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(decode_to_execute_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; + default : decode_to_execute_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(decode_to_execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : decode_to_execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : decode_to_execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR"; + default : decode_to_execute_BRANCH_CTRL_string = "????"; + endcase + end + always @(*) begin + case(decode_to_execute_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE "; + default : decode_to_execute_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(decode_to_execute_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : decode_to_execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : decode_to_execute_SRC1_CTRL_string = "URS1 "; + default : decode_to_execute_SRC1_CTRL_string = "????????????"; + endcase + end + always @(*) begin + case(decode_to_execute_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : decode_to_execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : decode_to_execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : decode_to_execute_SRC2_CTRL_string = "PC "; + default : decode_to_execute_SRC2_CTRL_string = "???"; + endcase + end + always @(*) begin + case(decode_to_execute_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : decode_to_execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : decode_to_execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : decode_to_execute_ENV_CTRL_string = "ECALL "; + `EnvCtrlEnum_defaultEncoding_EBREAK : decode_to_execute_ENV_CTRL_string = "EBREAK"; + default : decode_to_execute_ENV_CTRL_string = "??????"; + endcase + end + `endif + + assign decode_CSR_WRITE_OPCODE = _zz_23_; + assign decode_SRC_LESS_UNSIGNED = _zz_47_; + assign decode_ENV_CTRL = _zz_1_; + assign _zz_2_ = _zz_3_; + assign execute_FORMAL_PC_NEXT = decode_to_execute_FORMAL_PC_NEXT; + assign decode_FORMAL_PC_NEXT = _zz_67_; + assign decode_SRC2_CTRL = _zz_4_; + assign _zz_5_ = _zz_6_; + assign decode_IS_CSR = _zz_57_; + assign decode_MEMORY_ENABLE = _zz_49_; + assign decode_SRC1_CTRL = _zz_7_; + assign _zz_8_ = _zz_9_; + assign decode_CSR_READ_OPCODE = _zz_22_; + assign execute_REGFILE_WRITE_VALID = decode_to_execute_REGFILE_WRITE_VALID; + assign decode_ALU_CTRL = _zz_10_; + assign _zz_11_ = _zz_12_; + assign decode_SRC2_FORCE_ZERO = _zz_36_; + assign decode_MEMORY_STORE = _zz_48_; + assign decode_BRANCH_CTRL = _zz_13_; + assign _zz_14_ = _zz_15_; + assign decode_SHIFT_CTRL = _zz_16_; + assign _zz_17_ = _zz_18_; + assign decode_ALU_BITWISE_CTRL = _zz_19_; + assign _zz_20_ = _zz_21_; + assign execute_CSR_READ_OPCODE = decode_to_execute_CSR_READ_OPCODE; + assign execute_CSR_WRITE_OPCODE = decode_to_execute_CSR_WRITE_OPCODE; + assign execute_IS_CSR = decode_to_execute_IS_CSR; + assign execute_ENV_CTRL = _zz_24_; + assign execute_BRANCH_CALC = _zz_25_; + assign execute_BRANCH_DO = _zz_27_; + assign execute_PC = decode_to_execute_PC; + assign execute_RS1 = _zz_42_; + assign execute_BRANCH_CTRL = _zz_26_; + assign execute_SHIFT_CTRL = _zz_28_; + assign execute_SRC_LESS_UNSIGNED = decode_to_execute_SRC_LESS_UNSIGNED; + assign execute_SRC2_FORCE_ZERO = decode_to_execute_SRC2_FORCE_ZERO; + assign execute_SRC_USE_SUB_LESS = decode_to_execute_SRC_USE_SUB_LESS; + assign execute_SRC2_CTRL = _zz_32_; + assign execute_SRC1_CTRL = _zz_34_; + assign decode_SRC_USE_SUB_LESS = _zz_46_; + assign decode_SRC_ADD_ZERO = _zz_43_; + assign execute_SRC_ADD_SUB = _zz_31_; + assign execute_SRC_LESS = _zz_29_; + assign execute_ALU_CTRL = _zz_37_; + assign execute_SRC2 = _zz_33_; + assign execute_SRC1 = _zz_35_; + assign execute_ALU_BITWISE_CTRL = _zz_39_; + always @ (*) begin + _zz_40_ = 1'b0; + if(execute_RegFilePlugin_regFileWrite_valid)begin + _zz_40_ = 1'b1; + end + end + + always @ (*) begin + decode_REGFILE_WRITE_VALID = _zz_44_; + if((decode_INSTRUCTION[11 : 7] == (5'b00000)))begin + decode_REGFILE_WRITE_VALID = 1'b0; + end + end + + assign decode_LEGAL_INSTRUCTION = _zz_58_; + assign decode_INSTRUCTION_READY = 1'b1; + always @ (*) begin + _zz_59_ = execute_REGFILE_WRITE_DATA; + execute_arbitration_haltItself = 1'b0; + if(((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! dBus_cmd_ready)) && (! execute_DBusSimplePlugin_skipCmd)) && (! execute_DBusSimplePlugin_cmdSent)))begin + execute_arbitration_haltItself = 1'b1; + end + if((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! execute_MEMORY_STORE)) && (! dBus_rsp_ready)))begin + execute_arbitration_haltItself = 1'b1; + end + if((execute_arbitration_isValid && execute_MEMORY_ENABLE))begin + _zz_59_ = execute_DBusSimplePlugin_rspFormated; + end + if(_zz_153_)begin + _zz_59_ = _zz_107_; + if(_zz_154_)begin + if(! execute_LightShifterPlugin_done) begin + execute_arbitration_haltItself = 1'b1; + end + end + end + if((execute_arbitration_isValid && execute_IS_CSR))begin + _zz_59_ = execute_CsrPlugin_readData; + if(execute_CsrPlugin_blockedBySideEffects)begin + execute_arbitration_haltItself = 1'b1; + end + end + end + + assign execute_MEMORY_ADDRESS_LOW = _zz_61_; + assign execute_MEMORY_READ_DATA = _zz_60_; + assign execute_REGFILE_WRITE_DATA = _zz_38_; + assign execute_SRC_ADD = _zz_30_; + assign execute_RS2 = _zz_41_; + assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION; + assign execute_MEMORY_STORE = decode_to_execute_MEMORY_STORE; + assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE; + assign execute_ALIGNEMENT_FAULT = _zz_62_; + assign decode_FLUSH_ALL = _zz_54_; + always @ (*) begin + IBusCachedPlugin_rsp_issueDetected = _zz_63_; + _zz_64_ = _zz_65_; + IBusCachedPlugin_decodeExceptionPort_valid = 1'b0; + IBusCachedPlugin_decodeExceptionPort_payload_code = (4'bxxxx); + if(((_zz_132_ && IBusCachedPlugin_cache_io_cpu_fetch_mmuException) && (! _zz_65_)))begin + _zz_64_ = 1'b1; + IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; + IBusCachedPlugin_decodeExceptionPort_payload_code = (4'b1100); + end + if(((_zz_132_ && IBusCachedPlugin_cache_io_cpu_fetch_error) && (! _zz_63_)))begin + IBusCachedPlugin_rsp_issueDetected = 1'b1; + IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; + IBusCachedPlugin_decodeExceptionPort_payload_code = (4'b0001); + end + if(IBusCachedPlugin_fetcherHalt)begin + IBusCachedPlugin_decodeExceptionPort_valid = 1'b0; + end + end + + always @ (*) begin + _zz_63_ = _zz_64_; + _zz_65_ = 1'b0; + IBusCachedPlugin_rsp_redoFetch = 1'b0; + _zz_147_ = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_fetch_mmuRefilling)); + if(((_zz_132_ && IBusCachedPlugin_cache_io_cpu_fetch_mmuRefilling) && (! 1'b0)))begin + _zz_65_ = 1'b1; + IBusCachedPlugin_rsp_redoFetch = 1'b1; + end + if(((_zz_132_ && IBusCachedPlugin_cache_io_cpu_fetch_cacheMiss) && (! _zz_64_)))begin + _zz_63_ = 1'b1; + _zz_147_ = 1'b1; + IBusCachedPlugin_rsp_redoFetch = 1'b1; + end + if((! IBusCachedPlugin_iBusRsp_readyForError))begin + IBusCachedPlugin_rsp_redoFetch = 1'b0; + end + if((! IBusCachedPlugin_iBusRsp_readyForError))begin + _zz_147_ = 1'b0; + end + end + + always @ (*) begin + _zz_66_ = decode_FORMAL_PC_NEXT; + if(IBusCachedPlugin_redoBranch_valid)begin + _zz_66_ = IBusCachedPlugin_redoBranch_payload; + end + end + + assign decode_PC = _zz_69_; + assign decode_INSTRUCTION = _zz_68_; + assign decode_arbitration_haltItself = 1'b0; + always @ (*) begin + decode_arbitration_haltByOther = 1'b0; + if(CsrPlugin_interrupt)begin + decode_arbitration_haltByOther = decode_arbitration_isValid; + end + if(((execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)) != (1'b0)))begin + decode_arbitration_haltByOther = 1'b1; + end + end + + always @ (*) begin + decode_arbitration_removeIt = 1'b0; + if(_zz_155_)begin + decode_arbitration_removeIt = 1'b1; + end + if(decode_arbitration_isFlushed)begin + decode_arbitration_removeIt = 1'b1; + end + end + + always @ (*) begin + decode_arbitration_flushAll = 1'b0; + execute_arbitration_removeIt = 1'b0; + IBusCachedPlugin_fetcherHalt = 1'b0; + CsrPlugin_jumpInterface_valid = 1'b0; + CsrPlugin_jumpInterface_payload = (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx); + if(BranchPlugin_jumpInterface_valid)begin + decode_arbitration_flushAll = 1'b1; + end + CsrPlugin_exceptionPortCtrl_exceptionValids_execute = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; + if(_zz_156_)begin + decode_arbitration_flushAll = 1'b1; + execute_arbitration_removeIt = 1'b1; + CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b1; + end + if(execute_arbitration_isFlushed)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b0; + end + if(({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode} != (2'b00)))begin + IBusCachedPlugin_fetcherHalt = 1'b1; + end + if(_zz_157_)begin + IBusCachedPlugin_fetcherHalt = 1'b1; + CsrPlugin_jumpInterface_valid = 1'b1; + CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,(2'b00)}; + decode_arbitration_flushAll = 1'b1; + end + if(_zz_158_)begin + IBusCachedPlugin_fetcherHalt = 1'b1; + CsrPlugin_jumpInterface_valid = 1'b1; + decode_arbitration_flushAll = 1'b1; + case(_zz_159_) + 2'b11 : begin + CsrPlugin_jumpInterface_payload = CsrPlugin_mepc; + end + default : begin + end + endcase + end + if(execute_arbitration_isFlushed)begin + execute_arbitration_removeIt = 1'b1; + end + end + + assign execute_arbitration_haltByOther = 1'b0; + assign execute_arbitration_flushAll = 1'b0; + assign IBusCachedPlugin_fetcherflushIt = 1'b0; + always @ (*) begin + IBusCachedPlugin_incomingInstruction = 1'b0; + if(IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid)begin + IBusCachedPlugin_incomingInstruction = 1'b1; + end + end + + assign CsrPlugin_forceMachineWire = 1'b0; + assign CsrPlugin_allowInterrupts = 1'b1; + assign CsrPlugin_allowException = 1'b1; + assign IBusCachedPlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,IBusCachedPlugin_redoBranch_valid}} != (3'b000)); + assign _zz_70_ = {IBusCachedPlugin_redoBranch_valid,{CsrPlugin_jumpInterface_valid,BranchPlugin_jumpInterface_valid}}; + assign _zz_71_ = (_zz_70_ & (~ _zz_165_)); + assign _zz_72_ = _zz_71_[1]; + assign _zz_73_ = _zz_71_[2]; + assign IBusCachedPlugin_jump_pcLoad_payload = _zz_150_; + assign _zz_74_ = (! IBusCachedPlugin_fetcherHalt); + assign IBusCachedPlugin_fetchPc_output_valid = (IBusCachedPlugin_fetchPc_preOutput_valid && _zz_74_); + assign IBusCachedPlugin_fetchPc_preOutput_ready = (IBusCachedPlugin_fetchPc_output_ready && _zz_74_); + assign IBusCachedPlugin_fetchPc_output_payload = IBusCachedPlugin_fetchPc_preOutput_payload; + always @ (*) begin + IBusCachedPlugin_fetchPc_propagatePc = 1'b0; + if((IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid && IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready))begin + IBusCachedPlugin_fetchPc_propagatePc = 1'b1; + end + end + + always @ (*) begin + IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_167_); + IBusCachedPlugin_fetchPc_samplePcNext = 1'b0; + if(IBusCachedPlugin_fetchPc_propagatePc)begin + IBusCachedPlugin_fetchPc_samplePcNext = 1'b1; + end + if(IBusCachedPlugin_jump_pcLoad_valid)begin + IBusCachedPlugin_fetchPc_samplePcNext = 1'b1; + IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_jump_pcLoad_payload; + end + if(_zz_160_)begin + IBusCachedPlugin_fetchPc_samplePcNext = 1'b1; + end + IBusCachedPlugin_fetchPc_pc[0] = 1'b0; + IBusCachedPlugin_fetchPc_pc[1] = 1'b0; + end + + assign IBusCachedPlugin_fetchPc_preOutput_valid = _zz_75_; + assign IBusCachedPlugin_fetchPc_preOutput_payload = IBusCachedPlugin_fetchPc_pc; + assign IBusCachedPlugin_iBusRsp_stages_0_input_valid = IBusCachedPlugin_fetchPc_output_valid; + assign IBusCachedPlugin_fetchPc_output_ready = IBusCachedPlugin_iBusRsp_stages_0_input_ready; + assign IBusCachedPlugin_iBusRsp_stages_0_input_payload = IBusCachedPlugin_fetchPc_output_payload; + assign IBusCachedPlugin_iBusRsp_stages_0_inputSample = 1'b1; + always @ (*) begin + IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b0; + if(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt)begin + IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b1; + end + end + + assign _zz_76_ = (! IBusCachedPlugin_iBusRsp_stages_0_halt); + assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_76_); + assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_76_); + assign IBusCachedPlugin_iBusRsp_stages_0_output_payload = IBusCachedPlugin_iBusRsp_stages_0_input_payload; + always @ (*) begin + IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt = 1'b0; + if(IBusCachedPlugin_cache_io_cpu_fetch_haltIt)begin + IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt = 1'b1; + end + if((IBusCachedPlugin_rsp_issueDetected || IBusCachedPlugin_rsp_iBusRspOutputHalt))begin + IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt = 1'b1; + end + end + + assign _zz_77_ = (! IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt); + assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready = (IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_ready && _zz_77_); + assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_valid = (IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid && _zz_77_); + assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_payload = IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload; + assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_78_; + assign _zz_78_ = ((1'b0 && (! _zz_79_)) || IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready); + assign _zz_79_ = _zz_80_; + assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid = _zz_79_; + assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload = IBusCachedPlugin_fetchPc_pcReg; + always @ (*) begin + IBusCachedPlugin_iBusRsp_readyForError = 1'b1; + if((! IBusCachedPlugin_pcValids_0))begin + IBusCachedPlugin_iBusRsp_readyForError = 1'b0; + end + end + + assign IBusCachedPlugin_pcValids_0 = IBusCachedPlugin_injector_nextPcCalc_valids_0; + assign IBusCachedPlugin_pcValids_1 = IBusCachedPlugin_injector_nextPcCalc_valids_1; + assign IBusCachedPlugin_iBusRsp_decodeInput_ready = (! decode_arbitration_isStuck); + assign decode_arbitration_isValid = (IBusCachedPlugin_iBusRsp_decodeInput_valid && (! IBusCachedPlugin_injector_decodeRemoved)); + assign _zz_69_ = IBusCachedPlugin_iBusRsp_decodeInput_payload_pc; + assign _zz_68_ = IBusCachedPlugin_iBusRsp_decodeInput_payload_rsp_inst; + assign _zz_67_ = (decode_PC + (32'b00000000000000000000000000000100)); + assign iBus_cmd_valid = IBusCachedPlugin_cache_io_mem_cmd_valid; + always @ (*) begin + iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; + iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; + end + + assign iBus_cmd_payload_size = IBusCachedPlugin_cache_io_mem_cmd_payload_size; + assign IBusCachedPlugin_s0_tightlyCoupledHit = 1'b0; + assign _zz_131_ = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); + assign _zz_134_ = (IBusCachedPlugin_jump_pcLoad_valid || IBusCachedPlugin_fetcherflushIt); + assign _zz_135_ = (32'b00000000000000000000000000000000); + assign _zz_132_ = (IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); + assign _zz_133_ = (! IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready); + assign _zz_143_ = (CsrPlugin_privilege == (2'b00)); + assign IBusCachedPlugin_rsp_iBusRspOutputHalt = 1'b0; + assign IBusCachedPlugin_decodeExceptionPort_payload_badAddr = {IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload[31 : 2],(2'b00)}; + assign IBusCachedPlugin_redoBranch_valid = IBusCachedPlugin_rsp_redoFetch; + assign IBusCachedPlugin_redoBranch_payload = IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload; + assign IBusCachedPlugin_iBusRsp_decodeInput_valid = IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_valid; + assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_ready = IBusCachedPlugin_iBusRsp_decodeInput_ready; + assign IBusCachedPlugin_iBusRsp_decodeInput_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_fetch_data; + assign IBusCachedPlugin_iBusRsp_decodeInput_payload_pc = IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_payload; + assign _zz_139_ = 1'b1; + assign _zz_137_ = 1'b1; + assign _zz_138_ = 1'b1; + assign _zz_136_ = 1'b0; + assign _zz_140_ = 1'b0; + assign _zz_141_ = 1'b0; + assign _zz_142_ = 1'b0; + assign _zz_130_ = (decode_arbitration_isValid && decode_FLUSH_ALL); + assign _zz_62_ = (((dBus_cmd_payload_size == (2'b10)) && (dBus_cmd_payload_address[1 : 0] != (2'b00))) || ((dBus_cmd_payload_size == (2'b01)) && (dBus_cmd_payload_address[0 : 0] != (1'b0)))); + always @ (*) begin + execute_DBusSimplePlugin_skipCmd = 1'b0; + if(execute_ALIGNEMENT_FAULT)begin + execute_DBusSimplePlugin_skipCmd = 1'b1; + end + end + + assign dBus_cmd_valid = (((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! execute_arbitration_isStuckByOthers)) && (! execute_arbitration_isFlushed)) && (! execute_DBusSimplePlugin_skipCmd)) && (! execute_DBusSimplePlugin_cmdSent)); + assign dBus_cmd_payload_wr = execute_MEMORY_STORE; + assign dBus_cmd_payload_size = execute_INSTRUCTION[13 : 12]; + always @ (*) begin + case(dBus_cmd_payload_size) + 2'b00 : begin + _zz_81_ = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; + end + 2'b01 : begin + _zz_81_ = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; + end + default : begin + _zz_81_ = execute_RS2[31 : 0]; + end + endcase + end + + assign dBus_cmd_payload_data = _zz_81_; + assign _zz_61_ = dBus_cmd_payload_address[1 : 0]; + always @ (*) begin + case(dBus_cmd_payload_size) + 2'b00 : begin + _zz_82_ = (4'b0001); + end + 2'b01 : begin + _zz_82_ = (4'b0011); + end + default : begin + _zz_82_ = (4'b1111); + end + endcase + end + + assign execute_DBusSimplePlugin_formalMask = (_zz_82_ <<< dBus_cmd_payload_address[1 : 0]); + assign dBus_cmd_payload_address = execute_SRC_ADD; + assign _zz_60_ = dBus_rsp_data; + always @ (*) begin + DBusSimplePlugin_memoryExceptionPort_valid = 1'b0; + DBusSimplePlugin_memoryExceptionPort_payload_code = (4'bxxxx); + if(execute_ALIGNEMENT_FAULT)begin + DBusSimplePlugin_memoryExceptionPort_payload_code = {1'd0, _zz_168_}; + DBusSimplePlugin_memoryExceptionPort_valid = 1'b1; + end + if((! ((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (1'b0 || (! execute_arbitration_isStuckByOthers)))))begin + DBusSimplePlugin_memoryExceptionPort_valid = 1'b0; + end + end + + assign DBusSimplePlugin_memoryExceptionPort_payload_badAddr = execute_REGFILE_WRITE_DATA; + always @ (*) begin + execute_DBusSimplePlugin_rspShifted = execute_MEMORY_READ_DATA; + case(execute_MEMORY_ADDRESS_LOW) + 2'b01 : begin + execute_DBusSimplePlugin_rspShifted[7 : 0] = execute_MEMORY_READ_DATA[15 : 8]; + end + 2'b10 : begin + execute_DBusSimplePlugin_rspShifted[15 : 0] = execute_MEMORY_READ_DATA[31 : 16]; + end + 2'b11 : begin + execute_DBusSimplePlugin_rspShifted[7 : 0] = execute_MEMORY_READ_DATA[31 : 24]; + end + default : begin + end + endcase + end + + assign _zz_83_ = (execute_DBusSimplePlugin_rspShifted[7] && (! execute_INSTRUCTION[14])); + always @ (*) begin + _zz_84_[31] = _zz_83_; + _zz_84_[30] = _zz_83_; + _zz_84_[29] = _zz_83_; + _zz_84_[28] = _zz_83_; + _zz_84_[27] = _zz_83_; + _zz_84_[26] = _zz_83_; + _zz_84_[25] = _zz_83_; + _zz_84_[24] = _zz_83_; + _zz_84_[23] = _zz_83_; + _zz_84_[22] = _zz_83_; + _zz_84_[21] = _zz_83_; + _zz_84_[20] = _zz_83_; + _zz_84_[19] = _zz_83_; + _zz_84_[18] = _zz_83_; + _zz_84_[17] = _zz_83_; + _zz_84_[16] = _zz_83_; + _zz_84_[15] = _zz_83_; + _zz_84_[14] = _zz_83_; + _zz_84_[13] = _zz_83_; + _zz_84_[12] = _zz_83_; + _zz_84_[11] = _zz_83_; + _zz_84_[10] = _zz_83_; + _zz_84_[9] = _zz_83_; + _zz_84_[8] = _zz_83_; + _zz_84_[7 : 0] = execute_DBusSimplePlugin_rspShifted[7 : 0]; + end + + assign _zz_85_ = (execute_DBusSimplePlugin_rspShifted[15] && (! execute_INSTRUCTION[14])); + always @ (*) begin + _zz_86_[31] = _zz_85_; + _zz_86_[30] = _zz_85_; + _zz_86_[29] = _zz_85_; + _zz_86_[28] = _zz_85_; + _zz_86_[27] = _zz_85_; + _zz_86_[26] = _zz_85_; + _zz_86_[25] = _zz_85_; + _zz_86_[24] = _zz_85_; + _zz_86_[23] = _zz_85_; + _zz_86_[22] = _zz_85_; + _zz_86_[21] = _zz_85_; + _zz_86_[20] = _zz_85_; + _zz_86_[19] = _zz_85_; + _zz_86_[18] = _zz_85_; + _zz_86_[17] = _zz_85_; + _zz_86_[16] = _zz_85_; + _zz_86_[15 : 0] = execute_DBusSimplePlugin_rspShifted[15 : 0]; + end + + always @ (*) begin + case(_zz_163_) + 2'b00 : begin + execute_DBusSimplePlugin_rspFormated = _zz_84_; + end + 2'b01 : begin + execute_DBusSimplePlugin_rspFormated = _zz_86_; + end + default : begin + execute_DBusSimplePlugin_rspFormated = execute_DBusSimplePlugin_rspShifted; + end + endcase + end + + assign _zz_88_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000000100)) == (32'b00000000000000000000000000000100)); + assign _zz_89_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001001000)) == (32'b00000000000000000000000001001000)); + assign _zz_90_ = ((decode_INSTRUCTION & (32'b00000000000000000100000001010000)) == (32'b00000000000000000100000001010000)); + assign _zz_91_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001010000)) == (32'b00000000000000000000000000010000)); + assign _zz_87_ = {(_zz_91_ != (1'b0)),{({_zz_206_,_zz_207_} != (2'b00)),{({_zz_208_,_zz_209_} != (6'b000000)),{(_zz_210_ != _zz_211_),{_zz_212_,{_zz_213_,_zz_214_}}}}}}; + assign _zz_58_ = ({((decode_INSTRUCTION & (32'b00000000000000000000000001011111)) == (32'b00000000000000000000000000010111)),{((decode_INSTRUCTION & (32'b00000000000000000000000001111111)) == (32'b00000000000000000000000001101111)),{((decode_INSTRUCTION & (32'b00000000000000000001000001101111)) == (32'b00000000000000000000000000000011)),{((decode_INSTRUCTION & _zz_321_) == (32'b00000000000000000001000001110011)),{(_zz_322_ == _zz_323_),{_zz_324_,{_zz_325_,_zz_326_}}}}}}} != (20'b00000000000000000000)); + assign _zz_57_ = _zz_169_[0]; + assign _zz_92_ = _zz_87_[4 : 3]; + assign _zz_56_ = _zz_92_; + assign _zz_93_ = _zz_87_[6 : 5]; + assign _zz_55_ = _zz_93_; + assign _zz_54_ = _zz_170_[0]; + assign _zz_94_ = _zz_87_[9 : 8]; + assign _zz_53_ = _zz_94_; + assign _zz_95_ = _zz_87_[11 : 10]; + assign _zz_52_ = _zz_95_; + assign _zz_96_ = _zz_87_[13 : 12]; + assign _zz_51_ = _zz_96_; + assign _zz_97_ = _zz_87_[17 : 16]; + assign _zz_50_ = _zz_97_; + assign _zz_49_ = _zz_171_[0]; + assign _zz_48_ = _zz_172_[0]; + assign _zz_47_ = _zz_173_[0]; + assign _zz_46_ = _zz_174_[0]; + assign _zz_98_ = _zz_87_[23 : 22]; + assign _zz_45_ = _zz_98_; + assign _zz_44_ = _zz_175_[0]; + assign _zz_43_ = _zz_176_[0]; + assign decodeExceptionPort_valid = ((decode_arbitration_isValid && decode_INSTRUCTION_READY) && (! decode_LEGAL_INSTRUCTION)); + assign decodeExceptionPort_payload_code = (4'b0010); + assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION; + assign execute_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION[19 : 15]; + assign execute_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION[24 : 20]; + assign _zz_99_ = (! execute_arbitration_isStuck); + assign execute_RegFilePlugin_rs1Data = _zz_148_; + assign execute_RegFilePlugin_rs2Data = _zz_149_; + assign _zz_42_ = execute_RegFilePlugin_rs1Data; + assign _zz_41_ = execute_RegFilePlugin_rs2Data; + assign execute_RegFilePlugin_regFileWrite_valid = (execute_REGFILE_WRITE_VALID && execute_arbitration_isFiring); + assign execute_RegFilePlugin_regFileWrite_payload_address = execute_INSTRUCTION[11 : 7]; + assign execute_RegFilePlugin_regFileWrite_payload_data = _zz_59_; + always @ (*) begin + case(execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : begin + execute_IntAluPlugin_bitwise = (execute_SRC1 & execute_SRC2); + end + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : begin + execute_IntAluPlugin_bitwise = (execute_SRC1 | execute_SRC2); + end + default : begin + execute_IntAluPlugin_bitwise = (execute_SRC1 ^ execute_SRC2); + end + endcase + end + + always @ (*) begin + case(execute_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_BITWISE : begin + _zz_100_ = execute_IntAluPlugin_bitwise; + end + `AluCtrlEnum_defaultEncoding_SLT_SLTU : begin + _zz_100_ = {31'd0, _zz_177_}; + end + default : begin + _zz_100_ = execute_SRC_ADD_SUB; + end + endcase + end + + assign _zz_38_ = _zz_100_; + assign _zz_36_ = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS)); + always @ (*) begin + case(execute_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : begin + _zz_101_ = execute_RS1; + end + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : begin + _zz_101_ = {29'd0, _zz_178_}; + end + `Src1CtrlEnum_defaultEncoding_IMU : begin + _zz_101_ = {execute_INSTRUCTION[31 : 12],(12'b000000000000)}; + end + default : begin + _zz_101_ = {27'd0, _zz_179_}; + end + endcase + end + + assign _zz_35_ = _zz_101_; + assign _zz_102_ = _zz_180_[11]; + always @ (*) begin + _zz_103_[19] = _zz_102_; + _zz_103_[18] = _zz_102_; + _zz_103_[17] = _zz_102_; + _zz_103_[16] = _zz_102_; + _zz_103_[15] = _zz_102_; + _zz_103_[14] = _zz_102_; + _zz_103_[13] = _zz_102_; + _zz_103_[12] = _zz_102_; + _zz_103_[11] = _zz_102_; + _zz_103_[10] = _zz_102_; + _zz_103_[9] = _zz_102_; + _zz_103_[8] = _zz_102_; + _zz_103_[7] = _zz_102_; + _zz_103_[6] = _zz_102_; + _zz_103_[5] = _zz_102_; + _zz_103_[4] = _zz_102_; + _zz_103_[3] = _zz_102_; + _zz_103_[2] = _zz_102_; + _zz_103_[1] = _zz_102_; + _zz_103_[0] = _zz_102_; + end + + assign _zz_104_ = _zz_181_[11]; + always @ (*) begin + _zz_105_[19] = _zz_104_; + _zz_105_[18] = _zz_104_; + _zz_105_[17] = _zz_104_; + _zz_105_[16] = _zz_104_; + _zz_105_[15] = _zz_104_; + _zz_105_[14] = _zz_104_; + _zz_105_[13] = _zz_104_; + _zz_105_[12] = _zz_104_; + _zz_105_[11] = _zz_104_; + _zz_105_[10] = _zz_104_; + _zz_105_[9] = _zz_104_; + _zz_105_[8] = _zz_104_; + _zz_105_[7] = _zz_104_; + _zz_105_[6] = _zz_104_; + _zz_105_[5] = _zz_104_; + _zz_105_[4] = _zz_104_; + _zz_105_[3] = _zz_104_; + _zz_105_[2] = _zz_104_; + _zz_105_[1] = _zz_104_; + _zz_105_[0] = _zz_104_; + end + + always @ (*) begin + case(execute_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : begin + _zz_106_ = execute_RS2; + end + `Src2CtrlEnum_defaultEncoding_IMI : begin + _zz_106_ = {_zz_103_,execute_INSTRUCTION[31 : 20]}; + end + `Src2CtrlEnum_defaultEncoding_IMS : begin + _zz_106_ = {_zz_105_,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; + end + default : begin + _zz_106_ = execute_PC; + end + endcase + end + + assign _zz_33_ = _zz_106_; + always @ (*) begin + execute_SrcPlugin_addSub = _zz_182_; + if(execute_SRC2_FORCE_ZERO)begin + execute_SrcPlugin_addSub = execute_SRC1; + end + end + + assign execute_SrcPlugin_less = ((execute_SRC1[31] == execute_SRC2[31]) ? execute_SrcPlugin_addSub[31] : (execute_SRC_LESS_UNSIGNED ? execute_SRC2[31] : execute_SRC1[31])); + assign _zz_31_ = execute_SrcPlugin_addSub; + assign _zz_30_ = execute_SrcPlugin_addSub; + assign _zz_29_ = execute_SrcPlugin_less; + assign execute_LightShifterPlugin_isShift = (execute_SHIFT_CTRL != `ShiftCtrlEnum_defaultEncoding_DISABLE_1); + assign execute_LightShifterPlugin_amplitude = (execute_LightShifterPlugin_isActive ? execute_LightShifterPlugin_amplitudeReg : execute_SRC2[4 : 0]); + assign execute_LightShifterPlugin_shiftInput = (execute_LightShifterPlugin_isActive ? execute_LightShifterPlugin_shiftReg : execute_SRC1); + assign execute_LightShifterPlugin_done = (execute_LightShifterPlugin_amplitude[4 : 1] == (4'b0000)); + always @ (*) begin + case(execute_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_SLL_1 : begin + _zz_107_ = (execute_LightShifterPlugin_shiftInput <<< 1); + end + default : begin + _zz_107_ = _zz_189_; + end + endcase + end + + assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2); + assign _zz_108_ = execute_INSTRUCTION[14 : 12]; + always @ (*) begin + if((_zz_108_ == (3'b000))) begin + _zz_109_ = execute_BranchPlugin_eq; + end else if((_zz_108_ == (3'b001))) begin + _zz_109_ = (! execute_BranchPlugin_eq); + end else if((((_zz_108_ & (3'b101)) == (3'b101)))) begin + _zz_109_ = (! execute_SRC_LESS); + end else begin + _zz_109_ = execute_SRC_LESS; + end + end + + always @ (*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : begin + _zz_110_ = 1'b0; + end + `BranchCtrlEnum_defaultEncoding_JAL : begin + _zz_110_ = 1'b1; + end + `BranchCtrlEnum_defaultEncoding_JALR : begin + _zz_110_ = 1'b1; + end + default : begin + _zz_110_ = _zz_109_; + end + endcase + end + + assign _zz_27_ = _zz_110_; + assign execute_BranchPlugin_branch_src1 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JALR) ? execute_RS1 : execute_PC); + assign _zz_111_ = _zz_191_[19]; + always @ (*) begin + _zz_112_[10] = _zz_111_; + _zz_112_[9] = _zz_111_; + _zz_112_[8] = _zz_111_; + _zz_112_[7] = _zz_111_; + _zz_112_[6] = _zz_111_; + _zz_112_[5] = _zz_111_; + _zz_112_[4] = _zz_111_; + _zz_112_[3] = _zz_111_; + _zz_112_[2] = _zz_111_; + _zz_112_[1] = _zz_111_; + _zz_112_[0] = _zz_111_; + end + + assign _zz_113_ = _zz_192_[11]; + always @ (*) begin + _zz_114_[19] = _zz_113_; + _zz_114_[18] = _zz_113_; + _zz_114_[17] = _zz_113_; + _zz_114_[16] = _zz_113_; + _zz_114_[15] = _zz_113_; + _zz_114_[14] = _zz_113_; + _zz_114_[13] = _zz_113_; + _zz_114_[12] = _zz_113_; + _zz_114_[11] = _zz_113_; + _zz_114_[10] = _zz_113_; + _zz_114_[9] = _zz_113_; + _zz_114_[8] = _zz_113_; + _zz_114_[7] = _zz_113_; + _zz_114_[6] = _zz_113_; + _zz_114_[5] = _zz_113_; + _zz_114_[4] = _zz_113_; + _zz_114_[3] = _zz_113_; + _zz_114_[2] = _zz_113_; + _zz_114_[1] = _zz_113_; + _zz_114_[0] = _zz_113_; + end + + assign _zz_115_ = _zz_193_[11]; + always @ (*) begin + _zz_116_[18] = _zz_115_; + _zz_116_[17] = _zz_115_; + _zz_116_[16] = _zz_115_; + _zz_116_[15] = _zz_115_; + _zz_116_[14] = _zz_115_; + _zz_116_[13] = _zz_115_; + _zz_116_[12] = _zz_115_; + _zz_116_[11] = _zz_115_; + _zz_116_[10] = _zz_115_; + _zz_116_[9] = _zz_115_; + _zz_116_[8] = _zz_115_; + _zz_116_[7] = _zz_115_; + _zz_116_[6] = _zz_115_; + _zz_116_[5] = _zz_115_; + _zz_116_[4] = _zz_115_; + _zz_116_[3] = _zz_115_; + _zz_116_[2] = _zz_115_; + _zz_116_[1] = _zz_115_; + _zz_116_[0] = _zz_115_; + end + + always @ (*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_JAL : begin + _zz_117_ = {{_zz_112_,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; + end + `BranchCtrlEnum_defaultEncoding_JALR : begin + _zz_117_ = {_zz_114_,execute_INSTRUCTION[31 : 20]}; + end + default : begin + _zz_117_ = {{_zz_116_,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; + end + endcase + end + + assign execute_BranchPlugin_branch_src2 = _zz_117_; + assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2); + assign _zz_25_ = {execute_BranchPlugin_branchAdder[31 : 1],(1'b0)}; + assign BranchPlugin_jumpInterface_valid = ((execute_arbitration_isValid && (! execute_arbitration_isStuckByOthers)) && execute_BRANCH_DO); + assign BranchPlugin_jumpInterface_payload = execute_BRANCH_CALC; + always @ (*) begin + BranchPlugin_branchExceptionPort_valid = ((execute_arbitration_isValid && execute_BRANCH_DO) && BranchPlugin_jumpInterface_payload[1]); + if(1'b0)begin + BranchPlugin_branchExceptionPort_valid = 1'b0; + end + end + + assign BranchPlugin_branchExceptionPort_payload_code = (4'b0000); + assign BranchPlugin_branchExceptionPort_payload_badAddr = BranchPlugin_jumpInterface_payload; + always @ (*) begin + CsrPlugin_privilege = (2'b11); + if(CsrPlugin_forceMachineWire)begin + CsrPlugin_privilege = (2'b11); + end + end + + assign CsrPlugin_misa_base = (2'b01); + assign CsrPlugin_misa_extensions = (26'b00000000000000000000000000); + assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = (2'b11); + assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege); + assign _zz_118_ = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; + assign _zz_119_ = _zz_194_[0]; + assign _zz_120_ = {CsrPlugin_selfException_valid,{BranchPlugin_branchExceptionPort_valid,DBusSimplePlugin_memoryExceptionPort_valid}}; + assign _zz_121_ = (_zz_120_ & (~ _zz_196_)); + assign _zz_122_ = _zz_121_[1]; + assign _zz_123_ = _zz_121_[2]; + assign _zz_124_ = {_zz_123_,_zz_122_}; + always @ (*) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; + if(_zz_155_)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b1; + end + if(decode_arbitration_isFlushed)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b0; + end + end + + assign CsrPlugin_exceptionPendings_0 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; + assign CsrPlugin_exceptionPendings_1 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; + always @ (*) begin + CsrPlugin_interrupt = 1'b0; + CsrPlugin_interruptCode = (4'bxxxx); + CsrPlugin_interruptTargetPrivilege = (2'bxx); + if((CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < (2'b11))))begin + if((((CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE) && 1'b1) && (! 1'b0)))begin + CsrPlugin_interrupt = 1'b1; + CsrPlugin_interruptCode = (4'b0111); + CsrPlugin_interruptTargetPrivilege = (2'b11); + end + if((((CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE) && 1'b1) && (! 1'b0)))begin + CsrPlugin_interrupt = 1'b1; + CsrPlugin_interruptCode = (4'b0011); + CsrPlugin_interruptTargetPrivilege = (2'b11); + end + if((((CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE) && 1'b1) && (! 1'b0)))begin + CsrPlugin_interrupt = 1'b1; + CsrPlugin_interruptCode = (4'b1011); + CsrPlugin_interruptTargetPrivilege = (2'b11); + end + end + if((! CsrPlugin_allowInterrupts))begin + CsrPlugin_interrupt = 1'b0; + end + end + + assign CsrPlugin_exception = (CsrPlugin_exceptionPortCtrl_exceptionValids_execute && CsrPlugin_allowException); + assign CsrPlugin_lastStageWasWfi = 1'b0; + always @ (*) begin + CsrPlugin_pipelineLiberator_done = ((! (execute_arbitration_isValid != (1'b0))) && IBusCachedPlugin_pcValids_1); + if((CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute != (1'b0)))begin + CsrPlugin_pipelineLiberator_done = 1'b0; + end + if(CsrPlugin_hadException)begin + CsrPlugin_pipelineLiberator_done = 1'b0; + end + end + + assign CsrPlugin_interruptJump = (CsrPlugin_interrupt && CsrPlugin_pipelineLiberator_done); + always @ (*) begin + CsrPlugin_targetPrivilege = CsrPlugin_interruptTargetPrivilege; + if(CsrPlugin_hadException)begin + CsrPlugin_targetPrivilege = CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; + end + end + + always @ (*) begin + CsrPlugin_trapCause = CsrPlugin_interruptCode; + if(CsrPlugin_hadException)begin + CsrPlugin_trapCause = CsrPlugin_exceptionPortCtrl_exceptionContext_code; + end + end + + always @ (*) begin + CsrPlugin_xtvec_mode = (2'bxx); + CsrPlugin_xtvec_base = (30'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx); + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_xtvec_mode = CsrPlugin_mtvec_mode; + CsrPlugin_xtvec_base = CsrPlugin_mtvec_base; + end + default : begin + end + endcase + end + + assign contextSwitching = CsrPlugin_jumpInterface_valid; + assign _zz_23_ = (! (((decode_INSTRUCTION[14 : 13] == (2'b01)) && (decode_INSTRUCTION[19 : 15] == (5'b00000))) || ((decode_INSTRUCTION[14 : 13] == (2'b11)) && (decode_INSTRUCTION[19 : 15] == (5'b00000))))); + assign _zz_22_ = (decode_INSTRUCTION[13 : 7] != (7'b0100000)); + assign execute_CsrPlugin_inWfi = 1'b0; + assign execute_CsrPlugin_blockedBySideEffects = 1'b0; + always @ (*) begin + execute_CsrPlugin_illegalAccess = 1'b1; + execute_CsrPlugin_readData = (32'b00000000000000000000000000000000); + case(execute_CsrPlugin_csrAddress) + 12'b101111000000 : begin + execute_CsrPlugin_illegalAccess = 1'b0; + execute_CsrPlugin_readData[31 : 0] = _zz_125_; + end + 12'b001100000000 : begin + execute_CsrPlugin_illegalAccess = 1'b0; + execute_CsrPlugin_readData[12 : 11] = CsrPlugin_mstatus_MPP; + execute_CsrPlugin_readData[7 : 7] = CsrPlugin_mstatus_MPIE; + execute_CsrPlugin_readData[3 : 3] = CsrPlugin_mstatus_MIE; + end + 12'b001101000001 : begin + execute_CsrPlugin_illegalAccess = 1'b0; + execute_CsrPlugin_readData[31 : 0] = CsrPlugin_mepc; + end + 12'b001100000101 : begin + if(execute_CSR_WRITE_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + 12'b001101000100 : begin + execute_CsrPlugin_illegalAccess = 1'b0; + execute_CsrPlugin_readData[11 : 11] = CsrPlugin_mip_MEIP; + execute_CsrPlugin_readData[7 : 7] = CsrPlugin_mip_MTIP; + execute_CsrPlugin_readData[3 : 3] = CsrPlugin_mip_MSIP; + end + 12'b001101000011 : begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + execute_CsrPlugin_readData[31 : 0] = CsrPlugin_mtval; + end + 12'b111111000000 : begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + execute_CsrPlugin_readData[31 : 0] = _zz_126_; + end + 12'b001101000000 : begin + execute_CsrPlugin_illegalAccess = 1'b0; + execute_CsrPlugin_readData[31 : 0] = CsrPlugin_mscratch; + end + 12'b001100000100 : begin + execute_CsrPlugin_illegalAccess = 1'b0; + execute_CsrPlugin_readData[11 : 11] = CsrPlugin_mie_MEIE; + execute_CsrPlugin_readData[7 : 7] = CsrPlugin_mie_MTIE; + execute_CsrPlugin_readData[3 : 3] = CsrPlugin_mie_MSIE; + end + 12'b001101000010 : begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + execute_CsrPlugin_readData[31 : 31] = CsrPlugin_mcause_interrupt; + execute_CsrPlugin_readData[3 : 0] = CsrPlugin_mcause_exceptionCode; + end + default : begin + end + endcase + if((CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]))begin + execute_CsrPlugin_illegalAccess = 1'b1; + end + if(((! execute_arbitration_isValid) || (! execute_IS_CSR)))begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + + always @ (*) begin + execute_CsrPlugin_illegalInstruction = 1'b0; + if((execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)))begin + if((CsrPlugin_privilege < execute_INSTRUCTION[29 : 28]))begin + execute_CsrPlugin_illegalInstruction = 1'b1; + end + end + end + + always @ (*) begin + CsrPlugin_selfException_valid = 1'b0; + CsrPlugin_selfException_payload_code = (4'bxxxx); + if((execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)))begin + CsrPlugin_selfException_valid = 1'b1; + case(CsrPlugin_privilege) + 2'b00 : begin + CsrPlugin_selfException_payload_code = (4'b1000); + end + default : begin + CsrPlugin_selfException_payload_code = (4'b1011); + end + endcase + end + if((execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_EBREAK)))begin + CsrPlugin_selfException_valid = 1'b1; + CsrPlugin_selfException_payload_code = (4'b0011); + end + end + + assign CsrPlugin_selfException_payload_badAddr = execute_INSTRUCTION; + assign execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); + assign execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); + assign execute_CsrPlugin_writeEnable = ((execute_CsrPlugin_writeInstruction && (! execute_CsrPlugin_blockedBySideEffects)) && (! execute_arbitration_isStuckByOthers)); + assign execute_CsrPlugin_readEnable = ((execute_CsrPlugin_readInstruction && (! execute_CsrPlugin_blockedBySideEffects)) && (! execute_arbitration_isStuckByOthers)); + assign execute_CsrPlugin_readToWriteData = execute_CsrPlugin_readData; + always @ (*) begin + case(_zz_164_) + 1'b0 : begin + execute_CsrPlugin_writeData = execute_SRC1; + end + default : begin + execute_CsrPlugin_writeData = (execute_INSTRUCTION[12] ? (execute_CsrPlugin_readToWriteData & (~ execute_SRC1)) : (execute_CsrPlugin_readToWriteData | execute_SRC1)); + end + endcase + end + + assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20]; + assign _zz_126_ = (_zz_125_ & externalInterruptArray_regNext); + assign externalInterrupt = (_zz_126_ != (32'b00000000000000000000000000000000)); + assign _zz_21_ = decode_ALU_BITWISE_CTRL; + assign _zz_19_ = _zz_45_; + assign _zz_39_ = decode_to_execute_ALU_BITWISE_CTRL; + assign _zz_18_ = decode_SHIFT_CTRL; + assign _zz_16_ = _zz_56_; + assign _zz_28_ = decode_to_execute_SHIFT_CTRL; + assign _zz_15_ = decode_BRANCH_CTRL; + assign _zz_13_ = _zz_51_; + assign _zz_26_ = decode_to_execute_BRANCH_CTRL; + assign _zz_12_ = decode_ALU_CTRL; + assign _zz_10_ = _zz_53_; + assign _zz_37_ = decode_to_execute_ALU_CTRL; + assign _zz_9_ = decode_SRC1_CTRL; + assign _zz_7_ = _zz_50_; + assign _zz_34_ = decode_to_execute_SRC1_CTRL; + assign _zz_6_ = decode_SRC2_CTRL; + assign _zz_4_ = _zz_55_; + assign _zz_32_ = decode_to_execute_SRC2_CTRL; + assign _zz_3_ = decode_ENV_CTRL; + assign _zz_1_ = _zz_52_; + assign _zz_24_ = decode_to_execute_ENV_CTRL; + assign decode_arbitration_isFlushed = ({execute_arbitration_flushAll,decode_arbitration_flushAll} != (2'b00)); + assign execute_arbitration_isFlushed = (execute_arbitration_flushAll != (1'b0)); + assign decode_arbitration_isStuckByOthers = (decode_arbitration_haltByOther || (1'b0 || execute_arbitration_isStuck)); + assign decode_arbitration_isStuck = (decode_arbitration_haltItself || decode_arbitration_isStuckByOthers); + assign decode_arbitration_isMoving = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)); + assign decode_arbitration_isFiring = ((decode_arbitration_isValid && (! decode_arbitration_isStuck)) && (! decode_arbitration_removeIt)); + assign execute_arbitration_isStuckByOthers = (execute_arbitration_haltByOther || 1'b0); + assign execute_arbitration_isStuck = (execute_arbitration_haltItself || execute_arbitration_isStuckByOthers); + assign execute_arbitration_isMoving = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)); + assign execute_arbitration_isFiring = ((execute_arbitration_isValid && (! execute_arbitration_isStuck)) && (! execute_arbitration_removeIt)); + assign iBusWishbone_ADR = {_zz_203_,_zz_127_}; + assign iBusWishbone_CTI = ((_zz_127_ == (3'b111)) ? (3'b111) : (3'b010)); + assign iBusWishbone_BTE = (2'b00); + assign iBusWishbone_SEL = (4'b1111); + assign iBusWishbone_WE = 1'b0; + assign iBusWishbone_DAT_MOSI = (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx); + always @ (*) begin + iBusWishbone_CYC = 1'b0; + iBusWishbone_STB = 1'b0; + if(_zz_161_)begin + iBusWishbone_CYC = 1'b1; + iBusWishbone_STB = 1'b1; + end + end + + assign iBus_cmd_ready = (iBus_cmd_valid && iBusWishbone_ACK); + assign iBus_rsp_valid = _zz_128_; + assign iBus_rsp_payload_data = iBusWishbone_DAT_MISO_regNext; + assign iBus_rsp_payload_error = 1'b0; + assign dBus_cmd_halfPipe_valid = dBus_cmd_halfPipe_regs_valid; + assign dBus_cmd_halfPipe_payload_wr = dBus_cmd_halfPipe_regs_payload_wr; + assign dBus_cmd_halfPipe_payload_address = dBus_cmd_halfPipe_regs_payload_address; + assign dBus_cmd_halfPipe_payload_data = dBus_cmd_halfPipe_regs_payload_data; + assign dBus_cmd_halfPipe_payload_size = dBus_cmd_halfPipe_regs_payload_size; + assign dBus_cmd_ready = dBus_cmd_halfPipe_regs_ready; + assign dBusWishbone_ADR = (dBus_cmd_halfPipe_payload_address >>> 2); + assign dBusWishbone_CTI = (3'b000); + assign dBusWishbone_BTE = (2'b00); + always @ (*) begin + case(dBus_cmd_halfPipe_payload_size) + 2'b00 : begin + _zz_129_ = (4'b0001); + end + 2'b01 : begin + _zz_129_ = (4'b0011); + end + default : begin + _zz_129_ = (4'b1111); + end + endcase + end + + always @ (*) begin + dBusWishbone_SEL = _zz_204_[3:0]; + if((! dBus_cmd_halfPipe_payload_wr))begin + dBusWishbone_SEL = (4'b1111); + end + end + + assign dBusWishbone_WE = dBus_cmd_halfPipe_payload_wr; + assign dBusWishbone_DAT_MOSI = dBus_cmd_halfPipe_payload_data; + assign dBus_cmd_halfPipe_ready = (dBus_cmd_halfPipe_valid && dBusWishbone_ACK); + assign dBusWishbone_CYC = dBus_cmd_halfPipe_valid; + assign dBusWishbone_STB = dBus_cmd_halfPipe_valid; + assign dBus_rsp_ready = ((dBus_cmd_halfPipe_valid && (! dBusWishbone_WE)) && dBusWishbone_ACK); + assign dBus_rsp_data = dBusWishbone_DAT_MISO; + assign dBus_rsp_error = 1'b0; + always @ (posedge clk) begin + if(reset) begin + IBusCachedPlugin_fetchPc_pcReg <= externalResetVector; + IBusCachedPlugin_fetchPc_inc <= 1'b0; + _zz_75_ <= 1'b0; + _zz_80_ <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; + IBusCachedPlugin_injector_decodeRemoved <= 1'b0; + execute_DBusSimplePlugin_cmdSent <= 1'b0; + execute_LightShifterPlugin_isActive <= 1'b0; + CsrPlugin_mstatus_MIE <= 1'b0; + CsrPlugin_mstatus_MPIE <= 1'b0; + CsrPlugin_mstatus_MPP <= (2'b11); + CsrPlugin_mie_MEIE <= 1'b0; + CsrPlugin_mie_MTIE <= 1'b0; + CsrPlugin_mie_MSIE <= 1'b0; + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= 1'b0; + CsrPlugin_hadException <= 1'b0; + _zz_125_ <= (32'b00000000000000000000000000000000); + execute_arbitration_isValid <= 1'b0; + _zz_127_ <= (3'b000); + _zz_128_ <= 1'b0; + dBus_cmd_halfPipe_regs_valid <= 1'b0; + dBus_cmd_halfPipe_regs_ready <= 1'b1; + end else begin + if(IBusCachedPlugin_fetchPc_propagatePc)begin + IBusCachedPlugin_fetchPc_inc <= 1'b0; + end + if(IBusCachedPlugin_jump_pcLoad_valid)begin + IBusCachedPlugin_fetchPc_inc <= 1'b0; + end + if(_zz_160_)begin + IBusCachedPlugin_fetchPc_inc <= 1'b1; + end + if(IBusCachedPlugin_fetchPc_samplePcNext)begin + IBusCachedPlugin_fetchPc_pcReg <= IBusCachedPlugin_fetchPc_pc; + end + _zz_75_ <= 1'b1; + if((IBusCachedPlugin_jump_pcLoad_valid || IBusCachedPlugin_fetcherflushIt))begin + _zz_80_ <= 1'b0; + end + if(_zz_78_)begin + _zz_80_ <= IBusCachedPlugin_iBusRsp_stages_0_output_valid; + end + if((IBusCachedPlugin_jump_pcLoad_valid || IBusCachedPlugin_fetcherflushIt))begin + IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; + end + if((! (! IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready)))begin + IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b1; + end + if((IBusCachedPlugin_jump_pcLoad_valid || IBusCachedPlugin_fetcherflushIt))begin + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; + end + if((! execute_arbitration_isStuck))begin + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= IBusCachedPlugin_injector_nextPcCalc_valids_0; + end + if((IBusCachedPlugin_jump_pcLoad_valid || IBusCachedPlugin_fetcherflushIt))begin + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; + end + if(decode_arbitration_removeIt)begin + IBusCachedPlugin_injector_decodeRemoved <= 1'b1; + end + if((IBusCachedPlugin_jump_pcLoad_valid || IBusCachedPlugin_fetcherflushIt))begin + IBusCachedPlugin_injector_decodeRemoved <= 1'b0; + end + if((dBus_cmd_valid && dBus_cmd_ready))begin + execute_DBusSimplePlugin_cmdSent <= 1'b1; + end + if((! execute_arbitration_isStuck))begin + execute_DBusSimplePlugin_cmdSent <= 1'b0; + end + if(_zz_153_)begin + if(_zz_154_)begin + execute_LightShifterPlugin_isActive <= 1'b1; + if(execute_LightShifterPlugin_done)begin + execute_LightShifterPlugin_isActive <= 1'b0; + end + end + end + if(execute_arbitration_removeIt)begin + execute_LightShifterPlugin_isActive <= 1'b0; + end + if((! decode_arbitration_isStuck))begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; + end else begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= CsrPlugin_exceptionPortCtrl_exceptionValids_decode; + end + if((! execute_arbitration_isStuck))begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= (CsrPlugin_exceptionPortCtrl_exceptionValids_decode && (! decode_arbitration_isStuck)); + end else begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= 1'b0; + end + CsrPlugin_hadException <= CsrPlugin_exception; + if(_zz_157_)begin + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_mstatus_MIE <= 1'b0; + CsrPlugin_mstatus_MPIE <= CsrPlugin_mstatus_MIE; + CsrPlugin_mstatus_MPP <= CsrPlugin_privilege; + end + default : begin + end + endcase + end + if(_zz_158_)begin + case(_zz_159_) + 2'b11 : begin + CsrPlugin_mstatus_MPP <= (2'b00); + CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE; + CsrPlugin_mstatus_MPIE <= 1'b1; + end + default : begin + end + endcase + end + if(((! execute_arbitration_isStuck) || execute_arbitration_removeIt))begin + execute_arbitration_isValid <= 1'b0; + end + if(((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)))begin + execute_arbitration_isValid <= decode_arbitration_isValid; + end + case(execute_CsrPlugin_csrAddress) + 12'b101111000000 : begin + if(execute_CsrPlugin_writeEnable)begin + _zz_125_ <= execute_CsrPlugin_writeData[31 : 0]; + end + end + 12'b001100000000 : begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11]; + CsrPlugin_mstatus_MPIE <= _zz_197_[0]; + CsrPlugin_mstatus_MIE <= _zz_198_[0]; + end + end + 12'b001101000001 : begin + end + 12'b001100000101 : begin + end + 12'b001101000100 : begin + end + 12'b001101000011 : begin + end + 12'b111111000000 : begin + end + 12'b001101000000 : begin + end + 12'b001100000100 : begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mie_MEIE <= _zz_200_[0]; + CsrPlugin_mie_MTIE <= _zz_201_[0]; + CsrPlugin_mie_MSIE <= _zz_202_[0]; + end + end + 12'b001101000010 : begin + end + default : begin + end + endcase + if(_zz_161_)begin + if(iBusWishbone_ACK)begin + _zz_127_ <= (_zz_127_ + (3'b001)); + end + end + _zz_128_ <= (iBusWishbone_CYC && iBusWishbone_ACK); + if(_zz_162_)begin + dBus_cmd_halfPipe_regs_valid <= dBus_cmd_valid; + dBus_cmd_halfPipe_regs_ready <= (! dBus_cmd_valid); + end else begin + dBus_cmd_halfPipe_regs_valid <= (! dBus_cmd_halfPipe_ready); + dBus_cmd_halfPipe_regs_ready <= dBus_cmd_halfPipe_ready; + end + end + end + + always @ (posedge clk) begin + if(IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready)begin + IBusCachedPlugin_s1_tightlyCoupledHit <= IBusCachedPlugin_s0_tightlyCoupledHit; + end + if((! execute_arbitration_isStuckByOthers))begin + execute_LightShifterPlugin_shiftReg <= _zz_59_; + end + if(_zz_153_)begin + if(_zz_154_)begin + execute_LightShifterPlugin_amplitudeReg <= (execute_LightShifterPlugin_amplitude - (5'b00001)); + end + end + CsrPlugin_mip_MEIP <= externalInterrupt; + CsrPlugin_mip_MTIP <= timerInterrupt; + CsrPlugin_mip_MSIP <= softwareInterrupt; + CsrPlugin_mcycle <= (CsrPlugin_mcycle + (64'b0000000000000000000000000000000000000000000000000000000000000001)); + if(execute_arbitration_isFiring)begin + CsrPlugin_minstret <= (CsrPlugin_minstret + (64'b0000000000000000000000000000000000000000000000000000000000000001)); + end + if(_zz_155_)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_119_ ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_119_ ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); + end + if(_zz_156_)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= _zz_151_; + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= _zz_152_; + end + if(_zz_157_)begin + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException); + CsrPlugin_mcause_exceptionCode <= CsrPlugin_trapCause; + CsrPlugin_mepc <= execute_PC; + if(CsrPlugin_hadException)begin + CsrPlugin_mtval <= CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; + end + end + default : begin + end + endcase + end + externalInterruptArray_regNext <= externalInterruptArray; + if((! execute_arbitration_isStuck))begin + decode_to_execute_ALU_BITWISE_CTRL <= _zz_20_; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SHIFT_CTRL <= _zz_17_; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_BRANCH_CTRL <= _zz_14_; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_MEMORY_STORE <= decode_MEMORY_STORE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC2_FORCE_ZERO <= decode_SRC2_FORCE_ZERO; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_ALU_CTRL <= _zz_11_; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC_USE_SUB_LESS <= decode_SRC_USE_SUB_LESS; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_CSR_READ_OPCODE <= decode_CSR_READ_OPCODE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC1_CTRL <= _zz_8_; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_MEMORY_ENABLE <= decode_MEMORY_ENABLE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_CSR <= decode_IS_CSR; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC2_CTRL <= _zz_5_; + end + if(((! execute_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_execute)))begin + decode_to_execute_PC <= decode_PC; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_INSTRUCTION <= decode_INSTRUCTION; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_FORMAL_PC_NEXT <= _zz_66_; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_ENV_CTRL <= _zz_2_; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_CSR_WRITE_OPCODE <= decode_CSR_WRITE_OPCODE; + end + case(execute_CsrPlugin_csrAddress) + 12'b101111000000 : begin + end + 12'b001100000000 : begin + end + 12'b001101000001 : begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mepc <= execute_CsrPlugin_writeData[31 : 0]; + end + end + 12'b001100000101 : begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mtvec_base <= execute_CsrPlugin_writeData[31 : 2]; + CsrPlugin_mtvec_mode <= execute_CsrPlugin_writeData[1 : 0]; + end + end + 12'b001101000100 : begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mip_MSIP <= _zz_199_[0]; + end + end + 12'b001101000011 : begin + end + 12'b111111000000 : begin + end + 12'b001101000000 : begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mscratch <= execute_CsrPlugin_writeData[31 : 0]; + end + end + 12'b001100000100 : begin + end + 12'b001101000010 : begin + end + default : begin + end + endcase + iBusWishbone_DAT_MISO_regNext <= iBusWishbone_DAT_MISO; + if(_zz_162_)begin + dBus_cmd_halfPipe_regs_payload_wr <= dBus_cmd_payload_wr; + dBus_cmd_halfPipe_regs_payload_address <= dBus_cmd_payload_address; + dBus_cmd_halfPipe_regs_payload_data <= dBus_cmd_payload_data; + dBus_cmd_halfPipe_regs_payload_size <= dBus_cmd_payload_size; + end + end + +endmodule + diff --git a/hw/rtl/2-stage-2048-cache.v_toplevel_RegFilePlugin_regFile.bin b/hw/rtl/2-stage-2048-cache.v_toplevel_RegFilePlugin_regFile.bin new file mode 100644 index 0000000000000000000000000000000000000000..4c177b2156e519e76ef33fcac7621445a9beb984 GIT binary patch literal 1056 fcmXpozz?|aOB)!BDu9I0XgG|919Dy&Cg}kHTp__h literal 0 HcmV?d00001 diff --git a/hw/rtl/2-stage-2048-cache.yaml b/hw/rtl/2-stage-2048-cache.yaml new file mode 100644 index 0000000..b55f8e5 --- /dev/null +++ b/hw/rtl/2-stage-2048-cache.yaml @@ -0,0 +1,4 @@ +iBus: !!vexriscv.BusReport + flushInstructions: [4111, 19, 19, 19] + info: !!vexriscv.CacheReport {bytePerLine: 32, size: 2048} + kind: cached diff --git a/hw/2-stage-1024-cache-debug.v b/hw/rtl/2-stage-512-cache-debug.v similarity index 99% rename from hw/2-stage-1024-cache-debug.v rename to hw/rtl/2-stage-512-cache-debug.v index bb89379..2576298 100644 --- a/hw/2-stage-1024-cache-debug.v +++ b/hw/rtl/2-stage-512-cache-debug.v @@ -1,5 +1,5 @@ // Generator : SpinalHDL v1.3.2 git head : 41815ceafff4e72c2e3a3e1ff7e9ada5202a0d26 -// Date : 26/03/2019, 08:02:43 +// Date : 11/04/2019, 06:14:01 // Component : VexRiscv @@ -92,19 +92,19 @@ module InstructionCache ( input io_mem_rsp_payload_error, input clk, input reset); - reg [23:0] _zz_12_; + reg [24:0] _zz_12_; reg [31:0] _zz_13_; wire _zz_14_; wire [0:0] _zz_15_; wire [0:0] _zz_16_; - wire [23:0] _zz_17_; + wire [24:0] _zz_17_; reg _zz_1_; reg _zz_2_; reg lineLoader_fire; reg lineLoader_valid; reg [31:0] lineLoader_address; reg lineLoader_hadError; - reg [5:0] lineLoader_flushCounter; + reg [4:0] lineLoader_flushCounter; reg _zz_3_; reg lineLoader_flushFromInterface; wire _zz_4_; @@ -116,21 +116,21 @@ module InstructionCache ( wire lineLoader_wayToAllocate_willOverflow; reg [2:0] lineLoader_wordIndex; wire lineLoader_write_tag_0_valid; - wire [4:0] lineLoader_write_tag_0_payload_address; + wire [3:0] lineLoader_write_tag_0_payload_address; wire lineLoader_write_tag_0_payload_data_valid; wire lineLoader_write_tag_0_payload_data_error; - wire [21:0] lineLoader_write_tag_0_payload_data_address; + wire [22:0] lineLoader_write_tag_0_payload_data_address; wire lineLoader_write_data_0_valid; - wire [7:0] lineLoader_write_data_0_payload_address; + wire [6:0] lineLoader_write_data_0_payload_address; wire [31:0] lineLoader_write_data_0_payload_data; wire _zz_5_; - wire [4:0] _zz_6_; + wire [3:0] _zz_6_; wire _zz_7_; wire fetchStage_read_waysValues_0_tag_valid; wire fetchStage_read_waysValues_0_tag_error; - wire [21:0] fetchStage_read_waysValues_0_tag_address; - wire [23:0] _zz_8_; - wire [7:0] _zz_9_; + wire [22:0] fetchStage_read_waysValues_0_tag_address; + wire [24:0] _zz_8_; + wire [6:0] _zz_9_; wire _zz_10_; wire [31:0] fetchStage_read_waysValues_0_data; reg [31:0] decodeStage_mmuRsp_physicalAddress; @@ -143,7 +143,7 @@ module InstructionCache ( reg decodeStage_mmuRsp_hit; reg decodeStage_hit_tags_0_valid; reg decodeStage_hit_tags_0_error; - reg [21:0] decodeStage_hit_tags_0_address; + reg [22:0] decodeStage_hit_tags_0_address; wire decodeStage_hit_hits_0; wire decodeStage_hit_valid; wire decodeStage_hit_error; @@ -152,9 +152,9 @@ module InstructionCache ( reg [31:0] decodeStage_hit_word; reg io_cpu_fetch_dataBypassValid_regNextWhen; reg [31:0] io_cpu_fetch_dataBypass_regNextWhen; - reg [23:0] ways_0_tags [0:31]; - reg [31:0] ways_0_datas [0:255]; - assign _zz_14_ = (! lineLoader_flushCounter[5]); + reg [24:0] ways_0_tags [0:15]; + reg [31:0] ways_0_datas [0:127]; + assign _zz_14_ = (! lineLoader_flushCounter[4]); assign _zz_15_ = _zz_8_[0 : 0]; assign _zz_16_ = _zz_8_[1 : 1]; assign _zz_17_ = {lineLoader_write_tag_0_payload_data_address,{lineLoader_write_tag_0_payload_data_error,lineLoader_write_tag_0_payload_data_valid}}; @@ -222,7 +222,7 @@ module InstructionCache ( end assign io_flush_cmd_ready = (! (lineLoader_valid || io_cpu_fetch_isValid)); - assign _zz_4_ = lineLoader_flushCounter[5]; + assign _zz_4_ = lineLoader_flushCounter[4]; assign io_flush_rsp = ((_zz_4_ && (! _zz_4__regNext)) && lineLoader_flushFromInterface); assign io_mem_cmd_valid = (lineLoader_valid && (! lineLoader_cmdSent)); assign io_mem_cmd_payload_address = {lineLoader_address[31 : 5],(5'b00000)}; @@ -238,21 +238,21 @@ module InstructionCache ( assign lineLoader_wayToAllocate_willOverflowIfInc = 1'b1; assign lineLoader_wayToAllocate_willOverflow = (lineLoader_wayToAllocate_willOverflowIfInc && lineLoader_wayToAllocate_willIncrement); assign _zz_5_ = 1'b1; - assign lineLoader_write_tag_0_valid = ((_zz_5_ && lineLoader_fire) || (! lineLoader_flushCounter[5])); - assign lineLoader_write_tag_0_payload_address = (lineLoader_flushCounter[5] ? lineLoader_address[9 : 5] : lineLoader_flushCounter[4 : 0]); - assign lineLoader_write_tag_0_payload_data_valid = lineLoader_flushCounter[5]; + assign lineLoader_write_tag_0_valid = ((_zz_5_ && lineLoader_fire) || (! lineLoader_flushCounter[4])); + assign lineLoader_write_tag_0_payload_address = (lineLoader_flushCounter[4] ? lineLoader_address[8 : 5] : lineLoader_flushCounter[3 : 0]); + assign lineLoader_write_tag_0_payload_data_valid = lineLoader_flushCounter[4]; assign lineLoader_write_tag_0_payload_data_error = (lineLoader_hadError || io_mem_rsp_payload_error); - assign lineLoader_write_tag_0_payload_data_address = lineLoader_address[31 : 10]; + assign lineLoader_write_tag_0_payload_data_address = lineLoader_address[31 : 9]; assign lineLoader_write_data_0_valid = (io_mem_rsp_valid && _zz_5_); - assign lineLoader_write_data_0_payload_address = {lineLoader_address[9 : 5],lineLoader_wordIndex}; + assign lineLoader_write_data_0_payload_address = {lineLoader_address[8 : 5],lineLoader_wordIndex}; assign lineLoader_write_data_0_payload_data = io_mem_rsp_payload_data; - assign _zz_6_ = io_cpu_prefetch_pc[9 : 5]; + assign _zz_6_ = io_cpu_prefetch_pc[8 : 5]; assign _zz_7_ = (! io_cpu_fetch_isStuck); assign _zz_8_ = _zz_12_; assign fetchStage_read_waysValues_0_tag_valid = _zz_15_[0]; assign fetchStage_read_waysValues_0_tag_error = _zz_16_[0]; - assign fetchStage_read_waysValues_0_tag_address = _zz_8_[23 : 2]; - assign _zz_9_ = io_cpu_prefetch_pc[9 : 2]; + assign fetchStage_read_waysValues_0_tag_address = _zz_8_[24 : 2]; + assign _zz_9_ = io_cpu_prefetch_pc[8 : 2]; assign _zz_10_ = (! io_cpu_fetch_isStuck); assign fetchStage_read_waysValues_0_data = _zz_13_; assign io_cpu_fetch_data = (io_cpu_fetch_dataBypassValid ? io_cpu_fetch_dataBypass : fetchStage_read_waysValues_0_data[31 : 0]); @@ -261,7 +261,7 @@ module InstructionCache ( assign io_cpu_fetch_mmuBus_cmd_bypassTranslation = 1'b0; assign io_cpu_fetch_mmuBus_end = ((! io_cpu_fetch_isStuck) || io_cpu_fetch_isRemoved); assign io_cpu_fetch_physicalAddress = io_cpu_fetch_mmuBus_rsp_physicalAddress; - assign decodeStage_hit_hits_0 = (decodeStage_hit_tags_0_valid && (decodeStage_hit_tags_0_address == decodeStage_mmuRsp_physicalAddress[31 : 10])); + assign decodeStage_hit_hits_0 = (decodeStage_hit_tags_0_valid && (decodeStage_hit_tags_0_address == decodeStage_mmuRsp_physicalAddress[31 : 9])); assign decodeStage_hit_valid = (decodeStage_hit_hits_0 != (1'b0)); assign decodeStage_hit_error = decodeStage_hit_tags_0_error; assign decodeStage_hit_data = _zz_11_; @@ -282,7 +282,7 @@ module InstructionCache ( if(reset) begin lineLoader_valid <= 1'b0; lineLoader_hadError <= 1'b0; - lineLoader_flushCounter <= (6'b000000); + lineLoader_flushCounter <= (5'b00000); lineLoader_flushFromInterface <= 1'b0; lineLoader_cmdSent <= 1'b0; lineLoader_wordIndex <= (3'b000); @@ -297,11 +297,11 @@ module InstructionCache ( lineLoader_valid <= 1'b1; end if(_zz_14_)begin - lineLoader_flushCounter <= (lineLoader_flushCounter + (6'b000001)); + lineLoader_flushCounter <= (lineLoader_flushCounter + (5'b00001)); end if(io_flush_cmd_valid)begin if(io_flush_cmd_ready)begin - lineLoader_flushCounter <= (6'b000000); + lineLoader_flushCounter <= (5'b00000); lineLoader_flushFromInterface <= 1'b1; end end @@ -324,7 +324,7 @@ module InstructionCache ( if(io_cpu_fill_valid)begin lineLoader_address <= io_cpu_fill_payload; end - _zz_3_ <= lineLoader_flushCounter[5]; + _zz_3_ <= lineLoader_flushCounter[4]; _zz_4__regNext <= _zz_4_; if((! io_cpu_decode_isStuck))begin decodeStage_mmuRsp_physicalAddress <= io_cpu_fetch_mmuBus_rsp_physicalAddress; diff --git a/hw/rtl/2-stage-512-cache-debug.yaml b/hw/rtl/2-stage-512-cache-debug.yaml new file mode 100644 index 0000000..d2c99a3 --- /dev/null +++ b/hw/rtl/2-stage-512-cache-debug.yaml @@ -0,0 +1,5 @@ +debug: !!vexriscv.DebugReport {hardwareBreakpointCount: 4} +iBus: !!vexriscv.BusReport + flushInstructions: [16399, 19, 19, 19] + info: !!vexriscv.CacheReport {bytePerLine: 32, size: 512} + kind: cached diff --git a/hw/2-stage-no-cache-debug.v b/hw/rtl/2-stage-no-cache-debug.v similarity index 100% rename from hw/2-stage-no-cache-debug.v rename to hw/rtl/2-stage-no-cache-debug.v diff --git a/hw/rtl/2-stage-no-cache-debug.v_toplevel_RegFilePlugin_regFile.bin b/hw/rtl/2-stage-no-cache-debug.v_toplevel_RegFilePlugin_regFile.bin new file mode 100644 index 0000000000000000000000000000000000000000..4c177b2156e519e76ef33fcac7621445a9beb984 GIT binary patch literal 1056 fcmXpozz?|aOB)!BDu9I0XgG|919Dy&Cg}kHTp__h literal 0 HcmV?d00001 diff --git a/hw/2-stage-no-cache-debug.yaml b/hw/rtl/2-stage-no-cache-debug.yaml similarity index 100% rename from hw/2-stage-no-cache-debug.yaml rename to hw/rtl/2-stage-no-cache-debug.yaml diff --git a/hw/4-stage-1024-cache-debug.v b/hw/rtl/4-stage-1024-cache-debug.v similarity index 100% rename from hw/4-stage-1024-cache-debug.v rename to hw/rtl/4-stage-1024-cache-debug.v diff --git a/hw/rtl/4-stage-1024-cache-debug.v_toplevel_RegFilePlugin_regFile.bin b/hw/rtl/4-stage-1024-cache-debug.v_toplevel_RegFilePlugin_regFile.bin new file mode 100644 index 0000000000000000000000000000000000000000..4c177b2156e519e76ef33fcac7621445a9beb984 GIT binary patch literal 1056 fcmXpozz?|aOB)!BDu9I0XgG|919Dy&Cg}kHTp__h literal 0 HcmV?d00001 diff --git a/hw/4-stage-1024-cache-debug.yaml b/hw/rtl/4-stage-1024-cache-debug.yaml similarity index 100% rename from hw/4-stage-1024-cache-debug.yaml rename to hw/rtl/4-stage-1024-cache-debug.yaml diff --git a/hw/4-stage-no-cache-debug.v b/hw/rtl/4-stage-no-cache-debug.v similarity index 100% rename from hw/4-stage-no-cache-debug.v rename to hw/rtl/4-stage-no-cache-debug.v diff --git a/hw/rtl/4-stage-no-cache-debug.v_toplevel_RegFilePlugin_regFile.bin b/hw/rtl/4-stage-no-cache-debug.v_toplevel_RegFilePlugin_regFile.bin new file mode 100644 index 0000000000000000000000000000000000000000..4c177b2156e519e76ef33fcac7621445a9beb984 GIT binary patch literal 1056 fcmXpozz?|aOB)!BDu9I0XgG|919Dy&Cg}kHTp__h literal 0 HcmV?d00001 diff --git a/hw/4-stage-no-cache-debug.yaml b/hw/rtl/4-stage-no-cache-debug.yaml similarity index 100% rename from hw/4-stage-no-cache-debug.yaml rename to hw/rtl/4-stage-no-cache-debug.yaml diff --git a/hw/5-stage-pipelined-no-cache-debug.v b/hw/rtl/5-stage-pipelined-no-cache-debug.v similarity index 100% rename from hw/5-stage-pipelined-no-cache-debug.v rename to hw/rtl/5-stage-pipelined-no-cache-debug.v diff --git a/hw/5-stage-pipelined-no-cache-debug.yaml b/hw/rtl/5-stage-pipelined-no-cache-debug.yaml similarity index 100% rename from hw/5-stage-pipelined-no-cache-debug.yaml rename to hw/rtl/5-stage-pipelined-no-cache-debug.yaml diff --git a/hw/spimemio.v b/hw/rtl/spimemio.v similarity index 100% rename from hw/spimemio.v rename to hw/rtl/spimemio.v