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hw: set debug bridge memory size to 0x100
Hardware breakpoints live at offset 0x40 from the start of this region, so increase the size from 0x10 to 0x100. Signed-off-by: Sean Cross <sean@xobs.io>
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@ -711,7 +711,7 @@ class BaseSoC(SoCCore):
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self.cpu.use_external_variant("rtl/2-stage-1024-cache-debug.v")
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self.copy_memory_file("2-stage-1024-cache-debug.v_toplevel_RegFilePlugin_regFile.bin")
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os.path.join(output_dir, "gateware")
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self.register_mem("vexriscv_debug", 0xf00f0000, self.cpu.debug_bus, 0x10)
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self.register_mem("vexriscv_debug", 0xf00f0000, self.cpu.debug_bus, 0x100)
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else:
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if hasattr(self, "cpu"):
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self.cpu.use_external_variant("rtl/2-stage-1024-cache.v")
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