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hw: set debug bridge memory size to 0x100

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Hardware breakpoints live at offset 0x40 from the start of this region,
so increase the size from 0x10 to 0x100.

Signed-off-by: Sean Cross <sean@xobs.io>
This commit is contained in:
Sean Cross 2019-07-04 16:39:28 +08:00
parent c5b45a4314
commit d1cd68c232
1 changed files with 1 additions and 1 deletions
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2
hw/foboot-bitstream.py
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@ -711,7 +711,7 @@ class BaseSoC(SoCCore):
self.cpu.use_external_variant("rtl/2-stage-1024-cache-debug.v")
self.copy_memory_file("2-stage-1024-cache-debug.v_toplevel_RegFilePlugin_regFile.bin")
os.path.join(output_dir, "gateware")
self.register_mem("vexriscv_debug", 0xf00f0000, self.cpu.debug_bus, 0x10)
self.register_mem("vexriscv_debug", 0xf00f0000, self.cpu.debug_bus, 0x100)
else:
if hasattr(self, "cpu"):
self.cpu.use_external_variant("rtl/2-stage-1024-cache.v")