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sw: fix line endings

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Signed-off-by: Sean Cross <sean@xobs.io>
This commit is contained in:
Sean Cross 2019-04-11 15:53:08 +08:00
parent f30fbce79f
commit e5a2b29456
11 changed files with 1139 additions and 1318 deletions
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198
sw/include/generated/csr.h
View File

@ -398,204 +398,6 @@ static inline unsigned char usb_ep_0_in_ibuf_empty_read(void) {
unsigned char r = csr_readl(0xe0004840); unsigned char r = csr_readl(0xe0004840);
return r; return r;
} }
#define CSR_USB_EP_1_IN_EV_STATUS_ADDR 0xe0004844
#define CSR_USB_EP_1_IN_EV_STATUS_SIZE 1
static inline unsigned char usb_ep_1_in_ev_status_read(void) {
unsigned char r = csr_readl(0xe0004844);
return r;
}
static inline void usb_ep_1_in_ev_status_write(unsigned char value) {
csr_writel(value, 0xe0004844);
}
#define CSR_USB_EP_1_IN_EV_PENDING_ADDR 0xe0004848
#define CSR_USB_EP_1_IN_EV_PENDING_SIZE 1
static inline unsigned char usb_ep_1_in_ev_pending_read(void) {
unsigned char r = csr_readl(0xe0004848);
return r;
}
static inline void usb_ep_1_in_ev_pending_write(unsigned char value) {
csr_writel(value, 0xe0004848);
}
#define CSR_USB_EP_1_IN_EV_ENABLE_ADDR 0xe000484c
#define CSR_USB_EP_1_IN_EV_ENABLE_SIZE 1
static inline unsigned char usb_ep_1_in_ev_enable_read(void) {
unsigned char r = csr_readl(0xe000484c);
return r;
}
static inline void usb_ep_1_in_ev_enable_write(unsigned char value) {
csr_writel(value, 0xe000484c);
}
#define CSR_USB_EP_1_IN_LAST_TOK_ADDR 0xe0004850
#define CSR_USB_EP_1_IN_LAST_TOK_SIZE 1
static inline unsigned char usb_ep_1_in_last_tok_read(void) {
unsigned char r = csr_readl(0xe0004850);
return r;
}
#define CSR_USB_EP_1_IN_RESPOND_ADDR 0xe0004854
#define CSR_USB_EP_1_IN_RESPOND_SIZE 1
static inline unsigned char usb_ep_1_in_respond_read(void) {
unsigned char r = csr_readl(0xe0004854);
return r;
}
static inline void usb_ep_1_in_respond_write(unsigned char value) {
csr_writel(value, 0xe0004854);
}
#define CSR_USB_EP_1_IN_DTB_ADDR 0xe0004858
#define CSR_USB_EP_1_IN_DTB_SIZE 1
static inline unsigned char usb_ep_1_in_dtb_read(void) {
unsigned char r = csr_readl(0xe0004858);
return r;
}
static inline void usb_ep_1_in_dtb_write(unsigned char value) {
csr_writel(value, 0xe0004858);
}
#define CSR_USB_EP_1_IN_IBUF_HEAD_ADDR 0xe000485c
#define CSR_USB_EP_1_IN_IBUF_HEAD_SIZE 1
static inline unsigned char usb_ep_1_in_ibuf_head_read(void) {
unsigned char r = csr_readl(0xe000485c);
return r;
}
static inline void usb_ep_1_in_ibuf_head_write(unsigned char value) {
csr_writel(value, 0xe000485c);
}
#define CSR_USB_EP_1_IN_IBUF_EMPTY_ADDR 0xe0004860
#define CSR_USB_EP_1_IN_IBUF_EMPTY_SIZE 1
static inline unsigned char usb_ep_1_in_ibuf_empty_read(void) {
unsigned char r = csr_readl(0xe0004860);
return r;
}
#define CSR_USB_EP_2_OUT_EV_STATUS_ADDR 0xe0004864
#define CSR_USB_EP_2_OUT_EV_STATUS_SIZE 1
static inline unsigned char usb_ep_2_out_ev_status_read(void) {
unsigned char r = csr_readl(0xe0004864);
return r;
}
static inline void usb_ep_2_out_ev_status_write(unsigned char value) {
csr_writel(value, 0xe0004864);
}
#define CSR_USB_EP_2_OUT_EV_PENDING_ADDR 0xe0004868
#define CSR_USB_EP_2_OUT_EV_PENDING_SIZE 1
static inline unsigned char usb_ep_2_out_ev_pending_read(void) {
unsigned char r = csr_readl(0xe0004868);
return r;
}
static inline void usb_ep_2_out_ev_pending_write(unsigned char value) {
csr_writel(value, 0xe0004868);
}
#define CSR_USB_EP_2_OUT_EV_ENABLE_ADDR 0xe000486c
#define CSR_USB_EP_2_OUT_EV_ENABLE_SIZE 1
static inline unsigned char usb_ep_2_out_ev_enable_read(void) {
unsigned char r = csr_readl(0xe000486c);
return r;
}
static inline void usb_ep_2_out_ev_enable_write(unsigned char value) {
csr_writel(value, 0xe000486c);
}
#define CSR_USB_EP_2_OUT_LAST_TOK_ADDR 0xe0004870
#define CSR_USB_EP_2_OUT_LAST_TOK_SIZE 1
static inline unsigned char usb_ep_2_out_last_tok_read(void) {
unsigned char r = csr_readl(0xe0004870);
return r;
}
#define CSR_USB_EP_2_OUT_RESPOND_ADDR 0xe0004874
#define CSR_USB_EP_2_OUT_RESPOND_SIZE 1
static inline unsigned char usb_ep_2_out_respond_read(void) {
unsigned char r = csr_readl(0xe0004874);
return r;
}
static inline void usb_ep_2_out_respond_write(unsigned char value) {
csr_writel(value, 0xe0004874);
}
#define CSR_USB_EP_2_OUT_DTB_ADDR 0xe0004878
#define CSR_USB_EP_2_OUT_DTB_SIZE 1
static inline unsigned char usb_ep_2_out_dtb_read(void) {
unsigned char r = csr_readl(0xe0004878);
return r;
}
static inline void usb_ep_2_out_dtb_write(unsigned char value) {
csr_writel(value, 0xe0004878);
}
#define CSR_USB_EP_2_OUT_OBUF_HEAD_ADDR 0xe000487c
#define CSR_USB_EP_2_OUT_OBUF_HEAD_SIZE 1
static inline unsigned char usb_ep_2_out_obuf_head_read(void) {
unsigned char r = csr_readl(0xe000487c);
return r;
}
static inline void usb_ep_2_out_obuf_head_write(unsigned char value) {
csr_writel(value, 0xe000487c);
}
#define CSR_USB_EP_2_OUT_OBUF_EMPTY_ADDR 0xe0004880
#define CSR_USB_EP_2_OUT_OBUF_EMPTY_SIZE 1
static inline unsigned char usb_ep_2_out_obuf_empty_read(void) {
unsigned char r = csr_readl(0xe0004880);
return r;
}
#define CSR_USB_EP_2_IN_EV_STATUS_ADDR 0xe0004884
#define CSR_USB_EP_2_IN_EV_STATUS_SIZE 1
static inline unsigned char usb_ep_2_in_ev_status_read(void) {
unsigned char r = csr_readl(0xe0004884);
return r;
}
static inline void usb_ep_2_in_ev_status_write(unsigned char value) {
csr_writel(value, 0xe0004884);
}
#define CSR_USB_EP_2_IN_EV_PENDING_ADDR 0xe0004888
#define CSR_USB_EP_2_IN_EV_PENDING_SIZE 1
static inline unsigned char usb_ep_2_in_ev_pending_read(void) {
unsigned char r = csr_readl(0xe0004888);
return r;
}
static inline void usb_ep_2_in_ev_pending_write(unsigned char value) {
csr_writel(value, 0xe0004888);
}
#define CSR_USB_EP_2_IN_EV_ENABLE_ADDR 0xe000488c
#define CSR_USB_EP_2_IN_EV_ENABLE_SIZE 1
static inline unsigned char usb_ep_2_in_ev_enable_read(void) {
unsigned char r = csr_readl(0xe000488c);
return r;
}
static inline void usb_ep_2_in_ev_enable_write(unsigned char value) {
csr_writel(value, 0xe000488c);
}
#define CSR_USB_EP_2_IN_LAST_TOK_ADDR 0xe0004890
#define CSR_USB_EP_2_IN_LAST_TOK_SIZE 1
static inline unsigned char usb_ep_2_in_last_tok_read(void) {
unsigned char r = csr_readl(0xe0004890);
return r;
}
#define CSR_USB_EP_2_IN_RESPOND_ADDR 0xe0004894
#define CSR_USB_EP_2_IN_RESPOND_SIZE 1
static inline unsigned char usb_ep_2_in_respond_read(void) {
unsigned char r = csr_readl(0xe0004894);
return r;
}
static inline void usb_ep_2_in_respond_write(unsigned char value) {
csr_writel(value, 0xe0004894);
}
#define CSR_USB_EP_2_IN_DTB_ADDR 0xe0004898
#define CSR_USB_EP_2_IN_DTB_SIZE 1
static inline unsigned char usb_ep_2_in_dtb_read(void) {
unsigned char r = csr_readl(0xe0004898);
return r;
}
static inline void usb_ep_2_in_dtb_write(unsigned char value) {
csr_writel(value, 0xe0004898);
}
#define CSR_USB_EP_2_IN_IBUF_HEAD_ADDR 0xe000489c
#define CSR_USB_EP_2_IN_IBUF_HEAD_SIZE 1
static inline unsigned char usb_ep_2_in_ibuf_head_read(void) {
unsigned char r = csr_readl(0xe000489c);
return r;
}
static inline void usb_ep_2_in_ibuf_head_write(unsigned char value) {
csr_writel(value, 0xe000489c);
}
#define CSR_USB_EP_2_IN_IBUF_EMPTY_ADDR 0xe00048a0
#define CSR_USB_EP_2_IN_IBUF_EMPTY_SIZE 1
static inline unsigned char usb_ep_2_in_ibuf_empty_read(void) {
unsigned char r = csr_readl(0xe00048a0);
return r;
}
/* constants */ /* constants */
#define NMI_INTERRUPT 0 #define NMI_INTERRUPT 0

3
sw/include/generated/mem.h
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@ -1,6 +1,9 @@
#ifndef __GENERATED_MEM_H #ifndef __GENERATED_MEM_H
#define __GENERATED_MEM_H #define __GENERATED_MEM_H
#define VEXRISCV_DEBUG_BASE 0xf00f0000
#define VEXRISCV_DEBUG_SIZE 0x00000010
#define SRAM_BASE 0x10000000 #define SRAM_BASE 0x10000000
#define SRAM_SIZE 0x00020000 #define SRAM_SIZE 0x00020000

7
sw/include/system.h
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@ -58,12 +58,9 @@ static inline void mtspr(unsigned long add, unsigned long val)
#include <generated/csr.h> #include <generated/csr.h>
__attribute__((noreturn)) static inline void reboot(void) { __attribute__((noreturn)) void reboot(void);
reboot_ctrl_write(0xac);
while (1);
}
__attribute__((noreturn)) static inline void reboot_to_image(uint8_t image_index) { __attribute__((noreturn)) static inline void warmboot_to_image(uint8_t image_index) {
reboot_ctrl_write(0xac | (image_index & 3) << 0); reboot_ctrl_write(0xac | (image_index & 3) << 0);
while (1); while (1);
} }

66
sw/src/main.c
View File

@ -38,34 +38,56 @@ static void rv_putchar(void *ignored, char c)
} }
#endif #endif
void reboot_to(uint32_t addr) { #define REBOOT_ADDR 0x20040000
void reboot(void) {
irq_setie(0); irq_setie(0);
irq_setmask(0);
usb_disconnect(); usb_disconnect();
spiFree(); spiFree();
rgb_mode_error(); rgb_mode_error();
/*
* Set the return address register to the base of the DDR memory at 0x80000000. // Check the first few words for the sync pulse;
* The reset handler of the application loaded to DDR memory by the bootloader int i;
* is expected to be at that location. int riscv_boot = 1;
*/ uint32_t *destination_array = (uint32_t *)REBOOT_ADDR;
void (*fnc)(void) = (void *)addr; for (i = 0; i < 16; i++) {
fnc(); if (destination_array[i] == 0x7e99aa7e) {
__builtin_unreachable(); riscv_boot = 0;
asm volatile("mv ra,%0\n\t" break;
}
}
if (riscv_boot) {
// Reset the Return Address, zero out some registers, and return.
asm volatile(
"mv ra,%0\n\t" /* x1 */
"mv sp,zero\n\t" /* x2 */
"mv gp,zero\n\t" /* x3 */
"mv tp,zero\n\t" /* x4 */
"mv t0,zero\n\t" /* x5 */
"mv t1,zero\n\t" /* x6 */
"mv t2,zero\n\t" /* x7 */
"mv x8,zero\n\t" /* x8 */
"mv s1,zero\n\t" /* x9 */
"mv a0,zero\n\t" /* x10 */
"mv a1,zero\n\t" /* x11 */
// /* Flush the caches */
// ".word 0x400f\n\t"
// "nop\n\t"
// "nop\n\t"
// "nop\n\t"
"ret\n\t"
: :
: "r"(addr) : "r"(REBOOT_ADDR)
); );
}
/* else {
* Flush the cache. // Issue a reboot
*/ warmboot_to_image(2);
// asm volatile ("fence.i"); }
/*
* We need to explicitly execute a return intruction in case the compiler had
* done some return addres register manipulation in this function's veneer.
*/
asm volatile("ret");
__builtin_unreachable(); __builtin_unreachable();
} }

5
sw/src/usb-dev.c
View File

@ -192,10 +192,7 @@ void usb_setup(const struct usb_setup_request *setup)
// to be received. // to be received.
usb_ack_in(); usb_ack_in();
usb_wait_for_send_done(); usb_wait_for_send_done();
reboot_to(0x20040000); reboot();
// Issue a reboot
reboot_to_image(0);
while (1) while (1)
; ;
return; return;