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hw: bitstream: move memory range for litex compatability

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The latest version of litex requires that we move this memory range up
by 0x80000000 to build.

Signed-off-by: Sean Cross <sean@xobs.io>
This commit is contained in:
Sean Cross 2019-11-25 12:53:54 +08:00
parent aa00485f43
commit f36a52453e
1 changed files with 2 additions and 2 deletions
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4
hw/foboot-bitstream.py
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@ -19,7 +19,7 @@ from migen.fhdl.decorators import ClockDomainsRenamer
from litex.build.lattice.platform import LatticePlatform
from litex.build.generic_platform import Pins, Subsignal
from litex.soc.integration.doc import AutoDoc, ModuleDoc
from litex.soc.integration import SoCCore
from litex.soc.integration.soc_core import SoCCore
from litex.soc.integration.builder import Builder
from litex.soc.interconnect import wishbone
@ -112,7 +112,7 @@ class BaseSoC(SoCCore, AutoDoc):
"sram": 0x10000000, # (default shadow @0xa0000000)
"spiflash": 0x20000000, # (default shadow @0xa0000000)
"main_ram": 0x40000000, # (default shadow @0xc0000000)
"csr": 0x60000000, # (default shadow @0xe0000000)
"csr": 0xe0000000, # (default shadow @0xe0000000)
}
interrupt_map = {