mirror of
https://github.com/im-tomu/foboot.git
synced 2024-09-20 02:40:09 +00:00
58f99aebf2
This commit includes the spibone support we're using to debug eptri. Signed-off-by: Sean Cross <sean@xobs.io>
4534 lines
186 KiB
Verilog
4534 lines
186 KiB
Verilog
// Generator : SpinalHDL v1.3.6 git head : 9bf01e7f360e003fac1dd5ca8b8f4bffec0e52b8
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// Date : 29/10/2019, 08:59:50
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// Component : VexRiscv
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`define EnvCtrlEnum_defaultEncoding_type [1:0]
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`define EnvCtrlEnum_defaultEncoding_NONE 2'b00
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`define EnvCtrlEnum_defaultEncoding_XRET 2'b01
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`define EnvCtrlEnum_defaultEncoding_ECALL 2'b10
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`define EnvCtrlEnum_defaultEncoding_EBREAK 2'b11
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`define ShiftCtrlEnum_defaultEncoding_type [1:0]
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`define ShiftCtrlEnum_defaultEncoding_DISABLE_1 2'b00
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`define ShiftCtrlEnum_defaultEncoding_SLL_1 2'b01
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`define ShiftCtrlEnum_defaultEncoding_SRL_1 2'b10
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`define ShiftCtrlEnum_defaultEncoding_SRA_1 2'b11
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`define AluCtrlEnum_defaultEncoding_type [1:0]
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`define AluCtrlEnum_defaultEncoding_ADD_SUB 2'b00
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`define AluCtrlEnum_defaultEncoding_SLT_SLTU 2'b01
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`define AluCtrlEnum_defaultEncoding_BITWISE 2'b10
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`define Src2CtrlEnum_defaultEncoding_type [1:0]
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`define Src2CtrlEnum_defaultEncoding_RS 2'b00
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`define Src2CtrlEnum_defaultEncoding_IMI 2'b01
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`define Src2CtrlEnum_defaultEncoding_IMS 2'b10
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`define Src2CtrlEnum_defaultEncoding_PC 2'b11
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`define BranchCtrlEnum_defaultEncoding_type [1:0]
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`define BranchCtrlEnum_defaultEncoding_INC 2'b00
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`define BranchCtrlEnum_defaultEncoding_B 2'b01
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`define BranchCtrlEnum_defaultEncoding_JAL 2'b10
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`define BranchCtrlEnum_defaultEncoding_JALR 2'b11
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`define AluBitwiseCtrlEnum_defaultEncoding_type [1:0]
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`define AluBitwiseCtrlEnum_defaultEncoding_XOR_1 2'b00
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`define AluBitwiseCtrlEnum_defaultEncoding_OR_1 2'b01
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`define AluBitwiseCtrlEnum_defaultEncoding_AND_1 2'b10
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`define Src1CtrlEnum_defaultEncoding_type [1:0]
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`define Src1CtrlEnum_defaultEncoding_RS 2'b00
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`define Src1CtrlEnum_defaultEncoding_IMU 2'b01
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`define Src1CtrlEnum_defaultEncoding_PC_INCREMENT 2'b10
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`define Src1CtrlEnum_defaultEncoding_URS1 2'b11
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`define MmuPlugin_shared_State_defaultEncoding_type [2:0]
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`define MmuPlugin_shared_State_defaultEncoding_IDLE 3'b000
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`define MmuPlugin_shared_State_defaultEncoding_L1_CMD 3'b001
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`define MmuPlugin_shared_State_defaultEncoding_L1_RSP 3'b010
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`define MmuPlugin_shared_State_defaultEncoding_L0_CMD 3'b011
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`define MmuPlugin_shared_State_defaultEncoding_L0_RSP 3'b100
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module InstructionCache (
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input io_flush,
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input io_cpu_prefetch_isValid,
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output reg io_cpu_prefetch_haltIt,
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input [31:0] io_cpu_prefetch_pc,
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input io_cpu_fetch_isValid,
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input io_cpu_fetch_isStuck,
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input io_cpu_fetch_isRemoved,
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input [31:0] io_cpu_fetch_pc,
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output [31:0] io_cpu_fetch_data,
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input io_cpu_fetch_dataBypassValid,
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input [31:0] io_cpu_fetch_dataBypass,
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output io_cpu_fetch_mmuBus_cmd_isValid,
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output [31:0] io_cpu_fetch_mmuBus_cmd_virtualAddress,
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output io_cpu_fetch_mmuBus_cmd_bypassTranslation,
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input [31:0] io_cpu_fetch_mmuBus_rsp_physicalAddress,
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input io_cpu_fetch_mmuBus_rsp_isIoAccess,
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input io_cpu_fetch_mmuBus_rsp_allowRead,
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input io_cpu_fetch_mmuBus_rsp_allowWrite,
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input io_cpu_fetch_mmuBus_rsp_allowExecute,
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input io_cpu_fetch_mmuBus_rsp_exception,
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input io_cpu_fetch_mmuBus_rsp_refilling,
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output io_cpu_fetch_mmuBus_end,
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input io_cpu_fetch_mmuBus_busy,
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output [31:0] io_cpu_fetch_physicalAddress,
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output io_cpu_fetch_cacheMiss,
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output io_cpu_fetch_error,
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output io_cpu_fetch_mmuRefilling,
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output io_cpu_fetch_mmuException,
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input io_cpu_fetch_isUser,
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output io_cpu_fetch_haltIt,
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input io_cpu_decode_isValid,
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input io_cpu_decode_isStuck,
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input [31:0] io_cpu_decode_pc,
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output [31:0] io_cpu_decode_physicalAddress,
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output [31:0] io_cpu_decode_data,
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input io_cpu_fill_valid,
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input [31:0] io_cpu_fill_payload,
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output io_mem_cmd_valid,
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input io_mem_cmd_ready,
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output [31:0] io_mem_cmd_payload_address,
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output [2:0] io_mem_cmd_payload_size,
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input io_mem_rsp_valid,
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input [31:0] io_mem_rsp_payload_data,
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input io_mem_rsp_payload_error,
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input clk,
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input reset);
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reg [22:0] _zz_10_;
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reg [31:0] _zz_11_;
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wire _zz_12_;
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wire _zz_13_;
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wire [0:0] _zz_14_;
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wire [0:0] _zz_15_;
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wire [22:0] _zz_16_;
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reg _zz_1_;
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reg _zz_2_;
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reg lineLoader_fire;
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reg lineLoader_valid;
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reg [31:0] lineLoader_address;
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reg lineLoader_hadError;
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reg lineLoader_flushPending;
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reg [6:0] lineLoader_flushCounter;
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reg _zz_3_;
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reg lineLoader_cmdSent;
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reg lineLoader_wayToAllocate_willIncrement;
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wire lineLoader_wayToAllocate_willClear;
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wire lineLoader_wayToAllocate_willOverflowIfInc;
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wire lineLoader_wayToAllocate_willOverflow;
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reg [2:0] lineLoader_wordIndex;
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wire lineLoader_write_tag_0_valid;
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wire [5:0] lineLoader_write_tag_0_payload_address;
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wire lineLoader_write_tag_0_payload_data_valid;
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wire lineLoader_write_tag_0_payload_data_error;
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wire [20:0] lineLoader_write_tag_0_payload_data_address;
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wire lineLoader_write_data_0_valid;
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wire [8:0] lineLoader_write_data_0_payload_address;
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wire [31:0] lineLoader_write_data_0_payload_data;
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wire _zz_4_;
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wire [5:0] _zz_5_;
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wire _zz_6_;
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wire fetchStage_read_waysValues_0_tag_valid;
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wire fetchStage_read_waysValues_0_tag_error;
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wire [20:0] fetchStage_read_waysValues_0_tag_address;
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wire [22:0] _zz_7_;
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wire [8:0] _zz_8_;
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wire _zz_9_;
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wire [31:0] fetchStage_read_waysValues_0_data;
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wire fetchStage_hit_hits_0;
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wire fetchStage_hit_valid;
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wire fetchStage_hit_error;
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wire [31:0] fetchStage_hit_data;
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wire [31:0] fetchStage_hit_word;
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reg [22:0] ways_0_tags [0:63];
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reg [31:0] ways_0_datas [0:511];
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assign _zz_12_ = (! lineLoader_flushCounter[6]);
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assign _zz_13_ = (lineLoader_flushPending && (! (lineLoader_valid || io_cpu_fetch_isValid)));
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assign _zz_14_ = _zz_7_[0 : 0];
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assign _zz_15_ = _zz_7_[1 : 1];
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assign _zz_16_ = {lineLoader_write_tag_0_payload_data_address,{lineLoader_write_tag_0_payload_data_error,lineLoader_write_tag_0_payload_data_valid}};
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always @ (posedge clk) begin
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if(_zz_2_) begin
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ways_0_tags[lineLoader_write_tag_0_payload_address] <= _zz_16_;
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end
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end
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always @ (posedge clk) begin
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if(_zz_6_) begin
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_zz_10_ <= ways_0_tags[_zz_5_];
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end
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end
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always @ (posedge clk) begin
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if(_zz_1_) begin
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ways_0_datas[lineLoader_write_data_0_payload_address] <= lineLoader_write_data_0_payload_data;
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end
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end
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always @ (posedge clk) begin
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if(_zz_9_) begin
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_zz_11_ <= ways_0_datas[_zz_8_];
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end
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end
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always @ (*) begin
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_zz_1_ = 1'b0;
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if(lineLoader_write_data_0_valid)begin
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_zz_1_ = 1'b1;
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end
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end
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always @ (*) begin
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_zz_2_ = 1'b0;
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if(lineLoader_write_tag_0_valid)begin
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_zz_2_ = 1'b1;
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end
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end
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assign io_cpu_fetch_haltIt = io_cpu_fetch_mmuBus_busy;
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always @ (*) begin
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lineLoader_fire = 1'b0;
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if(io_mem_rsp_valid)begin
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if((lineLoader_wordIndex == (3'b111)))begin
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lineLoader_fire = 1'b1;
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end
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end
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end
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always @ (*) begin
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io_cpu_prefetch_haltIt = (lineLoader_valid || lineLoader_flushPending);
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if(_zz_12_)begin
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io_cpu_prefetch_haltIt = 1'b1;
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end
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if((! _zz_3_))begin
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io_cpu_prefetch_haltIt = 1'b1;
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end
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if(io_flush)begin
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io_cpu_prefetch_haltIt = 1'b1;
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end
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end
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assign io_mem_cmd_valid = (lineLoader_valid && (! lineLoader_cmdSent));
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assign io_mem_cmd_payload_address = {lineLoader_address[31 : 5],(5'b00000)};
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assign io_mem_cmd_payload_size = (3'b101);
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always @ (*) begin
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lineLoader_wayToAllocate_willIncrement = 1'b0;
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if((! lineLoader_valid))begin
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lineLoader_wayToAllocate_willIncrement = 1'b1;
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end
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end
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assign lineLoader_wayToAllocate_willClear = 1'b0;
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assign lineLoader_wayToAllocate_willOverflowIfInc = 1'b1;
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assign lineLoader_wayToAllocate_willOverflow = (lineLoader_wayToAllocate_willOverflowIfInc && lineLoader_wayToAllocate_willIncrement);
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assign _zz_4_ = 1'b1;
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assign lineLoader_write_tag_0_valid = ((_zz_4_ && lineLoader_fire) || (! lineLoader_flushCounter[6]));
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assign lineLoader_write_tag_0_payload_address = (lineLoader_flushCounter[6] ? lineLoader_address[10 : 5] : lineLoader_flushCounter[5 : 0]);
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assign lineLoader_write_tag_0_payload_data_valid = lineLoader_flushCounter[6];
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assign lineLoader_write_tag_0_payload_data_error = (lineLoader_hadError || io_mem_rsp_payload_error);
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assign lineLoader_write_tag_0_payload_data_address = lineLoader_address[31 : 11];
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assign lineLoader_write_data_0_valid = (io_mem_rsp_valid && _zz_4_);
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assign lineLoader_write_data_0_payload_address = {lineLoader_address[10 : 5],lineLoader_wordIndex};
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assign lineLoader_write_data_0_payload_data = io_mem_rsp_payload_data;
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assign _zz_5_ = io_cpu_prefetch_pc[10 : 5];
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assign _zz_6_ = (! io_cpu_fetch_isStuck);
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assign _zz_7_ = _zz_10_;
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assign fetchStage_read_waysValues_0_tag_valid = _zz_14_[0];
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assign fetchStage_read_waysValues_0_tag_error = _zz_15_[0];
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assign fetchStage_read_waysValues_0_tag_address = _zz_7_[22 : 2];
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assign _zz_8_ = io_cpu_prefetch_pc[10 : 2];
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assign _zz_9_ = (! io_cpu_fetch_isStuck);
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assign fetchStage_read_waysValues_0_data = _zz_11_;
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assign fetchStage_hit_hits_0 = (fetchStage_read_waysValues_0_tag_valid && (fetchStage_read_waysValues_0_tag_address == io_cpu_fetch_mmuBus_rsp_physicalAddress[31 : 11]));
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assign fetchStage_hit_valid = (fetchStage_hit_hits_0 != (1'b0));
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assign fetchStage_hit_error = fetchStage_read_waysValues_0_tag_error;
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assign fetchStage_hit_data = fetchStage_read_waysValues_0_data;
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assign fetchStage_hit_word = fetchStage_hit_data[31 : 0];
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assign io_cpu_fetch_data = (io_cpu_fetch_dataBypassValid ? io_cpu_fetch_dataBypass : fetchStage_hit_word);
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assign io_cpu_fetch_mmuBus_cmd_isValid = io_cpu_fetch_isValid;
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assign io_cpu_fetch_mmuBus_cmd_virtualAddress = io_cpu_fetch_pc;
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assign io_cpu_fetch_mmuBus_cmd_bypassTranslation = 1'b0;
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assign io_cpu_fetch_mmuBus_end = ((! io_cpu_fetch_isStuck) || io_cpu_fetch_isRemoved);
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assign io_cpu_fetch_physicalAddress = io_cpu_fetch_mmuBus_rsp_physicalAddress;
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assign io_cpu_fetch_cacheMiss = (! fetchStage_hit_valid);
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assign io_cpu_fetch_error = fetchStage_hit_error;
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assign io_cpu_fetch_mmuRefilling = io_cpu_fetch_mmuBus_rsp_refilling;
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assign io_cpu_fetch_mmuException = ((! io_cpu_fetch_mmuBus_rsp_refilling) && (io_cpu_fetch_mmuBus_rsp_exception || (! io_cpu_fetch_mmuBus_rsp_allowExecute)));
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always @ (posedge clk) begin
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if(reset) begin
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lineLoader_valid <= 1'b0;
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lineLoader_hadError <= 1'b0;
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lineLoader_flushPending <= 1'b1;
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lineLoader_cmdSent <= 1'b0;
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lineLoader_wordIndex <= (3'b000);
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end else begin
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if(lineLoader_fire)begin
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lineLoader_valid <= 1'b0;
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end
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if(lineLoader_fire)begin
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lineLoader_hadError <= 1'b0;
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end
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if(io_cpu_fill_valid)begin
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lineLoader_valid <= 1'b1;
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end
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if(io_flush)begin
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lineLoader_flushPending <= 1'b1;
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end
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if(_zz_13_)begin
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lineLoader_flushPending <= 1'b0;
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end
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if((io_mem_cmd_valid && io_mem_cmd_ready))begin
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lineLoader_cmdSent <= 1'b1;
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end
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if(lineLoader_fire)begin
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lineLoader_cmdSent <= 1'b0;
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end
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if(io_mem_rsp_valid)begin
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lineLoader_wordIndex <= (lineLoader_wordIndex + (3'b001));
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if(io_mem_rsp_payload_error)begin
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lineLoader_hadError <= 1'b1;
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end
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end
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end
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end
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always @ (posedge clk) begin
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if(io_cpu_fill_valid)begin
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lineLoader_address <= io_cpu_fill_payload;
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end
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if(_zz_12_)begin
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lineLoader_flushCounter <= (lineLoader_flushCounter + (7'b0000001));
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end
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_zz_3_ <= lineLoader_flushCounter[6];
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if(_zz_13_)begin
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lineLoader_flushCounter <= (7'b0000000);
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end
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end
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endmodule
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module VexRiscv (
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input [31:0] externalResetVector,
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input timerInterrupt,
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input softwareInterrupt,
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input [31:0] externalInterruptArray,
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output reg iBusWishbone_CYC,
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output reg iBusWishbone_STB,
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input iBusWishbone_ACK,
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output iBusWishbone_WE,
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output [29:0] iBusWishbone_ADR,
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input [31:0] iBusWishbone_DAT_MISO,
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output [31:0] iBusWishbone_DAT_MOSI,
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output [3:0] iBusWishbone_SEL,
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input iBusWishbone_ERR,
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output [1:0] iBusWishbone_BTE,
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output [2:0] iBusWishbone_CTI,
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output dBusWishbone_CYC,
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output dBusWishbone_STB,
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input dBusWishbone_ACK,
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output dBusWishbone_WE,
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output [29:0] dBusWishbone_ADR,
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input [31:0] dBusWishbone_DAT_MISO,
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output [31:0] dBusWishbone_DAT_MOSI,
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output reg [3:0] dBusWishbone_SEL,
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input dBusWishbone_ERR,
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output [1:0] dBusWishbone_BTE,
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output [2:0] dBusWishbone_CTI,
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input clk,
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input reset);
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wire _zz_152_;
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wire _zz_153_;
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wire _zz_154_;
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wire _zz_155_;
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wire [31:0] _zz_156_;
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wire _zz_157_;
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wire _zz_158_;
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wire _zz_159_;
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wire [31:0] _zz_160_;
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reg _zz_161_;
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reg [31:0] _zz_162_;
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reg [31:0] _zz_163_;
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reg [31:0] _zz_164_;
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reg [3:0] _zz_165_;
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reg [31:0] _zz_166_;
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wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt;
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wire IBusCachedPlugin_cache_io_cpu_fetch_error;
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wire IBusCachedPlugin_cache_io_cpu_fetch_mmuRefilling;
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wire IBusCachedPlugin_cache_io_cpu_fetch_mmuException;
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wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_data;
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wire IBusCachedPlugin_cache_io_cpu_fetch_cacheMiss;
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wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress;
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wire IBusCachedPlugin_cache_io_cpu_fetch_haltIt;
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wire IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_isValid;
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wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_virtualAddress;
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wire IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_bypassTranslation;
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wire IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_end;
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wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_data;
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wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_physicalAddress;
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wire IBusCachedPlugin_cache_io_mem_cmd_valid;
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wire [31:0] IBusCachedPlugin_cache_io_mem_cmd_payload_address;
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wire [2:0] IBusCachedPlugin_cache_io_mem_cmd_payload_size;
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wire _zz_167_;
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wire _zz_168_;
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wire _zz_169_;
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wire _zz_170_;
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wire _zz_171_;
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wire _zz_172_;
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wire _zz_173_;
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wire _zz_174_;
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wire _zz_175_;
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wire _zz_176_;
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wire _zz_177_;
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wire [1:0] _zz_178_;
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wire _zz_179_;
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wire _zz_180_;
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wire _zz_181_;
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wire _zz_182_;
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wire _zz_183_;
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wire _zz_184_;
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wire _zz_185_;
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wire _zz_186_;
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wire _zz_187_;
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wire _zz_188_;
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wire _zz_189_;
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wire _zz_190_;
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wire _zz_191_;
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wire _zz_192_;
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wire _zz_193_;
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wire _zz_194_;
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wire _zz_195_;
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wire _zz_196_;
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wire _zz_197_;
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|
wire _zz_198_;
|
|
wire [1:0] _zz_199_;
|
|
wire _zz_200_;
|
|
wire [3:0] _zz_201_;
|
|
wire [2:0] _zz_202_;
|
|
wire [31:0] _zz_203_;
|
|
wire [2:0] _zz_204_;
|
|
wire [0:0] _zz_205_;
|
|
wire [0:0] _zz_206_;
|
|
wire [0:0] _zz_207_;
|
|
wire [0:0] _zz_208_;
|
|
wire [0:0] _zz_209_;
|
|
wire [0:0] _zz_210_;
|
|
wire [0:0] _zz_211_;
|
|
wire [0:0] _zz_212_;
|
|
wire [0:0] _zz_213_;
|
|
wire [0:0] _zz_214_;
|
|
wire [0:0] _zz_215_;
|
|
wire [0:0] _zz_216_;
|
|
wire [2:0] _zz_217_;
|
|
wire [4:0] _zz_218_;
|
|
wire [11:0] _zz_219_;
|
|
wire [11:0] _zz_220_;
|
|
wire [31:0] _zz_221_;
|
|
wire [31:0] _zz_222_;
|
|
wire [31:0] _zz_223_;
|
|
wire [31:0] _zz_224_;
|
|
wire [31:0] _zz_225_;
|
|
wire [31:0] _zz_226_;
|
|
wire [31:0] _zz_227_;
|
|
wire [31:0] _zz_228_;
|
|
wire [32:0] _zz_229_;
|
|
wire [19:0] _zz_230_;
|
|
wire [11:0] _zz_231_;
|
|
wire [11:0] _zz_232_;
|
|
wire [0:0] _zz_233_;
|
|
wire [0:0] _zz_234_;
|
|
wire [0:0] _zz_235_;
|
|
wire [0:0] _zz_236_;
|
|
wire [0:0] _zz_237_;
|
|
wire [0:0] _zz_238_;
|
|
wire [0:0] _zz_239_;
|
|
wire [0:0] _zz_240_;
|
|
wire [1:0] _zz_241_;
|
|
wire [1:0] _zz_242_;
|
|
wire [2:0] _zz_243_;
|
|
wire [0:0] _zz_244_;
|
|
wire [0:0] _zz_245_;
|
|
wire [0:0] _zz_246_;
|
|
wire [0:0] _zz_247_;
|
|
wire [0:0] _zz_248_;
|
|
wire [0:0] _zz_249_;
|
|
wire [0:0] _zz_250_;
|
|
wire [0:0] _zz_251_;
|
|
wire [0:0] _zz_252_;
|
|
wire [0:0] _zz_253_;
|
|
wire [0:0] _zz_254_;
|
|
wire [0:0] _zz_255_;
|
|
wire [0:0] _zz_256_;
|
|
wire [26:0] _zz_257_;
|
|
wire [6:0] _zz_258_;
|
|
wire [1:0] _zz_259_;
|
|
wire [31:0] _zz_260_;
|
|
wire [31:0] _zz_261_;
|
|
wire [31:0] _zz_262_;
|
|
wire [31:0] _zz_263_;
|
|
wire [31:0] _zz_264_;
|
|
wire [31:0] _zz_265_;
|
|
wire [0:0] _zz_266_;
|
|
wire [5:0] _zz_267_;
|
|
wire [0:0] _zz_268_;
|
|
wire [0:0] _zz_269_;
|
|
wire _zz_270_;
|
|
wire [0:0] _zz_271_;
|
|
wire [22:0] _zz_272_;
|
|
wire [31:0] _zz_273_;
|
|
wire [31:0] _zz_274_;
|
|
wire _zz_275_;
|
|
wire [0:0] _zz_276_;
|
|
wire [2:0] _zz_277_;
|
|
wire [31:0] _zz_278_;
|
|
wire _zz_279_;
|
|
wire _zz_280_;
|
|
wire [0:0] _zz_281_;
|
|
wire [1:0] _zz_282_;
|
|
wire [0:0] _zz_283_;
|
|
wire [0:0] _zz_284_;
|
|
wire _zz_285_;
|
|
wire [0:0] _zz_286_;
|
|
wire [19:0] _zz_287_;
|
|
wire [31:0] _zz_288_;
|
|
wire [31:0] _zz_289_;
|
|
wire [31:0] _zz_290_;
|
|
wire [0:0] _zz_291_;
|
|
wire [0:0] _zz_292_;
|
|
wire [31:0] _zz_293_;
|
|
wire [31:0] _zz_294_;
|
|
wire [31:0] _zz_295_;
|
|
wire [31:0] _zz_296_;
|
|
wire _zz_297_;
|
|
wire _zz_298_;
|
|
wire [31:0] _zz_299_;
|
|
wire [31:0] _zz_300_;
|
|
wire [0:0] _zz_301_;
|
|
wire [1:0] _zz_302_;
|
|
wire [1:0] _zz_303_;
|
|
wire [1:0] _zz_304_;
|
|
wire _zz_305_;
|
|
wire [0:0] _zz_306_;
|
|
wire [17:0] _zz_307_;
|
|
wire [31:0] _zz_308_;
|
|
wire [31:0] _zz_309_;
|
|
wire [31:0] _zz_310_;
|
|
wire [31:0] _zz_311_;
|
|
wire [31:0] _zz_312_;
|
|
wire [31:0] _zz_313_;
|
|
wire [31:0] _zz_314_;
|
|
wire [31:0] _zz_315_;
|
|
wire _zz_316_;
|
|
wire _zz_317_;
|
|
wire _zz_318_;
|
|
wire [0:0] _zz_319_;
|
|
wire [0:0] _zz_320_;
|
|
wire [0:0] _zz_321_;
|
|
wire [0:0] _zz_322_;
|
|
wire _zz_323_;
|
|
wire [0:0] _zz_324_;
|
|
wire [15:0] _zz_325_;
|
|
wire [31:0] _zz_326_;
|
|
wire [31:0] _zz_327_;
|
|
wire _zz_328_;
|
|
wire _zz_329_;
|
|
wire _zz_330_;
|
|
wire [0:0] _zz_331_;
|
|
wire [0:0] _zz_332_;
|
|
wire _zz_333_;
|
|
wire [0:0] _zz_334_;
|
|
wire [12:0] _zz_335_;
|
|
wire [31:0] _zz_336_;
|
|
wire _zz_337_;
|
|
wire _zz_338_;
|
|
wire _zz_339_;
|
|
wire [2:0] _zz_340_;
|
|
wire [2:0] _zz_341_;
|
|
wire _zz_342_;
|
|
wire [0:0] _zz_343_;
|
|
wire [9:0] _zz_344_;
|
|
wire _zz_345_;
|
|
wire _zz_346_;
|
|
wire [0:0] _zz_347_;
|
|
wire [0:0] _zz_348_;
|
|
wire _zz_349_;
|
|
wire [0:0] _zz_350_;
|
|
wire [6:0] _zz_351_;
|
|
wire [31:0] _zz_352_;
|
|
wire _zz_353_;
|
|
wire _zz_354_;
|
|
wire _zz_355_;
|
|
wire [1:0] _zz_356_;
|
|
wire [1:0] _zz_357_;
|
|
wire _zz_358_;
|
|
wire [0:0] _zz_359_;
|
|
wire [2:0] _zz_360_;
|
|
wire [31:0] _zz_361_;
|
|
wire [31:0] _zz_362_;
|
|
wire _zz_363_;
|
|
wire _zz_364_;
|
|
wire [0:0] _zz_365_;
|
|
wire [3:0] _zz_366_;
|
|
wire [1:0] _zz_367_;
|
|
wire [1:0] _zz_368_;
|
|
wire _zz_369_;
|
|
wire _zz_370_;
|
|
wire [31:0] _zz_371_;
|
|
wire [31:0] _zz_372_;
|
|
wire [31:0] _zz_373_;
|
|
wire _zz_374_;
|
|
wire [0:0] _zz_375_;
|
|
wire [0:0] _zz_376_;
|
|
wire [31:0] _zz_377_;
|
|
wire [31:0] _zz_378_;
|
|
wire [31:0] _zz_379_;
|
|
wire [31:0] _zz_380_;
|
|
wire _zz_381_;
|
|
wire _zz_382_;
|
|
wire [31:0] _zz_383_;
|
|
wire [31:0] _zz_384_;
|
|
wire [31:0] _zz_385_;
|
|
wire _zz_386_;
|
|
wire [0:0] _zz_387_;
|
|
wire [15:0] _zz_388_;
|
|
wire [31:0] _zz_389_;
|
|
wire [31:0] _zz_390_;
|
|
wire [31:0] _zz_391_;
|
|
wire _zz_392_;
|
|
wire [0:0] _zz_393_;
|
|
wire [9:0] _zz_394_;
|
|
wire [31:0] _zz_395_;
|
|
wire [31:0] _zz_396_;
|
|
wire [31:0] _zz_397_;
|
|
wire _zz_398_;
|
|
wire [0:0] _zz_399_;
|
|
wire [3:0] _zz_400_;
|
|
wire decode_SRC_LESS_UNSIGNED;
|
|
wire `EnvCtrlEnum_defaultEncoding_type decode_ENV_CTRL;
|
|
wire `EnvCtrlEnum_defaultEncoding_type _zz_1_;
|
|
wire `EnvCtrlEnum_defaultEncoding_type _zz_2_;
|
|
wire `EnvCtrlEnum_defaultEncoding_type _zz_3_;
|
|
wire decode_IS_CSR;
|
|
wire decode_MEMORY_STORE;
|
|
wire `ShiftCtrlEnum_defaultEncoding_type decode_SHIFT_CTRL;
|
|
wire `ShiftCtrlEnum_defaultEncoding_type _zz_4_;
|
|
wire `ShiftCtrlEnum_defaultEncoding_type _zz_5_;
|
|
wire `ShiftCtrlEnum_defaultEncoding_type _zz_6_;
|
|
wire decode_CSR_READ_OPCODE;
|
|
wire `AluCtrlEnum_defaultEncoding_type decode_ALU_CTRL;
|
|
wire `AluCtrlEnum_defaultEncoding_type _zz_7_;
|
|
wire `AluCtrlEnum_defaultEncoding_type _zz_8_;
|
|
wire `AluCtrlEnum_defaultEncoding_type _zz_9_;
|
|
wire `Src2CtrlEnum_defaultEncoding_type decode_SRC2_CTRL;
|
|
wire `Src2CtrlEnum_defaultEncoding_type _zz_10_;
|
|
wire `Src2CtrlEnum_defaultEncoding_type _zz_11_;
|
|
wire `Src2CtrlEnum_defaultEncoding_type _zz_12_;
|
|
wire execute_REGFILE_WRITE_VALID;
|
|
wire `BranchCtrlEnum_defaultEncoding_type decode_BRANCH_CTRL;
|
|
wire `BranchCtrlEnum_defaultEncoding_type _zz_13_;
|
|
wire `BranchCtrlEnum_defaultEncoding_type _zz_14_;
|
|
wire `BranchCtrlEnum_defaultEncoding_type _zz_15_;
|
|
wire decode_CSR_WRITE_OPCODE;
|
|
wire `AluBitwiseCtrlEnum_defaultEncoding_type decode_ALU_BITWISE_CTRL;
|
|
wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_16_;
|
|
wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_17_;
|
|
wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_18_;
|
|
wire [31:0] execute_FORMAL_PC_NEXT;
|
|
wire [31:0] decode_FORMAL_PC_NEXT;
|
|
wire decode_SRC2_FORCE_ZERO;
|
|
wire `Src1CtrlEnum_defaultEncoding_type decode_SRC1_CTRL;
|
|
wire `Src1CtrlEnum_defaultEncoding_type _zz_19_;
|
|
wire `Src1CtrlEnum_defaultEncoding_type _zz_20_;
|
|
wire `Src1CtrlEnum_defaultEncoding_type _zz_21_;
|
|
wire decode_IS_SFENCE_VMA;
|
|
wire decode_MEMORY_ATOMIC;
|
|
wire execute_CSR_READ_OPCODE;
|
|
wire execute_CSR_WRITE_OPCODE;
|
|
wire execute_IS_CSR;
|
|
wire _zz_22_;
|
|
wire _zz_23_;
|
|
wire `EnvCtrlEnum_defaultEncoding_type execute_ENV_CTRL;
|
|
wire `EnvCtrlEnum_defaultEncoding_type _zz_24_;
|
|
wire execute_IS_SFENCE_VMA;
|
|
wire [31:0] execute_BRANCH_CALC;
|
|
wire execute_BRANCH_DO;
|
|
wire [31:0] _zz_25_;
|
|
wire [31:0] execute_RS1;
|
|
wire `BranchCtrlEnum_defaultEncoding_type execute_BRANCH_CTRL;
|
|
wire `BranchCtrlEnum_defaultEncoding_type _zz_26_;
|
|
wire _zz_27_;
|
|
wire `ShiftCtrlEnum_defaultEncoding_type execute_SHIFT_CTRL;
|
|
wire `ShiftCtrlEnum_defaultEncoding_type _zz_28_;
|
|
wire _zz_29_;
|
|
wire [31:0] _zz_30_;
|
|
wire [31:0] _zz_31_;
|
|
wire execute_SRC_LESS_UNSIGNED;
|
|
wire execute_SRC2_FORCE_ZERO;
|
|
wire execute_SRC_USE_SUB_LESS;
|
|
wire `Src2CtrlEnum_defaultEncoding_type execute_SRC2_CTRL;
|
|
wire `Src2CtrlEnum_defaultEncoding_type _zz_32_;
|
|
wire [31:0] _zz_33_;
|
|
wire `Src1CtrlEnum_defaultEncoding_type execute_SRC1_CTRL;
|
|
wire `Src1CtrlEnum_defaultEncoding_type _zz_34_;
|
|
wire [31:0] _zz_35_;
|
|
wire decode_SRC_USE_SUB_LESS;
|
|
wire decode_SRC_ADD_ZERO;
|
|
wire _zz_36_;
|
|
wire [31:0] execute_SRC_ADD_SUB;
|
|
wire execute_SRC_LESS;
|
|
wire `AluCtrlEnum_defaultEncoding_type execute_ALU_CTRL;
|
|
wire `AluCtrlEnum_defaultEncoding_type _zz_37_;
|
|
wire [31:0] _zz_38_;
|
|
wire [31:0] execute_SRC2;
|
|
wire [31:0] execute_SRC1;
|
|
wire `AluBitwiseCtrlEnum_defaultEncoding_type execute_ALU_BITWISE_CTRL;
|
|
wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_39_;
|
|
reg _zz_40_;
|
|
wire [31:0] _zz_41_;
|
|
wire [31:0] _zz_42_;
|
|
reg decode_REGFILE_WRITE_VALID;
|
|
wire decode_LEGAL_INSTRUCTION;
|
|
wire decode_INSTRUCTION_READY;
|
|
wire `AluCtrlEnum_defaultEncoding_type _zz_43_;
|
|
wire _zz_44_;
|
|
wire `EnvCtrlEnum_defaultEncoding_type _zz_45_;
|
|
wire _zz_46_;
|
|
wire _zz_47_;
|
|
wire `Src2CtrlEnum_defaultEncoding_type _zz_48_;
|
|
wire `ShiftCtrlEnum_defaultEncoding_type _zz_49_;
|
|
wire _zz_50_;
|
|
wire _zz_51_;
|
|
wire _zz_52_;
|
|
wire `Src1CtrlEnum_defaultEncoding_type _zz_53_;
|
|
wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_54_;
|
|
wire _zz_55_;
|
|
wire _zz_56_;
|
|
wire _zz_57_;
|
|
wire `BranchCtrlEnum_defaultEncoding_type _zz_58_;
|
|
wire _zz_59_;
|
|
wire _zz_60_;
|
|
reg [31:0] _zz_61_;
|
|
wire [1:0] execute_MEMORY_ADDRESS_LOW;
|
|
wire [31:0] execute_MEMORY_READ_DATA;
|
|
wire [31:0] execute_REGFILE_WRITE_DATA;
|
|
wire [31:0] _zz_62_;
|
|
wire execute_ATOMIC_HIT;
|
|
wire execute_MEMORY_ATOMIC;
|
|
wire _zz_63_;
|
|
wire [31:0] _zz_64_;
|
|
wire _zz_65_;
|
|
wire _zz_66_;
|
|
wire _zz_67_;
|
|
wire _zz_68_;
|
|
wire _zz_69_;
|
|
wire _zz_70_;
|
|
wire execute_MMU_FAULT;
|
|
wire [31:0] execute_MMU_RSP_physicalAddress;
|
|
wire execute_MMU_RSP_isIoAccess;
|
|
wire execute_MMU_RSP_allowRead;
|
|
wire execute_MMU_RSP_allowWrite;
|
|
wire execute_MMU_RSP_allowExecute;
|
|
wire execute_MMU_RSP_exception;
|
|
wire execute_MMU_RSP_refilling;
|
|
wire _zz_71_;
|
|
wire [31:0] execute_SRC_ADD;
|
|
wire [1:0] _zz_72_;
|
|
wire [31:0] execute_RS2;
|
|
wire execute_MEMORY_STORE;
|
|
wire execute_MEMORY_ENABLE;
|
|
wire execute_ALIGNEMENT_FAULT;
|
|
wire _zz_73_;
|
|
wire decode_MEMORY_ENABLE;
|
|
wire decode_FLUSH_ALL;
|
|
reg IBusCachedPlugin_rsp_issueDetected;
|
|
reg _zz_74_;
|
|
reg _zz_75_;
|
|
reg _zz_76_;
|
|
reg [31:0] _zz_77_;
|
|
wire [31:0] decode_PC;
|
|
wire [31:0] _zz_78_;
|
|
wire [31:0] _zz_79_;
|
|
wire [31:0] _zz_80_;
|
|
wire [31:0] decode_INSTRUCTION;
|
|
wire [31:0] execute_PC;
|
|
wire [31:0] execute_INSTRUCTION;
|
|
reg decode_arbitration_haltItself;
|
|
reg decode_arbitration_haltByOther;
|
|
reg decode_arbitration_removeIt;
|
|
wire decode_arbitration_flushIt;
|
|
reg decode_arbitration_flushNext;
|
|
wire decode_arbitration_isValid;
|
|
wire decode_arbitration_isStuck;
|
|
wire decode_arbitration_isStuckByOthers;
|
|
wire decode_arbitration_isFlushed;
|
|
wire decode_arbitration_isMoving;
|
|
wire decode_arbitration_isFiring;
|
|
reg execute_arbitration_haltItself;
|
|
wire execute_arbitration_haltByOther;
|
|
reg execute_arbitration_removeIt;
|
|
reg execute_arbitration_flushIt;
|
|
reg execute_arbitration_flushNext;
|
|
reg execute_arbitration_isValid;
|
|
wire execute_arbitration_isStuck;
|
|
wire execute_arbitration_isStuckByOthers;
|
|
wire execute_arbitration_isFlushed;
|
|
wire execute_arbitration_isMoving;
|
|
wire execute_arbitration_isFiring;
|
|
wire [31:0] lastStageInstruction /* verilator public */ ;
|
|
wire [31:0] lastStagePc /* verilator public */ ;
|
|
wire lastStageIsValid /* verilator public */ ;
|
|
wire lastStageIsFiring /* verilator public */ ;
|
|
reg IBusCachedPlugin_fetcherHalt;
|
|
reg IBusCachedPlugin_fetcherflushIt;
|
|
reg IBusCachedPlugin_incomingInstruction;
|
|
wire IBusCachedPlugin_pcValids_0;
|
|
wire IBusCachedPlugin_pcValids_1;
|
|
wire IBusCachedPlugin_redoBranch_valid;
|
|
wire [31:0] IBusCachedPlugin_redoBranch_payload;
|
|
reg IBusCachedPlugin_decodeExceptionPort_valid;
|
|
reg [3:0] IBusCachedPlugin_decodeExceptionPort_payload_code;
|
|
wire [31:0] IBusCachedPlugin_decodeExceptionPort_payload_badAddr;
|
|
wire IBusCachedPlugin_mmuBus_cmd_isValid;
|
|
wire [31:0] IBusCachedPlugin_mmuBus_cmd_virtualAddress;
|
|
wire IBusCachedPlugin_mmuBus_cmd_bypassTranslation;
|
|
reg [31:0] IBusCachedPlugin_mmuBus_rsp_physicalAddress;
|
|
wire IBusCachedPlugin_mmuBus_rsp_isIoAccess;
|
|
reg IBusCachedPlugin_mmuBus_rsp_allowRead;
|
|
reg IBusCachedPlugin_mmuBus_rsp_allowWrite;
|
|
reg IBusCachedPlugin_mmuBus_rsp_allowExecute;
|
|
reg IBusCachedPlugin_mmuBus_rsp_exception;
|
|
reg IBusCachedPlugin_mmuBus_rsp_refilling;
|
|
wire IBusCachedPlugin_mmuBus_end;
|
|
wire IBusCachedPlugin_mmuBus_busy;
|
|
reg DBusSimplePlugin_memoryExceptionPort_valid;
|
|
reg [3:0] DBusSimplePlugin_memoryExceptionPort_payload_code;
|
|
wire [31:0] DBusSimplePlugin_memoryExceptionPort_payload_badAddr;
|
|
wire DBusSimplePlugin_mmuBus_cmd_isValid;
|
|
wire [31:0] DBusSimplePlugin_mmuBus_cmd_virtualAddress;
|
|
wire DBusSimplePlugin_mmuBus_cmd_bypassTranslation;
|
|
reg [31:0] DBusSimplePlugin_mmuBus_rsp_physicalAddress;
|
|
wire DBusSimplePlugin_mmuBus_rsp_isIoAccess;
|
|
reg DBusSimplePlugin_mmuBus_rsp_allowRead;
|
|
reg DBusSimplePlugin_mmuBus_rsp_allowWrite;
|
|
reg DBusSimplePlugin_mmuBus_rsp_allowExecute;
|
|
reg DBusSimplePlugin_mmuBus_rsp_exception;
|
|
reg DBusSimplePlugin_mmuBus_rsp_refilling;
|
|
wire DBusSimplePlugin_mmuBus_end;
|
|
wire DBusSimplePlugin_mmuBus_busy;
|
|
reg DBusSimplePlugin_redoBranch_valid;
|
|
wire [31:0] DBusSimplePlugin_redoBranch_payload;
|
|
wire decodeExceptionPort_valid;
|
|
wire [3:0] decodeExceptionPort_payload_code;
|
|
wire [31:0] decodeExceptionPort_payload_badAddr;
|
|
wire BranchPlugin_jumpInterface_valid;
|
|
wire [31:0] BranchPlugin_jumpInterface_payload;
|
|
reg BranchPlugin_branchExceptionPort_valid;
|
|
wire [3:0] BranchPlugin_branchExceptionPort_payload_code;
|
|
wire [31:0] BranchPlugin_branchExceptionPort_payload_badAddr;
|
|
reg MmuPlugin_dBusAccess_cmd_valid;
|
|
reg MmuPlugin_dBusAccess_cmd_ready;
|
|
reg [31:0] MmuPlugin_dBusAccess_cmd_payload_address;
|
|
wire [1:0] MmuPlugin_dBusAccess_cmd_payload_size;
|
|
wire MmuPlugin_dBusAccess_cmd_payload_write;
|
|
wire [31:0] MmuPlugin_dBusAccess_cmd_payload_data;
|
|
wire [3:0] MmuPlugin_dBusAccess_cmd_payload_writeMask;
|
|
reg MmuPlugin_dBusAccess_rsp_valid;
|
|
wire [31:0] MmuPlugin_dBusAccess_rsp_payload_data;
|
|
wire MmuPlugin_dBusAccess_rsp_payload_error;
|
|
wire MmuPlugin_dBusAccess_rsp_payload_redo;
|
|
reg CsrPlugin_jumpInterface_valid;
|
|
reg [31:0] CsrPlugin_jumpInterface_payload;
|
|
wire CsrPlugin_exceptionPendings_0;
|
|
wire CsrPlugin_exceptionPendings_1;
|
|
wire externalInterrupt;
|
|
wire contextSwitching;
|
|
reg [1:0] CsrPlugin_privilege;
|
|
wire CsrPlugin_forceMachineWire;
|
|
reg CsrPlugin_selfException_valid;
|
|
reg [3:0] CsrPlugin_selfException_payload_code;
|
|
wire [31:0] CsrPlugin_selfException_payload_badAddr;
|
|
wire CsrPlugin_allowInterrupts;
|
|
wire CsrPlugin_allowException;
|
|
wire IBusCachedPlugin_jump_pcLoad_valid;
|
|
wire [31:0] IBusCachedPlugin_jump_pcLoad_payload;
|
|
wire [3:0] _zz_81_;
|
|
wire [3:0] _zz_82_;
|
|
wire _zz_83_;
|
|
wire _zz_84_;
|
|
wire _zz_85_;
|
|
wire IBusCachedPlugin_fetchPc_output_valid;
|
|
wire IBusCachedPlugin_fetchPc_output_ready;
|
|
wire [31:0] IBusCachedPlugin_fetchPc_output_payload;
|
|
reg [31:0] IBusCachedPlugin_fetchPc_pcReg /* verilator public */ ;
|
|
reg IBusCachedPlugin_fetchPc_corrected;
|
|
reg IBusCachedPlugin_fetchPc_pcRegPropagate;
|
|
reg IBusCachedPlugin_fetchPc_booted;
|
|
reg IBusCachedPlugin_fetchPc_inc;
|
|
reg [31:0] IBusCachedPlugin_fetchPc_pc;
|
|
wire IBusCachedPlugin_iBusRsp_stages_0_input_valid;
|
|
wire IBusCachedPlugin_iBusRsp_stages_0_input_ready;
|
|
wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_input_payload;
|
|
wire IBusCachedPlugin_iBusRsp_stages_0_output_valid;
|
|
wire IBusCachedPlugin_iBusRsp_stages_0_output_ready;
|
|
wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_output_payload;
|
|
reg IBusCachedPlugin_iBusRsp_stages_0_halt;
|
|
wire IBusCachedPlugin_iBusRsp_stages_0_inputSample;
|
|
wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid;
|
|
wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready;
|
|
wire [31:0] IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload;
|
|
wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_valid;
|
|
wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_ready;
|
|
wire [31:0] IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_payload;
|
|
reg IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt;
|
|
wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_inputSample;
|
|
wire _zz_86_;
|
|
wire _zz_87_;
|
|
wire _zz_88_;
|
|
wire _zz_89_;
|
|
reg _zz_90_;
|
|
reg IBusCachedPlugin_iBusRsp_readyForError;
|
|
wire IBusCachedPlugin_iBusRsp_inputBeforeStage_valid;
|
|
wire IBusCachedPlugin_iBusRsp_inputBeforeStage_ready;
|
|
wire [31:0] IBusCachedPlugin_iBusRsp_inputBeforeStage_payload_pc;
|
|
wire IBusCachedPlugin_iBusRsp_inputBeforeStage_payload_rsp_error;
|
|
wire [31:0] IBusCachedPlugin_iBusRsp_inputBeforeStage_payload_rsp_inst;
|
|
wire IBusCachedPlugin_iBusRsp_inputBeforeStage_payload_isRvc;
|
|
wire IBusCachedPlugin_injector_decodeInput_valid;
|
|
wire IBusCachedPlugin_injector_decodeInput_ready;
|
|
wire [31:0] IBusCachedPlugin_injector_decodeInput_payload_pc;
|
|
wire IBusCachedPlugin_injector_decodeInput_payload_rsp_error;
|
|
wire [31:0] IBusCachedPlugin_injector_decodeInput_payload_rsp_inst;
|
|
wire IBusCachedPlugin_injector_decodeInput_payload_isRvc;
|
|
reg _zz_91_;
|
|
reg [31:0] _zz_92_;
|
|
reg _zz_93_;
|
|
reg [31:0] _zz_94_;
|
|
reg _zz_95_;
|
|
reg IBusCachedPlugin_injector_nextPcCalc_valids_0;
|
|
reg IBusCachedPlugin_injector_nextPcCalc_valids_1;
|
|
reg IBusCachedPlugin_injector_nextPcCalc_valids_2;
|
|
reg IBusCachedPlugin_injector_decodeRemoved;
|
|
reg [31:0] IBusCachedPlugin_injector_formal_rawInDecode;
|
|
wire iBus_cmd_valid;
|
|
wire iBus_cmd_ready;
|
|
reg [31:0] iBus_cmd_payload_address;
|
|
wire [2:0] iBus_cmd_payload_size;
|
|
wire iBus_rsp_valid;
|
|
wire [31:0] iBus_rsp_payload_data;
|
|
wire iBus_rsp_payload_error;
|
|
wire [31:0] _zz_96_;
|
|
reg [31:0] IBusCachedPlugin_rspCounter;
|
|
wire IBusCachedPlugin_s0_tightlyCoupledHit;
|
|
reg IBusCachedPlugin_s1_tightlyCoupledHit;
|
|
wire IBusCachedPlugin_rsp_iBusRspOutputHalt;
|
|
reg IBusCachedPlugin_rsp_redoFetch;
|
|
reg dBus_cmd_valid;
|
|
wire dBus_cmd_ready;
|
|
reg dBus_cmd_payload_wr;
|
|
reg [31:0] dBus_cmd_payload_address;
|
|
reg [31:0] dBus_cmd_payload_data;
|
|
reg [1:0] dBus_cmd_payload_size;
|
|
wire dBus_rsp_ready;
|
|
wire dBus_rsp_error;
|
|
wire [31:0] dBus_rsp_data;
|
|
reg _zz_97_;
|
|
reg execute_DBusSimplePlugin_skipCmd;
|
|
reg [31:0] _zz_98_;
|
|
reg [3:0] _zz_99_;
|
|
wire [3:0] execute_DBusSimplePlugin_formalMask;
|
|
reg execute_DBusSimplePlugin_atomic_reserved;
|
|
reg [31:0] execute_DBusSimplePlugin_rspShifted;
|
|
wire _zz_100_;
|
|
reg [31:0] _zz_101_;
|
|
wire _zz_102_;
|
|
reg [31:0] _zz_103_;
|
|
reg [31:0] execute_DBusSimplePlugin_rspFormated;
|
|
reg [1:0] _zz_104_;
|
|
wire [28:0] _zz_105_;
|
|
wire _zz_106_;
|
|
wire _zz_107_;
|
|
wire _zz_108_;
|
|
wire _zz_109_;
|
|
wire _zz_110_;
|
|
wire `BranchCtrlEnum_defaultEncoding_type _zz_111_;
|
|
wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_112_;
|
|
wire `Src1CtrlEnum_defaultEncoding_type _zz_113_;
|
|
wire `ShiftCtrlEnum_defaultEncoding_type _zz_114_;
|
|
wire `Src2CtrlEnum_defaultEncoding_type _zz_115_;
|
|
wire `EnvCtrlEnum_defaultEncoding_type _zz_116_;
|
|
wire `AluCtrlEnum_defaultEncoding_type _zz_117_;
|
|
wire [4:0] execute_RegFilePlugin_regFileReadAddress1;
|
|
wire [4:0] execute_RegFilePlugin_regFileReadAddress2;
|
|
wire _zz_118_;
|
|
wire [31:0] execute_RegFilePlugin_rs1Data;
|
|
wire [31:0] execute_RegFilePlugin_rs2Data;
|
|
wire lastStageRegFileWrite_valid /* verilator public */ ;
|
|
wire [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ;
|
|
wire [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ;
|
|
reg [31:0] execute_IntAluPlugin_bitwise;
|
|
reg [31:0] _zz_119_;
|
|
reg [31:0] _zz_120_;
|
|
wire _zz_121_;
|
|
reg [19:0] _zz_122_;
|
|
wire _zz_123_;
|
|
reg [19:0] _zz_124_;
|
|
reg [31:0] _zz_125_;
|
|
reg [31:0] execute_SrcPlugin_addSub;
|
|
wire execute_SrcPlugin_less;
|
|
reg execute_LightShifterPlugin_isActive;
|
|
wire execute_LightShifterPlugin_isShift;
|
|
reg [4:0] execute_LightShifterPlugin_amplitudeReg;
|
|
wire [4:0] execute_LightShifterPlugin_amplitude;
|
|
reg [31:0] execute_LightShifterPlugin_shiftReg;
|
|
wire [31:0] execute_LightShifterPlugin_shiftInput;
|
|
wire execute_LightShifterPlugin_done;
|
|
reg [31:0] _zz_126_;
|
|
wire execute_BranchPlugin_eq;
|
|
wire [2:0] _zz_127_;
|
|
reg _zz_128_;
|
|
reg _zz_129_;
|
|
wire [31:0] execute_BranchPlugin_branch_src1;
|
|
wire _zz_130_;
|
|
reg [10:0] _zz_131_;
|
|
wire _zz_132_;
|
|
reg [19:0] _zz_133_;
|
|
wire _zz_134_;
|
|
reg [18:0] _zz_135_;
|
|
reg [31:0] _zz_136_;
|
|
wire [31:0] execute_BranchPlugin_branch_src2;
|
|
wire [31:0] execute_BranchPlugin_branchAdder;
|
|
reg MmuPlugin_status_sum;
|
|
reg MmuPlugin_status_mxr;
|
|
reg MmuPlugin_status_mprv;
|
|
reg MmuPlugin_satp_mode;
|
|
reg [19:0] MmuPlugin_satp_ppn;
|
|
reg MmuPlugin_ports_0_cache_0_valid;
|
|
reg MmuPlugin_ports_0_cache_0_exception;
|
|
reg MmuPlugin_ports_0_cache_0_superPage;
|
|
reg [9:0] MmuPlugin_ports_0_cache_0_virtualAddress_0;
|
|
reg [9:0] MmuPlugin_ports_0_cache_0_virtualAddress_1;
|
|
reg [9:0] MmuPlugin_ports_0_cache_0_physicalAddress_0;
|
|
reg [9:0] MmuPlugin_ports_0_cache_0_physicalAddress_1;
|
|
reg MmuPlugin_ports_0_cache_0_allowRead;
|
|
reg MmuPlugin_ports_0_cache_0_allowWrite;
|
|
reg MmuPlugin_ports_0_cache_0_allowExecute;
|
|
reg MmuPlugin_ports_0_cache_0_allowUser;
|
|
reg MmuPlugin_ports_0_cache_1_valid;
|
|
reg MmuPlugin_ports_0_cache_1_exception;
|
|
reg MmuPlugin_ports_0_cache_1_superPage;
|
|
reg [9:0] MmuPlugin_ports_0_cache_1_virtualAddress_0;
|
|
reg [9:0] MmuPlugin_ports_0_cache_1_virtualAddress_1;
|
|
reg [9:0] MmuPlugin_ports_0_cache_1_physicalAddress_0;
|
|
reg [9:0] MmuPlugin_ports_0_cache_1_physicalAddress_1;
|
|
reg MmuPlugin_ports_0_cache_1_allowRead;
|
|
reg MmuPlugin_ports_0_cache_1_allowWrite;
|
|
reg MmuPlugin_ports_0_cache_1_allowExecute;
|
|
reg MmuPlugin_ports_0_cache_1_allowUser;
|
|
wire MmuPlugin_ports_0_cacheHits_0;
|
|
wire MmuPlugin_ports_0_cacheHits_1;
|
|
wire MmuPlugin_ports_0_cacheHit;
|
|
wire MmuPlugin_ports_0_cacheLine_valid;
|
|
wire MmuPlugin_ports_0_cacheLine_exception;
|
|
wire MmuPlugin_ports_0_cacheLine_superPage;
|
|
wire [9:0] MmuPlugin_ports_0_cacheLine_virtualAddress_0;
|
|
wire [9:0] MmuPlugin_ports_0_cacheLine_virtualAddress_1;
|
|
wire [9:0] MmuPlugin_ports_0_cacheLine_physicalAddress_0;
|
|
wire [9:0] MmuPlugin_ports_0_cacheLine_physicalAddress_1;
|
|
wire MmuPlugin_ports_0_cacheLine_allowRead;
|
|
wire MmuPlugin_ports_0_cacheLine_allowWrite;
|
|
wire MmuPlugin_ports_0_cacheLine_allowExecute;
|
|
wire MmuPlugin_ports_0_cacheLine_allowUser;
|
|
reg MmuPlugin_ports_0_entryToReplace_willIncrement;
|
|
wire MmuPlugin_ports_0_entryToReplace_willClear;
|
|
reg [0:0] MmuPlugin_ports_0_entryToReplace_valueNext;
|
|
reg [0:0] MmuPlugin_ports_0_entryToReplace_value;
|
|
wire MmuPlugin_ports_0_entryToReplace_willOverflowIfInc;
|
|
wire MmuPlugin_ports_0_entryToReplace_willOverflow;
|
|
reg MmuPlugin_ports_0_requireMmuLockup;
|
|
reg MmuPlugin_ports_1_cache_0_valid;
|
|
reg MmuPlugin_ports_1_cache_0_exception;
|
|
reg MmuPlugin_ports_1_cache_0_superPage;
|
|
reg [9:0] MmuPlugin_ports_1_cache_0_virtualAddress_0;
|
|
reg [9:0] MmuPlugin_ports_1_cache_0_virtualAddress_1;
|
|
reg [9:0] MmuPlugin_ports_1_cache_0_physicalAddress_0;
|
|
reg [9:0] MmuPlugin_ports_1_cache_0_physicalAddress_1;
|
|
reg MmuPlugin_ports_1_cache_0_allowRead;
|
|
reg MmuPlugin_ports_1_cache_0_allowWrite;
|
|
reg MmuPlugin_ports_1_cache_0_allowExecute;
|
|
reg MmuPlugin_ports_1_cache_0_allowUser;
|
|
reg MmuPlugin_ports_1_cache_1_valid;
|
|
reg MmuPlugin_ports_1_cache_1_exception;
|
|
reg MmuPlugin_ports_1_cache_1_superPage;
|
|
reg [9:0] MmuPlugin_ports_1_cache_1_virtualAddress_0;
|
|
reg [9:0] MmuPlugin_ports_1_cache_1_virtualAddress_1;
|
|
reg [9:0] MmuPlugin_ports_1_cache_1_physicalAddress_0;
|
|
reg [9:0] MmuPlugin_ports_1_cache_1_physicalAddress_1;
|
|
reg MmuPlugin_ports_1_cache_1_allowRead;
|
|
reg MmuPlugin_ports_1_cache_1_allowWrite;
|
|
reg MmuPlugin_ports_1_cache_1_allowExecute;
|
|
reg MmuPlugin_ports_1_cache_1_allowUser;
|
|
wire MmuPlugin_ports_1_cacheHits_0;
|
|
wire MmuPlugin_ports_1_cacheHits_1;
|
|
wire MmuPlugin_ports_1_cacheHit;
|
|
wire MmuPlugin_ports_1_cacheLine_valid;
|
|
wire MmuPlugin_ports_1_cacheLine_exception;
|
|
wire MmuPlugin_ports_1_cacheLine_superPage;
|
|
wire [9:0] MmuPlugin_ports_1_cacheLine_virtualAddress_0;
|
|
wire [9:0] MmuPlugin_ports_1_cacheLine_virtualAddress_1;
|
|
wire [9:0] MmuPlugin_ports_1_cacheLine_physicalAddress_0;
|
|
wire [9:0] MmuPlugin_ports_1_cacheLine_physicalAddress_1;
|
|
wire MmuPlugin_ports_1_cacheLine_allowRead;
|
|
wire MmuPlugin_ports_1_cacheLine_allowWrite;
|
|
wire MmuPlugin_ports_1_cacheLine_allowExecute;
|
|
wire MmuPlugin_ports_1_cacheLine_allowUser;
|
|
reg MmuPlugin_ports_1_entryToReplace_willIncrement;
|
|
wire MmuPlugin_ports_1_entryToReplace_willClear;
|
|
reg [0:0] MmuPlugin_ports_1_entryToReplace_valueNext;
|
|
reg [0:0] MmuPlugin_ports_1_entryToReplace_value;
|
|
wire MmuPlugin_ports_1_entryToReplace_willOverflowIfInc;
|
|
wire MmuPlugin_ports_1_entryToReplace_willOverflow;
|
|
reg MmuPlugin_ports_1_requireMmuLockup;
|
|
reg `MmuPlugin_shared_State_defaultEncoding_type MmuPlugin_shared_state_1_;
|
|
reg [9:0] MmuPlugin_shared_vpn_0;
|
|
reg [9:0] MmuPlugin_shared_vpn_1;
|
|
reg [0:0] MmuPlugin_shared_portId;
|
|
wire MmuPlugin_shared_dBusRsp_pte_V;
|
|
wire MmuPlugin_shared_dBusRsp_pte_R;
|
|
wire MmuPlugin_shared_dBusRsp_pte_W;
|
|
wire MmuPlugin_shared_dBusRsp_pte_X;
|
|
wire MmuPlugin_shared_dBusRsp_pte_U;
|
|
wire MmuPlugin_shared_dBusRsp_pte_G;
|
|
wire MmuPlugin_shared_dBusRsp_pte_A;
|
|
wire MmuPlugin_shared_dBusRsp_pte_D;
|
|
wire [1:0] MmuPlugin_shared_dBusRsp_pte_RSW;
|
|
wire [9:0] MmuPlugin_shared_dBusRsp_pte_PPN0;
|
|
wire [11:0] MmuPlugin_shared_dBusRsp_pte_PPN1;
|
|
wire MmuPlugin_shared_dBusRsp_exception;
|
|
wire MmuPlugin_shared_dBusRsp_leaf;
|
|
reg MmuPlugin_shared_pteBuffer_V;
|
|
reg MmuPlugin_shared_pteBuffer_R;
|
|
reg MmuPlugin_shared_pteBuffer_W;
|
|
reg MmuPlugin_shared_pteBuffer_X;
|
|
reg MmuPlugin_shared_pteBuffer_U;
|
|
reg MmuPlugin_shared_pteBuffer_G;
|
|
reg MmuPlugin_shared_pteBuffer_A;
|
|
reg MmuPlugin_shared_pteBuffer_D;
|
|
reg [1:0] MmuPlugin_shared_pteBuffer_RSW;
|
|
reg [9:0] MmuPlugin_shared_pteBuffer_PPN0;
|
|
reg [11:0] MmuPlugin_shared_pteBuffer_PPN1;
|
|
wire [1:0] CsrPlugin_misa_base;
|
|
wire [25:0] CsrPlugin_misa_extensions;
|
|
reg [1:0] CsrPlugin_mtvec_mode;
|
|
reg [29:0] CsrPlugin_mtvec_base;
|
|
reg [31:0] CsrPlugin_mepc;
|
|
reg CsrPlugin_mstatus_MIE;
|
|
reg CsrPlugin_mstatus_MPIE;
|
|
reg [1:0] CsrPlugin_mstatus_MPP;
|
|
reg CsrPlugin_mip_MEIP;
|
|
reg CsrPlugin_mip_MTIP;
|
|
reg CsrPlugin_mip_MSIP;
|
|
reg CsrPlugin_mie_MEIE;
|
|
reg CsrPlugin_mie_MTIE;
|
|
reg CsrPlugin_mie_MSIE;
|
|
reg [31:0] CsrPlugin_mscratch;
|
|
reg CsrPlugin_mcause_interrupt;
|
|
reg [3:0] CsrPlugin_mcause_exceptionCode;
|
|
reg [31:0] CsrPlugin_mtval;
|
|
reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000;
|
|
reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000;
|
|
wire _zz_137_;
|
|
wire _zz_138_;
|
|
wire _zz_139_;
|
|
reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode;
|
|
reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute;
|
|
reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode;
|
|
reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute;
|
|
reg [3:0] CsrPlugin_exceptionPortCtrl_exceptionContext_code;
|
|
reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr;
|
|
wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped;
|
|
wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege;
|
|
wire [1:0] _zz_140_;
|
|
wire _zz_141_;
|
|
wire [2:0] _zz_142_;
|
|
wire [2:0] _zz_143_;
|
|
wire _zz_144_;
|
|
wire _zz_145_;
|
|
wire [1:0] _zz_146_;
|
|
reg CsrPlugin_interrupt_valid;
|
|
reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ;
|
|
reg [1:0] CsrPlugin_interrupt_targetPrivilege;
|
|
wire CsrPlugin_exception;
|
|
wire CsrPlugin_lastStageWasWfi;
|
|
reg CsrPlugin_pipelineLiberator_done;
|
|
wire CsrPlugin_interruptJump /* verilator public */ ;
|
|
reg CsrPlugin_hadException;
|
|
reg [1:0] CsrPlugin_targetPrivilege;
|
|
reg [3:0] CsrPlugin_trapCause;
|
|
reg [1:0] CsrPlugin_xtvec_mode;
|
|
reg [29:0] CsrPlugin_xtvec_base;
|
|
wire execute_CsrPlugin_inWfi /* verilator public */ ;
|
|
reg execute_CsrPlugin_wfiWake;
|
|
wire execute_CsrPlugin_blockedBySideEffects;
|
|
reg execute_CsrPlugin_illegalAccess;
|
|
reg execute_CsrPlugin_illegalInstruction;
|
|
reg [31:0] execute_CsrPlugin_readData;
|
|
wire execute_CsrPlugin_writeInstruction;
|
|
wire execute_CsrPlugin_readInstruction;
|
|
wire execute_CsrPlugin_writeEnable;
|
|
wire execute_CsrPlugin_readEnable;
|
|
wire [31:0] execute_CsrPlugin_readToWriteData;
|
|
reg [31:0] execute_CsrPlugin_writeData;
|
|
wire [11:0] execute_CsrPlugin_csrAddress;
|
|
reg [31:0] externalInterruptArray_regNext;
|
|
reg [31:0] _zz_147_;
|
|
wire [31:0] _zz_148_;
|
|
reg decode_to_execute_MEMORY_ATOMIC;
|
|
reg decode_to_execute_IS_SFENCE_VMA;
|
|
reg `Src1CtrlEnum_defaultEncoding_type decode_to_execute_SRC1_CTRL;
|
|
reg decode_to_execute_SRC2_FORCE_ZERO;
|
|
reg [31:0] decode_to_execute_FORMAL_PC_NEXT;
|
|
reg `AluBitwiseCtrlEnum_defaultEncoding_type decode_to_execute_ALU_BITWISE_CTRL;
|
|
reg decode_to_execute_SRC_USE_SUB_LESS;
|
|
reg decode_to_execute_CSR_WRITE_OPCODE;
|
|
reg `BranchCtrlEnum_defaultEncoding_type decode_to_execute_BRANCH_CTRL;
|
|
reg decode_to_execute_REGFILE_WRITE_VALID;
|
|
reg `Src2CtrlEnum_defaultEncoding_type decode_to_execute_SRC2_CTRL;
|
|
reg `AluCtrlEnum_defaultEncoding_type decode_to_execute_ALU_CTRL;
|
|
reg decode_to_execute_CSR_READ_OPCODE;
|
|
reg [31:0] decode_to_execute_PC;
|
|
reg `ShiftCtrlEnum_defaultEncoding_type decode_to_execute_SHIFT_CTRL;
|
|
reg decode_to_execute_MEMORY_STORE;
|
|
reg decode_to_execute_IS_CSR;
|
|
reg [31:0] decode_to_execute_INSTRUCTION;
|
|
reg `EnvCtrlEnum_defaultEncoding_type decode_to_execute_ENV_CTRL;
|
|
reg decode_to_execute_MEMORY_ENABLE;
|
|
reg decode_to_execute_SRC_LESS_UNSIGNED;
|
|
reg [2:0] _zz_149_;
|
|
reg _zz_150_;
|
|
reg [31:0] iBusWishbone_DAT_MISO_regNext;
|
|
wire dBus_cmd_halfPipe_valid;
|
|
wire dBus_cmd_halfPipe_ready;
|
|
wire dBus_cmd_halfPipe_payload_wr;
|
|
wire [31:0] dBus_cmd_halfPipe_payload_address;
|
|
wire [31:0] dBus_cmd_halfPipe_payload_data;
|
|
wire [1:0] dBus_cmd_halfPipe_payload_size;
|
|
reg dBus_cmd_halfPipe_regs_valid;
|
|
reg dBus_cmd_halfPipe_regs_ready;
|
|
reg dBus_cmd_halfPipe_regs_payload_wr;
|
|
reg [31:0] dBus_cmd_halfPipe_regs_payload_address;
|
|
reg [31:0] dBus_cmd_halfPipe_regs_payload_data;
|
|
reg [1:0] dBus_cmd_halfPipe_regs_payload_size;
|
|
reg [3:0] _zz_151_;
|
|
`ifndef SYNTHESIS
|
|
reg [47:0] decode_ENV_CTRL_string;
|
|
reg [47:0] _zz_1__string;
|
|
reg [47:0] _zz_2__string;
|
|
reg [47:0] _zz_3__string;
|
|
reg [71:0] decode_SHIFT_CTRL_string;
|
|
reg [71:0] _zz_4__string;
|
|
reg [71:0] _zz_5__string;
|
|
reg [71:0] _zz_6__string;
|
|
reg [63:0] decode_ALU_CTRL_string;
|
|
reg [63:0] _zz_7__string;
|
|
reg [63:0] _zz_8__string;
|
|
reg [63:0] _zz_9__string;
|
|
reg [23:0] decode_SRC2_CTRL_string;
|
|
reg [23:0] _zz_10__string;
|
|
reg [23:0] _zz_11__string;
|
|
reg [23:0] _zz_12__string;
|
|
reg [31:0] decode_BRANCH_CTRL_string;
|
|
reg [31:0] _zz_13__string;
|
|
reg [31:0] _zz_14__string;
|
|
reg [31:0] _zz_15__string;
|
|
reg [39:0] decode_ALU_BITWISE_CTRL_string;
|
|
reg [39:0] _zz_16__string;
|
|
reg [39:0] _zz_17__string;
|
|
reg [39:0] _zz_18__string;
|
|
reg [95:0] decode_SRC1_CTRL_string;
|
|
reg [95:0] _zz_19__string;
|
|
reg [95:0] _zz_20__string;
|
|
reg [95:0] _zz_21__string;
|
|
reg [47:0] execute_ENV_CTRL_string;
|
|
reg [47:0] _zz_24__string;
|
|
reg [31:0] execute_BRANCH_CTRL_string;
|
|
reg [31:0] _zz_26__string;
|
|
reg [71:0] execute_SHIFT_CTRL_string;
|
|
reg [71:0] _zz_28__string;
|
|
reg [23:0] execute_SRC2_CTRL_string;
|
|
reg [23:0] _zz_32__string;
|
|
reg [95:0] execute_SRC1_CTRL_string;
|
|
reg [95:0] _zz_34__string;
|
|
reg [63:0] execute_ALU_CTRL_string;
|
|
reg [63:0] _zz_37__string;
|
|
reg [39:0] execute_ALU_BITWISE_CTRL_string;
|
|
reg [39:0] _zz_39__string;
|
|
reg [63:0] _zz_43__string;
|
|
reg [47:0] _zz_45__string;
|
|
reg [23:0] _zz_48__string;
|
|
reg [71:0] _zz_49__string;
|
|
reg [95:0] _zz_53__string;
|
|
reg [39:0] _zz_54__string;
|
|
reg [31:0] _zz_58__string;
|
|
reg [31:0] _zz_111__string;
|
|
reg [39:0] _zz_112__string;
|
|
reg [95:0] _zz_113__string;
|
|
reg [71:0] _zz_114__string;
|
|
reg [23:0] _zz_115__string;
|
|
reg [47:0] _zz_116__string;
|
|
reg [63:0] _zz_117__string;
|
|
reg [47:0] MmuPlugin_shared_state_1__string;
|
|
reg [95:0] decode_to_execute_SRC1_CTRL_string;
|
|
reg [39:0] decode_to_execute_ALU_BITWISE_CTRL_string;
|
|
reg [31:0] decode_to_execute_BRANCH_CTRL_string;
|
|
reg [23:0] decode_to_execute_SRC2_CTRL_string;
|
|
reg [63:0] decode_to_execute_ALU_CTRL_string;
|
|
reg [71:0] decode_to_execute_SHIFT_CTRL_string;
|
|
reg [47:0] decode_to_execute_ENV_CTRL_string;
|
|
`endif
|
|
|
|
reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ;
|
|
assign _zz_167_ = ((execute_arbitration_isValid && execute_LightShifterPlugin_isShift) && (execute_SRC2[4 : 0] != (5'b00000)));
|
|
assign _zz_168_ = (execute_arbitration_isValid && execute_IS_CSR);
|
|
assign _zz_169_ = ((_zz_154_ && IBusCachedPlugin_cache_io_cpu_fetch_error) && (! _zz_74_));
|
|
assign _zz_170_ = ((_zz_154_ && IBusCachedPlugin_cache_io_cpu_fetch_cacheMiss) && (! _zz_75_));
|
|
assign _zz_171_ = ((_zz_154_ && IBusCachedPlugin_cache_io_cpu_fetch_mmuException) && (! _zz_76_));
|
|
assign _zz_172_ = ((_zz_154_ && IBusCachedPlugin_cache_io_cpu_fetch_mmuRefilling) && (! 1'b0));
|
|
assign _zz_173_ = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != (2'b00));
|
|
assign _zz_174_ = (! execute_arbitration_isStuckByOthers);
|
|
assign _zz_175_ = ({CsrPlugin_selfException_valid,{BranchPlugin_branchExceptionPort_valid,DBusSimplePlugin_memoryExceptionPort_valid}} != (3'b000));
|
|
assign _zz_176_ = (CsrPlugin_hadException || CsrPlugin_interruptJump);
|
|
assign _zz_177_ = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET));
|
|
assign _zz_178_ = execute_INSTRUCTION[29 : 28];
|
|
assign _zz_179_ = (! IBusCachedPlugin_iBusRsp_readyForError);
|
|
assign _zz_180_ = (! ((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (1'b0 || (! execute_arbitration_isStuckByOthers))));
|
|
assign _zz_181_ = ((MmuPlugin_dBusAccess_rsp_valid && (! MmuPlugin_dBusAccess_rsp_payload_redo)) && (MmuPlugin_shared_dBusRsp_leaf || MmuPlugin_shared_dBusRsp_exception));
|
|
assign _zz_182_ = (MmuPlugin_shared_portId == (1'b1));
|
|
assign _zz_183_ = (MmuPlugin_shared_portId == (1'b0));
|
|
assign _zz_184_ = (execute_CsrPlugin_illegalAccess || execute_CsrPlugin_illegalInstruction);
|
|
assign _zz_185_ = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL));
|
|
assign _zz_186_ = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_EBREAK));
|
|
assign _zz_187_ = (iBus_cmd_valid || (_zz_149_ != (3'b000)));
|
|
assign _zz_188_ = (IBusCachedPlugin_mmuBus_cmd_isValid && IBusCachedPlugin_mmuBus_rsp_refilling);
|
|
assign _zz_189_ = (DBusSimplePlugin_mmuBus_cmd_isValid && DBusSimplePlugin_mmuBus_rsp_refilling);
|
|
assign _zz_190_ = (MmuPlugin_ports_0_entryToReplace_value == (1'b0));
|
|
assign _zz_191_ = (MmuPlugin_ports_0_entryToReplace_value == (1'b1));
|
|
assign _zz_192_ = (MmuPlugin_ports_1_entryToReplace_value == (1'b0));
|
|
assign _zz_193_ = (MmuPlugin_ports_1_entryToReplace_value == (1'b1));
|
|
assign _zz_194_ = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < (2'b11)));
|
|
assign _zz_195_ = ((_zz_137_ && 1'b1) && (! 1'b0));
|
|
assign _zz_196_ = ((_zz_138_ && 1'b1) && (! 1'b0));
|
|
assign _zz_197_ = ((_zz_139_ && 1'b1) && (! 1'b0));
|
|
assign _zz_198_ = (! dBus_cmd_halfPipe_regs_valid);
|
|
assign _zz_199_ = execute_INSTRUCTION[13 : 12];
|
|
assign _zz_200_ = execute_INSTRUCTION[13];
|
|
assign _zz_201_ = (_zz_81_ - (4'b0001));
|
|
assign _zz_202_ = {IBusCachedPlugin_fetchPc_inc,(2'b00)};
|
|
assign _zz_203_ = {29'd0, _zz_202_};
|
|
assign _zz_204_ = (execute_MEMORY_STORE ? (3'b110) : (3'b100));
|
|
assign _zz_205_ = (! execute_ATOMIC_HIT);
|
|
assign _zz_206_ = _zz_105_[0 : 0];
|
|
assign _zz_207_ = _zz_105_[4 : 4];
|
|
assign _zz_208_ = _zz_105_[5 : 5];
|
|
assign _zz_209_ = _zz_105_[7 : 7];
|
|
assign _zz_210_ = _zz_105_[13 : 13];
|
|
assign _zz_211_ = _zz_105_[14 : 14];
|
|
assign _zz_212_ = _zz_105_[16 : 16];
|
|
assign _zz_213_ = _zz_105_[21 : 21];
|
|
assign _zz_214_ = _zz_105_[22 : 22];
|
|
assign _zz_215_ = _zz_105_[26 : 26];
|
|
assign _zz_216_ = execute_SRC_LESS;
|
|
assign _zz_217_ = (3'b100);
|
|
assign _zz_218_ = execute_INSTRUCTION[19 : 15];
|
|
assign _zz_219_ = execute_INSTRUCTION[31 : 20];
|
|
assign _zz_220_ = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]};
|
|
assign _zz_221_ = ($signed(_zz_222_) + $signed(_zz_225_));
|
|
assign _zz_222_ = ($signed(_zz_223_) + $signed(_zz_224_));
|
|
assign _zz_223_ = execute_SRC1;
|
|
assign _zz_224_ = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2);
|
|
assign _zz_225_ = (execute_SRC_USE_SUB_LESS ? _zz_226_ : _zz_227_);
|
|
assign _zz_226_ = (32'b00000000000000000000000000000001);
|
|
assign _zz_227_ = (32'b00000000000000000000000000000000);
|
|
assign _zz_228_ = (_zz_229_ >>> 1);
|
|
assign _zz_229_ = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_LightShifterPlugin_shiftInput[31]),execute_LightShifterPlugin_shiftInput};
|
|
assign _zz_230_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]};
|
|
assign _zz_231_ = execute_INSTRUCTION[31 : 20];
|
|
assign _zz_232_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]};
|
|
assign _zz_233_ = MmuPlugin_dBusAccess_rsp_payload_data[0 : 0];
|
|
assign _zz_234_ = MmuPlugin_dBusAccess_rsp_payload_data[1 : 1];
|
|
assign _zz_235_ = MmuPlugin_dBusAccess_rsp_payload_data[2 : 2];
|
|
assign _zz_236_ = MmuPlugin_dBusAccess_rsp_payload_data[3 : 3];
|
|
assign _zz_237_ = MmuPlugin_dBusAccess_rsp_payload_data[4 : 4];
|
|
assign _zz_238_ = MmuPlugin_dBusAccess_rsp_payload_data[5 : 5];
|
|
assign _zz_239_ = MmuPlugin_dBusAccess_rsp_payload_data[6 : 6];
|
|
assign _zz_240_ = MmuPlugin_dBusAccess_rsp_payload_data[7 : 7];
|
|
assign _zz_241_ = (_zz_140_ & (~ _zz_242_));
|
|
assign _zz_242_ = (_zz_140_ - (2'b01));
|
|
assign _zz_243_ = (_zz_142_ - (3'b001));
|
|
assign _zz_244_ = execute_CsrPlugin_writeData[19 : 19];
|
|
assign _zz_245_ = execute_CsrPlugin_writeData[18 : 18];
|
|
assign _zz_246_ = execute_CsrPlugin_writeData[17 : 17];
|
|
assign _zz_247_ = execute_CsrPlugin_writeData[7 : 7];
|
|
assign _zz_248_ = execute_CsrPlugin_writeData[3 : 3];
|
|
assign _zz_249_ = execute_CsrPlugin_writeData[19 : 19];
|
|
assign _zz_250_ = execute_CsrPlugin_writeData[18 : 18];
|
|
assign _zz_251_ = execute_CsrPlugin_writeData[17 : 17];
|
|
assign _zz_252_ = execute_CsrPlugin_writeData[3 : 3];
|
|
assign _zz_253_ = execute_CsrPlugin_writeData[31 : 31];
|
|
assign _zz_254_ = execute_CsrPlugin_writeData[11 : 11];
|
|
assign _zz_255_ = execute_CsrPlugin_writeData[7 : 7];
|
|
assign _zz_256_ = execute_CsrPlugin_writeData[3 : 3];
|
|
assign _zz_257_ = (iBus_cmd_payload_address >>> 5);
|
|
assign _zz_258_ = ({3'd0,_zz_151_} <<< dBus_cmd_halfPipe_payload_address[1 : 0]);
|
|
assign _zz_259_ = {_zz_85_,_zz_84_};
|
|
assign _zz_260_ = (decode_INSTRUCTION & (32'b00000000000000000110000000010100));
|
|
assign _zz_261_ = (32'b00000000000000000110000000010000);
|
|
assign _zz_262_ = (decode_INSTRUCTION & (32'b00000000000000000101000000010100));
|
|
assign _zz_263_ = (32'b00000000000000000100000000010000);
|
|
assign _zz_264_ = (decode_INSTRUCTION & (32'b00000000000000000110000000010100));
|
|
assign _zz_265_ = (32'b00000000000000000010000000010000);
|
|
assign _zz_266_ = _zz_106_;
|
|
assign _zz_267_ = {(_zz_273_ == _zz_274_),{_zz_275_,{_zz_276_,_zz_277_}}};
|
|
assign _zz_268_ = ((decode_INSTRUCTION & _zz_278_) == (32'b00000000000000000000000001010000));
|
|
assign _zz_269_ = (1'b0);
|
|
assign _zz_270_ = ({_zz_279_,_zz_280_} != (2'b00));
|
|
assign _zz_271_ = ({_zz_281_,_zz_282_} != (3'b000));
|
|
assign _zz_272_ = {(_zz_283_ != _zz_284_),{_zz_285_,{_zz_286_,_zz_287_}}};
|
|
assign _zz_273_ = (decode_INSTRUCTION & (32'b00000000000000000001000000010000));
|
|
assign _zz_274_ = (32'b00000000000000000001000000010000);
|
|
assign _zz_275_ = ((decode_INSTRUCTION & _zz_288_) == (32'b00000000000000000010000000010000));
|
|
assign _zz_276_ = (_zz_289_ == _zz_290_);
|
|
assign _zz_277_ = {_zz_108_,{_zz_291_,_zz_292_}};
|
|
assign _zz_278_ = (32'b00010000000000000011000001010000);
|
|
assign _zz_279_ = ((decode_INSTRUCTION & _zz_293_) == (32'b00000000000100000000000001010000));
|
|
assign _zz_280_ = ((decode_INSTRUCTION & _zz_294_) == (32'b00010000000000000000000001010000));
|
|
assign _zz_281_ = (_zz_295_ == _zz_296_);
|
|
assign _zz_282_ = {_zz_297_,_zz_298_};
|
|
assign _zz_283_ = (_zz_299_ == _zz_300_);
|
|
assign _zz_284_ = (1'b0);
|
|
assign _zz_285_ = ({_zz_301_,_zz_302_} != (3'b000));
|
|
assign _zz_286_ = (_zz_303_ != _zz_304_);
|
|
assign _zz_287_ = {_zz_305_,{_zz_306_,_zz_307_}};
|
|
assign _zz_288_ = (32'b00000000000000000010000000010000);
|
|
assign _zz_289_ = (decode_INSTRUCTION & (32'b00000000000000000010000000001000));
|
|
assign _zz_290_ = (32'b00000000000000000010000000001000);
|
|
assign _zz_291_ = (_zz_308_ == _zz_309_);
|
|
assign _zz_292_ = (_zz_310_ == _zz_311_);
|
|
assign _zz_293_ = (32'b00010000000100000011000001010000);
|
|
assign _zz_294_ = (32'b00010010010000000011000001010000);
|
|
assign _zz_295_ = (decode_INSTRUCTION & (32'b00000000000000000000000000110100));
|
|
assign _zz_296_ = (32'b00000000000000000000000000100000);
|
|
assign _zz_297_ = ((decode_INSTRUCTION & _zz_312_) == (32'b00000000000000000000000000100000));
|
|
assign _zz_298_ = ((decode_INSTRUCTION & _zz_313_) == (32'b00001000000000000000000000100000));
|
|
assign _zz_299_ = (decode_INSTRUCTION & (32'b00000000000000000000000000001000));
|
|
assign _zz_300_ = (32'b00000000000000000000000000001000);
|
|
assign _zz_301_ = (_zz_314_ == _zz_315_);
|
|
assign _zz_302_ = {_zz_316_,_zz_317_};
|
|
assign _zz_303_ = {_zz_110_,_zz_318_};
|
|
assign _zz_304_ = (2'b00);
|
|
assign _zz_305_ = ({_zz_319_,_zz_320_} != (2'b00));
|
|
assign _zz_306_ = (_zz_321_ != _zz_322_);
|
|
assign _zz_307_ = {_zz_323_,{_zz_324_,_zz_325_}};
|
|
assign _zz_308_ = (decode_INSTRUCTION & (32'b00000000000000000000000000001100));
|
|
assign _zz_309_ = (32'b00000000000000000000000000000100);
|
|
assign _zz_310_ = (decode_INSTRUCTION & (32'b00000000000000000000000000101000));
|
|
assign _zz_311_ = (32'b00000000000000000000000000000000);
|
|
assign _zz_312_ = (32'b00000000000000000000000001100100);
|
|
assign _zz_313_ = (32'b00001000000000000000000001110000);
|
|
assign _zz_314_ = (decode_INSTRUCTION & (32'b00000000000000000000000001000100));
|
|
assign _zz_315_ = (32'b00000000000000000000000001000000);
|
|
assign _zz_316_ = ((decode_INSTRUCTION & (32'b00000000000000000010000000010100)) == (32'b00000000000000000010000000010000));
|
|
assign _zz_317_ = ((decode_INSTRUCTION & (32'b01000000000000000100000000110100)) == (32'b01000000000000000000000000110000));
|
|
assign _zz_318_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001110000)) == (32'b00000000000000000000000000100000));
|
|
assign _zz_319_ = _zz_110_;
|
|
assign _zz_320_ = ((decode_INSTRUCTION & _zz_326_) == (32'b00000000000000000000000000000000));
|
|
assign _zz_321_ = ((decode_INSTRUCTION & _zz_327_) == (32'b00000000000000000101000000010000));
|
|
assign _zz_322_ = (1'b0);
|
|
assign _zz_323_ = ({_zz_328_,_zz_329_} != (2'b00));
|
|
assign _zz_324_ = (_zz_330_ != (1'b0));
|
|
assign _zz_325_ = {(_zz_331_ != _zz_332_),{_zz_333_,{_zz_334_,_zz_335_}}};
|
|
assign _zz_326_ = (32'b00000000000000000000000000100000);
|
|
assign _zz_327_ = (32'b00000000000000000111000001010100);
|
|
assign _zz_328_ = ((decode_INSTRUCTION & (32'b01000000000000000011000001010100)) == (32'b01000000000000000001000000010000));
|
|
assign _zz_329_ = ((decode_INSTRUCTION & (32'b00000000000000000111000001010100)) == (32'b00000000000000000001000000010000));
|
|
assign _zz_330_ = ((decode_INSTRUCTION & (32'b00000000000000000001000001001000)) == (32'b00000000000000000001000000001000));
|
|
assign _zz_331_ = ((decode_INSTRUCTION & _zz_336_) == (32'b00000000000000000000000000000000));
|
|
assign _zz_332_ = (1'b0);
|
|
assign _zz_333_ = ({_zz_337_,_zz_338_} != (2'b00));
|
|
assign _zz_334_ = (_zz_339_ != (1'b0));
|
|
assign _zz_335_ = {(_zz_340_ != _zz_341_),{_zz_342_,{_zz_343_,_zz_344_}}};
|
|
assign _zz_336_ = (32'b00000000000000000000000000000000);
|
|
assign _zz_337_ = ((decode_INSTRUCTION & (32'b00000000000000000010000000010000)) == (32'b00000000000000000010000000000000));
|
|
assign _zz_338_ = ((decode_INSTRUCTION & (32'b00000000000000000101000000000000)) == (32'b00000000000000000001000000000000));
|
|
assign _zz_339_ = ((decode_INSTRUCTION & (32'b00000010000000000011000001010000)) == (32'b00000010000000000000000001010000));
|
|
assign _zz_340_ = {_zz_106_,{_zz_109_,_zz_345_}};
|
|
assign _zz_341_ = (3'b000);
|
|
assign _zz_342_ = ({_zz_109_,_zz_346_} != (2'b00));
|
|
assign _zz_343_ = (_zz_108_ != (1'b0));
|
|
assign _zz_344_ = {(_zz_347_ != _zz_348_),{_zz_349_,{_zz_350_,_zz_351_}}};
|
|
assign _zz_345_ = ((decode_INSTRUCTION & (32'b00000000000000000010000000010100)) == (32'b00000000000000000000000000000100));
|
|
assign _zz_346_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001001100)) == (32'b00000000000000000000000000000100));
|
|
assign _zz_347_ = ((decode_INSTRUCTION & (32'b00000000000000000001000000000000)) == (32'b00000000000000000001000000000000));
|
|
assign _zz_348_ = (1'b0);
|
|
assign _zz_349_ = (((decode_INSTRUCTION & _zz_352_) == (32'b00000000000000000010000000000000)) != (1'b0));
|
|
assign _zz_350_ = ({_zz_353_,_zz_354_} != (2'b00));
|
|
assign _zz_351_ = {(_zz_355_ != (1'b0)),{(_zz_356_ != _zz_357_),{_zz_358_,{_zz_359_,_zz_360_}}}};
|
|
assign _zz_352_ = (32'b00000000000000000011000000000000);
|
|
assign _zz_353_ = ((decode_INSTRUCTION & (32'b00001000000000000000000000100000)) == (32'b00001000000000000000000000100000));
|
|
assign _zz_354_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000101000)) == (32'b00000000000000000000000000100000));
|
|
assign _zz_355_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000010000)) == (32'b00000000000000000000000000010000));
|
|
assign _zz_356_ = {_zz_107_,(_zz_361_ == _zz_362_)};
|
|
assign _zz_357_ = (2'b00);
|
|
assign _zz_358_ = ({_zz_363_,_zz_364_} != (2'b00));
|
|
assign _zz_359_ = ({_zz_365_,_zz_366_} != (5'b00000));
|
|
assign _zz_360_ = {(_zz_367_ != _zz_368_),{_zz_369_,_zz_370_}};
|
|
assign _zz_361_ = (decode_INSTRUCTION & (32'b00000000000000000000000001011000));
|
|
assign _zz_362_ = (32'b00000000000000000000000000000000);
|
|
assign _zz_363_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001100100)) == (32'b00000000000000000000000000100100));
|
|
assign _zz_364_ = ((decode_INSTRUCTION & (32'b00000000000000000011000001010100)) == (32'b00000000000000000001000000010000));
|
|
assign _zz_365_ = ((decode_INSTRUCTION & _zz_371_) == (32'b00000000000000000000000000000000));
|
|
assign _zz_366_ = {(_zz_372_ == _zz_373_),{_zz_374_,{_zz_375_,_zz_376_}}};
|
|
assign _zz_367_ = {_zz_106_,(_zz_377_ == _zz_378_)};
|
|
assign _zz_368_ = (2'b00);
|
|
assign _zz_369_ = ((_zz_379_ == _zz_380_) != (1'b0));
|
|
assign _zz_370_ = ({_zz_381_,_zz_382_} != (2'b00));
|
|
assign _zz_371_ = (32'b00000000000000000000000001000100);
|
|
assign _zz_372_ = (decode_INSTRUCTION & (32'b00000000000000000000000000011000));
|
|
assign _zz_373_ = (32'b00000000000000000000000000000000);
|
|
assign _zz_374_ = ((decode_INSTRUCTION & (32'b00000000000000000110000000000100)) == (32'b00000000000000000010000000000000));
|
|
assign _zz_375_ = ((decode_INSTRUCTION & (32'b00000000000000000101000000000100)) == (32'b00000000000000000001000000000000));
|
|
assign _zz_376_ = _zz_107_;
|
|
assign _zz_377_ = (decode_INSTRUCTION & (32'b00000000000000000000000000011100));
|
|
assign _zz_378_ = (32'b00000000000000000000000000000100);
|
|
assign _zz_379_ = (decode_INSTRUCTION & (32'b00000000000000000000000001011000));
|
|
assign _zz_380_ = (32'b00000000000000000000000001000000);
|
|
assign _zz_381_ = ((decode_INSTRUCTION & (32'b00000000000000000001000001010000)) == (32'b00000000000000000001000001010000));
|
|
assign _zz_382_ = ((decode_INSTRUCTION & (32'b00000000000000000010000001010000)) == (32'b00000000000000000010000001010000));
|
|
assign _zz_383_ = (32'b00000000000000000001000001111111);
|
|
assign _zz_384_ = (decode_INSTRUCTION & (32'b00000000000000000010000001111111));
|
|
assign _zz_385_ = (32'b00000000000000000010000001110011);
|
|
assign _zz_386_ = ((decode_INSTRUCTION & (32'b00000000000000000100000001111111)) == (32'b00000000000000000100000001100011));
|
|
assign _zz_387_ = ((decode_INSTRUCTION & (32'b00000000000000000010000001111111)) == (32'b00000000000000000010000000010011));
|
|
assign _zz_388_ = {((decode_INSTRUCTION & (32'b00000000000000000110000000111111)) == (32'b00000000000000000000000000100011)),{((decode_INSTRUCTION & (32'b00000000000000000010000001111111)) == (32'b00000000000000000000000000000011)),{((decode_INSTRUCTION & _zz_389_) == (32'b00000000000000000000000000000011)),{(_zz_390_ == _zz_391_),{_zz_392_,{_zz_393_,_zz_394_}}}}}};
|
|
assign _zz_389_ = (32'b00000000000000000101000001011111);
|
|
assign _zz_390_ = (decode_INSTRUCTION & (32'b00000000000000000111000001111011));
|
|
assign _zz_391_ = (32'b00000000000000000000000001100011);
|
|
assign _zz_392_ = ((decode_INSTRUCTION & (32'b00000000000000000110000001111111)) == (32'b00000000000000000000000000001111));
|
|
assign _zz_393_ = ((decode_INSTRUCTION & (32'b11111110000000000000000001111111)) == (32'b00000000000000000000000000110011));
|
|
assign _zz_394_ = {((decode_INSTRUCTION & (32'b11111000000000000111000001111111)) == (32'b00011000000000000010000000101111)),{((decode_INSTRUCTION & (32'b10111100000000000111000001111111)) == (32'b00000000000000000101000000010011)),{((decode_INSTRUCTION & _zz_395_) == (32'b00000000000000000001000000010011)),{(_zz_396_ == _zz_397_),{_zz_398_,{_zz_399_,_zz_400_}}}}}};
|
|
assign _zz_395_ = (32'b11111100000000000011000001111111);
|
|
assign _zz_396_ = (decode_INSTRUCTION & (32'b10111110000000000111000001111111));
|
|
assign _zz_397_ = (32'b00000000000000000101000000110011);
|
|
assign _zz_398_ = ((decode_INSTRUCTION & (32'b10111110000000000111000001111111)) == (32'b00000000000000000000000000110011));
|
|
assign _zz_399_ = ((decode_INSTRUCTION & (32'b11111001111100000111000001111111)) == (32'b00010000000000000010000000101111));
|
|
assign _zz_400_ = {((decode_INSTRUCTION & (32'b11111110000000000111111111111111)) == (32'b00010010000000000000000001110011)),{((decode_INSTRUCTION & (32'b11011111111111111111111111111111)) == (32'b00010000001000000000000001110011)),{((decode_INSTRUCTION & (32'b11111111111011111111111111111111)) == (32'b00000000000000000000000001110011)),((decode_INSTRUCTION & (32'b11111111111111111111111111111111)) == (32'b00010000010100000000000001110011))}}};
|
|
always @ (posedge clk) begin
|
|
if(_zz_40_) begin
|
|
RegFilePlugin_regFile[lastStageRegFileWrite_payload_address] <= lastStageRegFileWrite_payload_data;
|
|
end
|
|
end
|
|
|
|
always @ (posedge clk) begin
|
|
if(_zz_118_) begin
|
|
_zz_162_ <= RegFilePlugin_regFile[execute_RegFilePlugin_regFileReadAddress1];
|
|
end
|
|
end
|
|
|
|
always @ (posedge clk) begin
|
|
if(_zz_118_) begin
|
|
_zz_163_ <= RegFilePlugin_regFile[execute_RegFilePlugin_regFileReadAddress2];
|
|
end
|
|
end
|
|
|
|
InstructionCache IBusCachedPlugin_cache (
|
|
.io_flush(_zz_152_),
|
|
.io_cpu_prefetch_isValid(_zz_153_),
|
|
.io_cpu_prefetch_haltIt(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt),
|
|
.io_cpu_prefetch_pc(IBusCachedPlugin_iBusRsp_stages_0_input_payload),
|
|
.io_cpu_fetch_isValid(_zz_154_),
|
|
.io_cpu_fetch_isStuck(_zz_155_),
|
|
.io_cpu_fetch_isRemoved(IBusCachedPlugin_fetcherflushIt),
|
|
.io_cpu_fetch_pc(IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload),
|
|
.io_cpu_fetch_data(IBusCachedPlugin_cache_io_cpu_fetch_data),
|
|
.io_cpu_fetch_dataBypassValid(IBusCachedPlugin_s1_tightlyCoupledHit),
|
|
.io_cpu_fetch_dataBypass(_zz_156_),
|
|
.io_cpu_fetch_mmuBus_cmd_isValid(IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_isValid),
|
|
.io_cpu_fetch_mmuBus_cmd_virtualAddress(IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_virtualAddress),
|
|
.io_cpu_fetch_mmuBus_cmd_bypassTranslation(IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_bypassTranslation),
|
|
.io_cpu_fetch_mmuBus_rsp_physicalAddress(IBusCachedPlugin_mmuBus_rsp_physicalAddress),
|
|
.io_cpu_fetch_mmuBus_rsp_isIoAccess(IBusCachedPlugin_mmuBus_rsp_isIoAccess),
|
|
.io_cpu_fetch_mmuBus_rsp_allowRead(IBusCachedPlugin_mmuBus_rsp_allowRead),
|
|
.io_cpu_fetch_mmuBus_rsp_allowWrite(IBusCachedPlugin_mmuBus_rsp_allowWrite),
|
|
.io_cpu_fetch_mmuBus_rsp_allowExecute(IBusCachedPlugin_mmuBus_rsp_allowExecute),
|
|
.io_cpu_fetch_mmuBus_rsp_exception(IBusCachedPlugin_mmuBus_rsp_exception),
|
|
.io_cpu_fetch_mmuBus_rsp_refilling(IBusCachedPlugin_mmuBus_rsp_refilling),
|
|
.io_cpu_fetch_mmuBus_end(IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_end),
|
|
.io_cpu_fetch_mmuBus_busy(IBusCachedPlugin_mmuBus_busy),
|
|
.io_cpu_fetch_physicalAddress(IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress),
|
|
.io_cpu_fetch_cacheMiss(IBusCachedPlugin_cache_io_cpu_fetch_cacheMiss),
|
|
.io_cpu_fetch_error(IBusCachedPlugin_cache_io_cpu_fetch_error),
|
|
.io_cpu_fetch_mmuRefilling(IBusCachedPlugin_cache_io_cpu_fetch_mmuRefilling),
|
|
.io_cpu_fetch_mmuException(IBusCachedPlugin_cache_io_cpu_fetch_mmuException),
|
|
.io_cpu_fetch_isUser(_zz_157_),
|
|
.io_cpu_fetch_haltIt(IBusCachedPlugin_cache_io_cpu_fetch_haltIt),
|
|
.io_cpu_decode_isValid(_zz_158_),
|
|
.io_cpu_decode_isStuck(_zz_159_),
|
|
.io_cpu_decode_pc(_zz_160_),
|
|
.io_cpu_decode_physicalAddress(IBusCachedPlugin_cache_io_cpu_decode_physicalAddress),
|
|
.io_cpu_decode_data(IBusCachedPlugin_cache_io_cpu_decode_data),
|
|
.io_cpu_fill_valid(_zz_161_),
|
|
.io_cpu_fill_payload(IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress),
|
|
.io_mem_cmd_valid(IBusCachedPlugin_cache_io_mem_cmd_valid),
|
|
.io_mem_cmd_ready(iBus_cmd_ready),
|
|
.io_mem_cmd_payload_address(IBusCachedPlugin_cache_io_mem_cmd_payload_address),
|
|
.io_mem_cmd_payload_size(IBusCachedPlugin_cache_io_mem_cmd_payload_size),
|
|
.io_mem_rsp_valid(iBus_rsp_valid),
|
|
.io_mem_rsp_payload_data(iBus_rsp_payload_data),
|
|
.io_mem_rsp_payload_error(iBus_rsp_payload_error),
|
|
.clk(clk),
|
|
.reset(reset)
|
|
);
|
|
always @(*) begin
|
|
case(_zz_259_)
|
|
2'b00 : begin
|
|
_zz_164_ = DBusSimplePlugin_redoBranch_payload;
|
|
end
|
|
2'b01 : begin
|
|
_zz_164_ = BranchPlugin_jumpInterface_payload;
|
|
end
|
|
2'b10 : begin
|
|
_zz_164_ = CsrPlugin_jumpInterface_payload;
|
|
end
|
|
default : begin
|
|
_zz_164_ = IBusCachedPlugin_redoBranch_payload;
|
|
end
|
|
endcase
|
|
end
|
|
|
|
always @(*) begin
|
|
case(_zz_146_)
|
|
2'b00 : begin
|
|
_zz_165_ = DBusSimplePlugin_memoryExceptionPort_payload_code;
|
|
_zz_166_ = DBusSimplePlugin_memoryExceptionPort_payload_badAddr;
|
|
end
|
|
2'b01 : begin
|
|
_zz_165_ = BranchPlugin_branchExceptionPort_payload_code;
|
|
_zz_166_ = BranchPlugin_branchExceptionPort_payload_badAddr;
|
|
end
|
|
default : begin
|
|
_zz_165_ = CsrPlugin_selfException_payload_code;
|
|
_zz_166_ = CsrPlugin_selfException_payload_badAddr;
|
|
end
|
|
endcase
|
|
end
|
|
|
|
`ifndef SYNTHESIS
|
|
always @(*) begin
|
|
case(decode_ENV_CTRL)
|
|
`EnvCtrlEnum_defaultEncoding_NONE : decode_ENV_CTRL_string = "NONE ";
|
|
`EnvCtrlEnum_defaultEncoding_XRET : decode_ENV_CTRL_string = "XRET ";
|
|
`EnvCtrlEnum_defaultEncoding_ECALL : decode_ENV_CTRL_string = "ECALL ";
|
|
`EnvCtrlEnum_defaultEncoding_EBREAK : decode_ENV_CTRL_string = "EBREAK";
|
|
default : decode_ENV_CTRL_string = "??????";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(_zz_1_)
|
|
`EnvCtrlEnum_defaultEncoding_NONE : _zz_1__string = "NONE ";
|
|
`EnvCtrlEnum_defaultEncoding_XRET : _zz_1__string = "XRET ";
|
|
`EnvCtrlEnum_defaultEncoding_ECALL : _zz_1__string = "ECALL ";
|
|
`EnvCtrlEnum_defaultEncoding_EBREAK : _zz_1__string = "EBREAK";
|
|
default : _zz_1__string = "??????";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(_zz_2_)
|
|
`EnvCtrlEnum_defaultEncoding_NONE : _zz_2__string = "NONE ";
|
|
`EnvCtrlEnum_defaultEncoding_XRET : _zz_2__string = "XRET ";
|
|
`EnvCtrlEnum_defaultEncoding_ECALL : _zz_2__string = "ECALL ";
|
|
`EnvCtrlEnum_defaultEncoding_EBREAK : _zz_2__string = "EBREAK";
|
|
default : _zz_2__string = "??????";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(_zz_3_)
|
|
`EnvCtrlEnum_defaultEncoding_NONE : _zz_3__string = "NONE ";
|
|
`EnvCtrlEnum_defaultEncoding_XRET : _zz_3__string = "XRET ";
|
|
`EnvCtrlEnum_defaultEncoding_ECALL : _zz_3__string = "ECALL ";
|
|
`EnvCtrlEnum_defaultEncoding_EBREAK : _zz_3__string = "EBREAK";
|
|
default : _zz_3__string = "??????";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(decode_SHIFT_CTRL)
|
|
`ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1";
|
|
`ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 ";
|
|
`ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 ";
|
|
`ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 ";
|
|
default : decode_SHIFT_CTRL_string = "?????????";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(_zz_4_)
|
|
`ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_4__string = "DISABLE_1";
|
|
`ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_4__string = "SLL_1 ";
|
|
`ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_4__string = "SRL_1 ";
|
|
`ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_4__string = "SRA_1 ";
|
|
default : _zz_4__string = "?????????";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(_zz_5_)
|
|
`ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_5__string = "DISABLE_1";
|
|
`ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_5__string = "SLL_1 ";
|
|
`ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_5__string = "SRL_1 ";
|
|
`ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_5__string = "SRA_1 ";
|
|
default : _zz_5__string = "?????????";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(_zz_6_)
|
|
`ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_6__string = "DISABLE_1";
|
|
`ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_6__string = "SLL_1 ";
|
|
`ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_6__string = "SRL_1 ";
|
|
`ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_6__string = "SRA_1 ";
|
|
default : _zz_6__string = "?????????";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(decode_ALU_CTRL)
|
|
`AluCtrlEnum_defaultEncoding_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB ";
|
|
`AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU";
|
|
`AluCtrlEnum_defaultEncoding_BITWISE : decode_ALU_CTRL_string = "BITWISE ";
|
|
default : decode_ALU_CTRL_string = "????????";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(_zz_7_)
|
|
`AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_7__string = "ADD_SUB ";
|
|
`AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_7__string = "SLT_SLTU";
|
|
`AluCtrlEnum_defaultEncoding_BITWISE : _zz_7__string = "BITWISE ";
|
|
default : _zz_7__string = "????????";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(_zz_8_)
|
|
`AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_8__string = "ADD_SUB ";
|
|
`AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_8__string = "SLT_SLTU";
|
|
`AluCtrlEnum_defaultEncoding_BITWISE : _zz_8__string = "BITWISE ";
|
|
default : _zz_8__string = "????????";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(_zz_9_)
|
|
`AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_9__string = "ADD_SUB ";
|
|
`AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_9__string = "SLT_SLTU";
|
|
`AluCtrlEnum_defaultEncoding_BITWISE : _zz_9__string = "BITWISE ";
|
|
default : _zz_9__string = "????????";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(decode_SRC2_CTRL)
|
|
`Src2CtrlEnum_defaultEncoding_RS : decode_SRC2_CTRL_string = "RS ";
|
|
`Src2CtrlEnum_defaultEncoding_IMI : decode_SRC2_CTRL_string = "IMI";
|
|
`Src2CtrlEnum_defaultEncoding_IMS : decode_SRC2_CTRL_string = "IMS";
|
|
`Src2CtrlEnum_defaultEncoding_PC : decode_SRC2_CTRL_string = "PC ";
|
|
default : decode_SRC2_CTRL_string = "???";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(_zz_10_)
|
|
`Src2CtrlEnum_defaultEncoding_RS : _zz_10__string = "RS ";
|
|
`Src2CtrlEnum_defaultEncoding_IMI : _zz_10__string = "IMI";
|
|
`Src2CtrlEnum_defaultEncoding_IMS : _zz_10__string = "IMS";
|
|
`Src2CtrlEnum_defaultEncoding_PC : _zz_10__string = "PC ";
|
|
default : _zz_10__string = "???";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(_zz_11_)
|
|
`Src2CtrlEnum_defaultEncoding_RS : _zz_11__string = "RS ";
|
|
`Src2CtrlEnum_defaultEncoding_IMI : _zz_11__string = "IMI";
|
|
`Src2CtrlEnum_defaultEncoding_IMS : _zz_11__string = "IMS";
|
|
`Src2CtrlEnum_defaultEncoding_PC : _zz_11__string = "PC ";
|
|
default : _zz_11__string = "???";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(_zz_12_)
|
|
`Src2CtrlEnum_defaultEncoding_RS : _zz_12__string = "RS ";
|
|
`Src2CtrlEnum_defaultEncoding_IMI : _zz_12__string = "IMI";
|
|
`Src2CtrlEnum_defaultEncoding_IMS : _zz_12__string = "IMS";
|
|
`Src2CtrlEnum_defaultEncoding_PC : _zz_12__string = "PC ";
|
|
default : _zz_12__string = "???";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(decode_BRANCH_CTRL)
|
|
`BranchCtrlEnum_defaultEncoding_INC : decode_BRANCH_CTRL_string = "INC ";
|
|
`BranchCtrlEnum_defaultEncoding_B : decode_BRANCH_CTRL_string = "B ";
|
|
`BranchCtrlEnum_defaultEncoding_JAL : decode_BRANCH_CTRL_string = "JAL ";
|
|
`BranchCtrlEnum_defaultEncoding_JALR : decode_BRANCH_CTRL_string = "JALR";
|
|
default : decode_BRANCH_CTRL_string = "????";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(_zz_13_)
|
|
`BranchCtrlEnum_defaultEncoding_INC : _zz_13__string = "INC ";
|
|
`BranchCtrlEnum_defaultEncoding_B : _zz_13__string = "B ";
|
|
`BranchCtrlEnum_defaultEncoding_JAL : _zz_13__string = "JAL ";
|
|
`BranchCtrlEnum_defaultEncoding_JALR : _zz_13__string = "JALR";
|
|
default : _zz_13__string = "????";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(_zz_14_)
|
|
`BranchCtrlEnum_defaultEncoding_INC : _zz_14__string = "INC ";
|
|
`BranchCtrlEnum_defaultEncoding_B : _zz_14__string = "B ";
|
|
`BranchCtrlEnum_defaultEncoding_JAL : _zz_14__string = "JAL ";
|
|
`BranchCtrlEnum_defaultEncoding_JALR : _zz_14__string = "JALR";
|
|
default : _zz_14__string = "????";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(_zz_15_)
|
|
`BranchCtrlEnum_defaultEncoding_INC : _zz_15__string = "INC ";
|
|
`BranchCtrlEnum_defaultEncoding_B : _zz_15__string = "B ";
|
|
`BranchCtrlEnum_defaultEncoding_JAL : _zz_15__string = "JAL ";
|
|
`BranchCtrlEnum_defaultEncoding_JALR : _zz_15__string = "JALR";
|
|
default : _zz_15__string = "????";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(decode_ALU_BITWISE_CTRL)
|
|
`AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1";
|
|
`AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 ";
|
|
`AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1";
|
|
default : decode_ALU_BITWISE_CTRL_string = "?????";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(_zz_16_)
|
|
`AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_16__string = "XOR_1";
|
|
`AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_16__string = "OR_1 ";
|
|
`AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_16__string = "AND_1";
|
|
default : _zz_16__string = "?????";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(_zz_17_)
|
|
`AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_17__string = "XOR_1";
|
|
`AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_17__string = "OR_1 ";
|
|
`AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_17__string = "AND_1";
|
|
default : _zz_17__string = "?????";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(_zz_18_)
|
|
`AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_18__string = "XOR_1";
|
|
`AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_18__string = "OR_1 ";
|
|
`AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_18__string = "AND_1";
|
|
default : _zz_18__string = "?????";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(decode_SRC1_CTRL)
|
|
`Src1CtrlEnum_defaultEncoding_RS : decode_SRC1_CTRL_string = "RS ";
|
|
`Src1CtrlEnum_defaultEncoding_IMU : decode_SRC1_CTRL_string = "IMU ";
|
|
`Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT";
|
|
`Src1CtrlEnum_defaultEncoding_URS1 : decode_SRC1_CTRL_string = "URS1 ";
|
|
default : decode_SRC1_CTRL_string = "????????????";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(_zz_19_)
|
|
`Src1CtrlEnum_defaultEncoding_RS : _zz_19__string = "RS ";
|
|
`Src1CtrlEnum_defaultEncoding_IMU : _zz_19__string = "IMU ";
|
|
`Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_19__string = "PC_INCREMENT";
|
|
`Src1CtrlEnum_defaultEncoding_URS1 : _zz_19__string = "URS1 ";
|
|
default : _zz_19__string = "????????????";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(_zz_20_)
|
|
`Src1CtrlEnum_defaultEncoding_RS : _zz_20__string = "RS ";
|
|
`Src1CtrlEnum_defaultEncoding_IMU : _zz_20__string = "IMU ";
|
|
`Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_20__string = "PC_INCREMENT";
|
|
`Src1CtrlEnum_defaultEncoding_URS1 : _zz_20__string = "URS1 ";
|
|
default : _zz_20__string = "????????????";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(_zz_21_)
|
|
`Src1CtrlEnum_defaultEncoding_RS : _zz_21__string = "RS ";
|
|
`Src1CtrlEnum_defaultEncoding_IMU : _zz_21__string = "IMU ";
|
|
`Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_21__string = "PC_INCREMENT";
|
|
`Src1CtrlEnum_defaultEncoding_URS1 : _zz_21__string = "URS1 ";
|
|
default : _zz_21__string = "????????????";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(execute_ENV_CTRL)
|
|
`EnvCtrlEnum_defaultEncoding_NONE : execute_ENV_CTRL_string = "NONE ";
|
|
`EnvCtrlEnum_defaultEncoding_XRET : execute_ENV_CTRL_string = "XRET ";
|
|
`EnvCtrlEnum_defaultEncoding_ECALL : execute_ENV_CTRL_string = "ECALL ";
|
|
`EnvCtrlEnum_defaultEncoding_EBREAK : execute_ENV_CTRL_string = "EBREAK";
|
|
default : execute_ENV_CTRL_string = "??????";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(_zz_24_)
|
|
`EnvCtrlEnum_defaultEncoding_NONE : _zz_24__string = "NONE ";
|
|
`EnvCtrlEnum_defaultEncoding_XRET : _zz_24__string = "XRET ";
|
|
`EnvCtrlEnum_defaultEncoding_ECALL : _zz_24__string = "ECALL ";
|
|
`EnvCtrlEnum_defaultEncoding_EBREAK : _zz_24__string = "EBREAK";
|
|
default : _zz_24__string = "??????";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(execute_BRANCH_CTRL)
|
|
`BranchCtrlEnum_defaultEncoding_INC : execute_BRANCH_CTRL_string = "INC ";
|
|
`BranchCtrlEnum_defaultEncoding_B : execute_BRANCH_CTRL_string = "B ";
|
|
`BranchCtrlEnum_defaultEncoding_JAL : execute_BRANCH_CTRL_string = "JAL ";
|
|
`BranchCtrlEnum_defaultEncoding_JALR : execute_BRANCH_CTRL_string = "JALR";
|
|
default : execute_BRANCH_CTRL_string = "????";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(_zz_26_)
|
|
`BranchCtrlEnum_defaultEncoding_INC : _zz_26__string = "INC ";
|
|
`BranchCtrlEnum_defaultEncoding_B : _zz_26__string = "B ";
|
|
`BranchCtrlEnum_defaultEncoding_JAL : _zz_26__string = "JAL ";
|
|
`BranchCtrlEnum_defaultEncoding_JALR : _zz_26__string = "JALR";
|
|
default : _zz_26__string = "????";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(execute_SHIFT_CTRL)
|
|
`ShiftCtrlEnum_defaultEncoding_DISABLE_1 : execute_SHIFT_CTRL_string = "DISABLE_1";
|
|
`ShiftCtrlEnum_defaultEncoding_SLL_1 : execute_SHIFT_CTRL_string = "SLL_1 ";
|
|
`ShiftCtrlEnum_defaultEncoding_SRL_1 : execute_SHIFT_CTRL_string = "SRL_1 ";
|
|
`ShiftCtrlEnum_defaultEncoding_SRA_1 : execute_SHIFT_CTRL_string = "SRA_1 ";
|
|
default : execute_SHIFT_CTRL_string = "?????????";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(_zz_28_)
|
|
`ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_28__string = "DISABLE_1";
|
|
`ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_28__string = "SLL_1 ";
|
|
`ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_28__string = "SRL_1 ";
|
|
`ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_28__string = "SRA_1 ";
|
|
default : _zz_28__string = "?????????";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(execute_SRC2_CTRL)
|
|
`Src2CtrlEnum_defaultEncoding_RS : execute_SRC2_CTRL_string = "RS ";
|
|
`Src2CtrlEnum_defaultEncoding_IMI : execute_SRC2_CTRL_string = "IMI";
|
|
`Src2CtrlEnum_defaultEncoding_IMS : execute_SRC2_CTRL_string = "IMS";
|
|
`Src2CtrlEnum_defaultEncoding_PC : execute_SRC2_CTRL_string = "PC ";
|
|
default : execute_SRC2_CTRL_string = "???";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(_zz_32_)
|
|
`Src2CtrlEnum_defaultEncoding_RS : _zz_32__string = "RS ";
|
|
`Src2CtrlEnum_defaultEncoding_IMI : _zz_32__string = "IMI";
|
|
`Src2CtrlEnum_defaultEncoding_IMS : _zz_32__string = "IMS";
|
|
`Src2CtrlEnum_defaultEncoding_PC : _zz_32__string = "PC ";
|
|
default : _zz_32__string = "???";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(execute_SRC1_CTRL)
|
|
`Src1CtrlEnum_defaultEncoding_RS : execute_SRC1_CTRL_string = "RS ";
|
|
`Src1CtrlEnum_defaultEncoding_IMU : execute_SRC1_CTRL_string = "IMU ";
|
|
`Src1CtrlEnum_defaultEncoding_PC_INCREMENT : execute_SRC1_CTRL_string = "PC_INCREMENT";
|
|
`Src1CtrlEnum_defaultEncoding_URS1 : execute_SRC1_CTRL_string = "URS1 ";
|
|
default : execute_SRC1_CTRL_string = "????????????";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(_zz_34_)
|
|
`Src1CtrlEnum_defaultEncoding_RS : _zz_34__string = "RS ";
|
|
`Src1CtrlEnum_defaultEncoding_IMU : _zz_34__string = "IMU ";
|
|
`Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_34__string = "PC_INCREMENT";
|
|
`Src1CtrlEnum_defaultEncoding_URS1 : _zz_34__string = "URS1 ";
|
|
default : _zz_34__string = "????????????";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(execute_ALU_CTRL)
|
|
`AluCtrlEnum_defaultEncoding_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB ";
|
|
`AluCtrlEnum_defaultEncoding_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU";
|
|
`AluCtrlEnum_defaultEncoding_BITWISE : execute_ALU_CTRL_string = "BITWISE ";
|
|
default : execute_ALU_CTRL_string = "????????";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(_zz_37_)
|
|
`AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_37__string = "ADD_SUB ";
|
|
`AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_37__string = "SLT_SLTU";
|
|
`AluCtrlEnum_defaultEncoding_BITWISE : _zz_37__string = "BITWISE ";
|
|
default : _zz_37__string = "????????";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(execute_ALU_BITWISE_CTRL)
|
|
`AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1";
|
|
`AluBitwiseCtrlEnum_defaultEncoding_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 ";
|
|
`AluBitwiseCtrlEnum_defaultEncoding_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1";
|
|
default : execute_ALU_BITWISE_CTRL_string = "?????";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(_zz_39_)
|
|
`AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_39__string = "XOR_1";
|
|
`AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_39__string = "OR_1 ";
|
|
`AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_39__string = "AND_1";
|
|
default : _zz_39__string = "?????";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(_zz_43_)
|
|
`AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_43__string = "ADD_SUB ";
|
|
`AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_43__string = "SLT_SLTU";
|
|
`AluCtrlEnum_defaultEncoding_BITWISE : _zz_43__string = "BITWISE ";
|
|
default : _zz_43__string = "????????";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(_zz_45_)
|
|
`EnvCtrlEnum_defaultEncoding_NONE : _zz_45__string = "NONE ";
|
|
`EnvCtrlEnum_defaultEncoding_XRET : _zz_45__string = "XRET ";
|
|
`EnvCtrlEnum_defaultEncoding_ECALL : _zz_45__string = "ECALL ";
|
|
`EnvCtrlEnum_defaultEncoding_EBREAK : _zz_45__string = "EBREAK";
|
|
default : _zz_45__string = "??????";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(_zz_48_)
|
|
`Src2CtrlEnum_defaultEncoding_RS : _zz_48__string = "RS ";
|
|
`Src2CtrlEnum_defaultEncoding_IMI : _zz_48__string = "IMI";
|
|
`Src2CtrlEnum_defaultEncoding_IMS : _zz_48__string = "IMS";
|
|
`Src2CtrlEnum_defaultEncoding_PC : _zz_48__string = "PC ";
|
|
default : _zz_48__string = "???";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(_zz_49_)
|
|
`ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_49__string = "DISABLE_1";
|
|
`ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_49__string = "SLL_1 ";
|
|
`ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_49__string = "SRL_1 ";
|
|
`ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_49__string = "SRA_1 ";
|
|
default : _zz_49__string = "?????????";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(_zz_53_)
|
|
`Src1CtrlEnum_defaultEncoding_RS : _zz_53__string = "RS ";
|
|
`Src1CtrlEnum_defaultEncoding_IMU : _zz_53__string = "IMU ";
|
|
`Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_53__string = "PC_INCREMENT";
|
|
`Src1CtrlEnum_defaultEncoding_URS1 : _zz_53__string = "URS1 ";
|
|
default : _zz_53__string = "????????????";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(_zz_54_)
|
|
`AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_54__string = "XOR_1";
|
|
`AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_54__string = "OR_1 ";
|
|
`AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_54__string = "AND_1";
|
|
default : _zz_54__string = "?????";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(_zz_58_)
|
|
`BranchCtrlEnum_defaultEncoding_INC : _zz_58__string = "INC ";
|
|
`BranchCtrlEnum_defaultEncoding_B : _zz_58__string = "B ";
|
|
`BranchCtrlEnum_defaultEncoding_JAL : _zz_58__string = "JAL ";
|
|
`BranchCtrlEnum_defaultEncoding_JALR : _zz_58__string = "JALR";
|
|
default : _zz_58__string = "????";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(_zz_111_)
|
|
`BranchCtrlEnum_defaultEncoding_INC : _zz_111__string = "INC ";
|
|
`BranchCtrlEnum_defaultEncoding_B : _zz_111__string = "B ";
|
|
`BranchCtrlEnum_defaultEncoding_JAL : _zz_111__string = "JAL ";
|
|
`BranchCtrlEnum_defaultEncoding_JALR : _zz_111__string = "JALR";
|
|
default : _zz_111__string = "????";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(_zz_112_)
|
|
`AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_112__string = "XOR_1";
|
|
`AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_112__string = "OR_1 ";
|
|
`AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_112__string = "AND_1";
|
|
default : _zz_112__string = "?????";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(_zz_113_)
|
|
`Src1CtrlEnum_defaultEncoding_RS : _zz_113__string = "RS ";
|
|
`Src1CtrlEnum_defaultEncoding_IMU : _zz_113__string = "IMU ";
|
|
`Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_113__string = "PC_INCREMENT";
|
|
`Src1CtrlEnum_defaultEncoding_URS1 : _zz_113__string = "URS1 ";
|
|
default : _zz_113__string = "????????????";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(_zz_114_)
|
|
`ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_114__string = "DISABLE_1";
|
|
`ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_114__string = "SLL_1 ";
|
|
`ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_114__string = "SRL_1 ";
|
|
`ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_114__string = "SRA_1 ";
|
|
default : _zz_114__string = "?????????";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(_zz_115_)
|
|
`Src2CtrlEnum_defaultEncoding_RS : _zz_115__string = "RS ";
|
|
`Src2CtrlEnum_defaultEncoding_IMI : _zz_115__string = "IMI";
|
|
`Src2CtrlEnum_defaultEncoding_IMS : _zz_115__string = "IMS";
|
|
`Src2CtrlEnum_defaultEncoding_PC : _zz_115__string = "PC ";
|
|
default : _zz_115__string = "???";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(_zz_116_)
|
|
`EnvCtrlEnum_defaultEncoding_NONE : _zz_116__string = "NONE ";
|
|
`EnvCtrlEnum_defaultEncoding_XRET : _zz_116__string = "XRET ";
|
|
`EnvCtrlEnum_defaultEncoding_ECALL : _zz_116__string = "ECALL ";
|
|
`EnvCtrlEnum_defaultEncoding_EBREAK : _zz_116__string = "EBREAK";
|
|
default : _zz_116__string = "??????";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(_zz_117_)
|
|
`AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_117__string = "ADD_SUB ";
|
|
`AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_117__string = "SLT_SLTU";
|
|
`AluCtrlEnum_defaultEncoding_BITWISE : _zz_117__string = "BITWISE ";
|
|
default : _zz_117__string = "????????";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(MmuPlugin_shared_state_1_)
|
|
`MmuPlugin_shared_State_defaultEncoding_IDLE : MmuPlugin_shared_state_1__string = "IDLE ";
|
|
`MmuPlugin_shared_State_defaultEncoding_L1_CMD : MmuPlugin_shared_state_1__string = "L1_CMD";
|
|
`MmuPlugin_shared_State_defaultEncoding_L1_RSP : MmuPlugin_shared_state_1__string = "L1_RSP";
|
|
`MmuPlugin_shared_State_defaultEncoding_L0_CMD : MmuPlugin_shared_state_1__string = "L0_CMD";
|
|
`MmuPlugin_shared_State_defaultEncoding_L0_RSP : MmuPlugin_shared_state_1__string = "L0_RSP";
|
|
default : MmuPlugin_shared_state_1__string = "??????";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(decode_to_execute_SRC1_CTRL)
|
|
`Src1CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC1_CTRL_string = "RS ";
|
|
`Src1CtrlEnum_defaultEncoding_IMU : decode_to_execute_SRC1_CTRL_string = "IMU ";
|
|
`Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT";
|
|
`Src1CtrlEnum_defaultEncoding_URS1 : decode_to_execute_SRC1_CTRL_string = "URS1 ";
|
|
default : decode_to_execute_SRC1_CTRL_string = "????????????";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(decode_to_execute_ALU_BITWISE_CTRL)
|
|
`AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1";
|
|
`AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 ";
|
|
`AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1";
|
|
default : decode_to_execute_ALU_BITWISE_CTRL_string = "?????";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(decode_to_execute_BRANCH_CTRL)
|
|
`BranchCtrlEnum_defaultEncoding_INC : decode_to_execute_BRANCH_CTRL_string = "INC ";
|
|
`BranchCtrlEnum_defaultEncoding_B : decode_to_execute_BRANCH_CTRL_string = "B ";
|
|
`BranchCtrlEnum_defaultEncoding_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL ";
|
|
`BranchCtrlEnum_defaultEncoding_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR";
|
|
default : decode_to_execute_BRANCH_CTRL_string = "????";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(decode_to_execute_SRC2_CTRL)
|
|
`Src2CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC2_CTRL_string = "RS ";
|
|
`Src2CtrlEnum_defaultEncoding_IMI : decode_to_execute_SRC2_CTRL_string = "IMI";
|
|
`Src2CtrlEnum_defaultEncoding_IMS : decode_to_execute_SRC2_CTRL_string = "IMS";
|
|
`Src2CtrlEnum_defaultEncoding_PC : decode_to_execute_SRC2_CTRL_string = "PC ";
|
|
default : decode_to_execute_SRC2_CTRL_string = "???";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(decode_to_execute_ALU_CTRL)
|
|
`AluCtrlEnum_defaultEncoding_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB ";
|
|
`AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU";
|
|
`AluCtrlEnum_defaultEncoding_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE ";
|
|
default : decode_to_execute_ALU_CTRL_string = "????????";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(decode_to_execute_SHIFT_CTRL)
|
|
`ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_to_execute_SHIFT_CTRL_string = "DISABLE_1";
|
|
`ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_to_execute_SHIFT_CTRL_string = "SLL_1 ";
|
|
`ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_to_execute_SHIFT_CTRL_string = "SRL_1 ";
|
|
`ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_to_execute_SHIFT_CTRL_string = "SRA_1 ";
|
|
default : decode_to_execute_SHIFT_CTRL_string = "?????????";
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
case(decode_to_execute_ENV_CTRL)
|
|
`EnvCtrlEnum_defaultEncoding_NONE : decode_to_execute_ENV_CTRL_string = "NONE ";
|
|
`EnvCtrlEnum_defaultEncoding_XRET : decode_to_execute_ENV_CTRL_string = "XRET ";
|
|
`EnvCtrlEnum_defaultEncoding_ECALL : decode_to_execute_ENV_CTRL_string = "ECALL ";
|
|
`EnvCtrlEnum_defaultEncoding_EBREAK : decode_to_execute_ENV_CTRL_string = "EBREAK";
|
|
default : decode_to_execute_ENV_CTRL_string = "??????";
|
|
endcase
|
|
end
|
|
`endif
|
|
|
|
assign decode_SRC_LESS_UNSIGNED = _zz_51_;
|
|
assign decode_ENV_CTRL = _zz_1_;
|
|
assign _zz_2_ = _zz_3_;
|
|
assign decode_IS_CSR = _zz_59_;
|
|
assign decode_MEMORY_STORE = _zz_55_;
|
|
assign decode_SHIFT_CTRL = _zz_4_;
|
|
assign _zz_5_ = _zz_6_;
|
|
assign decode_CSR_READ_OPCODE = _zz_22_;
|
|
assign decode_ALU_CTRL = _zz_7_;
|
|
assign _zz_8_ = _zz_9_;
|
|
assign decode_SRC2_CTRL = _zz_10_;
|
|
assign _zz_11_ = _zz_12_;
|
|
assign execute_REGFILE_WRITE_VALID = decode_to_execute_REGFILE_WRITE_VALID;
|
|
assign decode_BRANCH_CTRL = _zz_13_;
|
|
assign _zz_14_ = _zz_15_;
|
|
assign decode_CSR_WRITE_OPCODE = _zz_23_;
|
|
assign decode_ALU_BITWISE_CTRL = _zz_16_;
|
|
assign _zz_17_ = _zz_18_;
|
|
assign execute_FORMAL_PC_NEXT = decode_to_execute_FORMAL_PC_NEXT;
|
|
assign decode_FORMAL_PC_NEXT = _zz_78_;
|
|
assign decode_SRC2_FORCE_ZERO = _zz_36_;
|
|
assign decode_SRC1_CTRL = _zz_19_;
|
|
assign _zz_20_ = _zz_21_;
|
|
assign decode_IS_SFENCE_VMA = _zz_52_;
|
|
assign decode_MEMORY_ATOMIC = _zz_46_;
|
|
assign execute_CSR_READ_OPCODE = decode_to_execute_CSR_READ_OPCODE;
|
|
assign execute_CSR_WRITE_OPCODE = decode_to_execute_CSR_WRITE_OPCODE;
|
|
assign execute_IS_CSR = decode_to_execute_IS_CSR;
|
|
assign execute_ENV_CTRL = _zz_24_;
|
|
assign execute_IS_SFENCE_VMA = decode_to_execute_IS_SFENCE_VMA;
|
|
assign execute_BRANCH_CALC = _zz_25_;
|
|
assign execute_BRANCH_DO = _zz_27_;
|
|
assign execute_RS1 = _zz_42_;
|
|
assign execute_BRANCH_CTRL = _zz_26_;
|
|
assign execute_SHIFT_CTRL = _zz_28_;
|
|
assign execute_SRC_LESS_UNSIGNED = decode_to_execute_SRC_LESS_UNSIGNED;
|
|
assign execute_SRC2_FORCE_ZERO = decode_to_execute_SRC2_FORCE_ZERO;
|
|
assign execute_SRC_USE_SUB_LESS = decode_to_execute_SRC_USE_SUB_LESS;
|
|
assign execute_SRC2_CTRL = _zz_32_;
|
|
assign execute_SRC1_CTRL = _zz_34_;
|
|
assign decode_SRC_USE_SUB_LESS = _zz_47_;
|
|
assign decode_SRC_ADD_ZERO = _zz_57_;
|
|
assign execute_SRC_ADD_SUB = _zz_31_;
|
|
assign execute_SRC_LESS = _zz_29_;
|
|
assign execute_ALU_CTRL = _zz_37_;
|
|
assign execute_SRC2 = _zz_33_;
|
|
assign execute_SRC1 = _zz_35_;
|
|
assign execute_ALU_BITWISE_CTRL = _zz_39_;
|
|
always @ (*) begin
|
|
_zz_40_ = 1'b0;
|
|
if(lastStageRegFileWrite_valid)begin
|
|
_zz_40_ = 1'b1;
|
|
end
|
|
end
|
|
|
|
always @ (*) begin
|
|
decode_REGFILE_WRITE_VALID = _zz_44_;
|
|
if((decode_INSTRUCTION[11 : 7] == (5'b00000)))begin
|
|
decode_REGFILE_WRITE_VALID = 1'b0;
|
|
end
|
|
end
|
|
|
|
assign decode_LEGAL_INSTRUCTION = _zz_60_;
|
|
assign decode_INSTRUCTION_READY = 1'b1;
|
|
always @ (*) begin
|
|
_zz_61_ = execute_REGFILE_WRITE_DATA;
|
|
if((execute_arbitration_isValid && execute_MEMORY_ENABLE))begin
|
|
_zz_61_ = execute_DBusSimplePlugin_rspFormated;
|
|
if((execute_MEMORY_ATOMIC && execute_MEMORY_STORE))begin
|
|
_zz_61_ = {31'd0, _zz_205_};
|
|
end
|
|
end
|
|
if(_zz_167_)begin
|
|
_zz_61_ = _zz_126_;
|
|
end
|
|
if(_zz_168_)begin
|
|
_zz_61_ = execute_CsrPlugin_readData;
|
|
end
|
|
end
|
|
|
|
assign execute_MEMORY_ADDRESS_LOW = _zz_72_;
|
|
assign execute_MEMORY_READ_DATA = _zz_62_;
|
|
assign execute_REGFILE_WRITE_DATA = _zz_38_;
|
|
assign execute_ATOMIC_HIT = _zz_63_;
|
|
assign execute_MEMORY_ATOMIC = decode_to_execute_MEMORY_ATOMIC;
|
|
assign execute_MMU_FAULT = _zz_71_;
|
|
assign execute_MMU_RSP_physicalAddress = _zz_64_;
|
|
assign execute_MMU_RSP_isIoAccess = _zz_65_;
|
|
assign execute_MMU_RSP_allowRead = _zz_66_;
|
|
assign execute_MMU_RSP_allowWrite = _zz_67_;
|
|
assign execute_MMU_RSP_allowExecute = _zz_68_;
|
|
assign execute_MMU_RSP_exception = _zz_69_;
|
|
assign execute_MMU_RSP_refilling = _zz_70_;
|
|
assign execute_SRC_ADD = _zz_30_;
|
|
assign execute_RS2 = _zz_41_;
|
|
assign execute_MEMORY_STORE = decode_to_execute_MEMORY_STORE;
|
|
assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE;
|
|
assign execute_ALIGNEMENT_FAULT = _zz_73_;
|
|
assign decode_MEMORY_ENABLE = _zz_56_;
|
|
assign decode_FLUSH_ALL = _zz_50_;
|
|
always @ (*) begin
|
|
IBusCachedPlugin_rsp_issueDetected = _zz_74_;
|
|
if(_zz_169_)begin
|
|
IBusCachedPlugin_rsp_issueDetected = 1'b1;
|
|
end
|
|
end
|
|
|
|
always @ (*) begin
|
|
_zz_74_ = _zz_75_;
|
|
if(_zz_170_)begin
|
|
_zz_74_ = 1'b1;
|
|
end
|
|
end
|
|
|
|
always @ (*) begin
|
|
_zz_75_ = _zz_76_;
|
|
if(_zz_171_)begin
|
|
_zz_75_ = 1'b1;
|
|
end
|
|
end
|
|
|
|
always @ (*) begin
|
|
_zz_76_ = 1'b0;
|
|
if(_zz_172_)begin
|
|
_zz_76_ = 1'b1;
|
|
end
|
|
end
|
|
|
|
always @ (*) begin
|
|
_zz_77_ = decode_FORMAL_PC_NEXT;
|
|
if(IBusCachedPlugin_redoBranch_valid)begin
|
|
_zz_77_ = IBusCachedPlugin_redoBranch_payload;
|
|
end
|
|
end
|
|
|
|
assign decode_PC = _zz_80_;
|
|
assign decode_INSTRUCTION = _zz_79_;
|
|
assign execute_PC = decode_to_execute_PC;
|
|
assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION;
|
|
always @ (*) begin
|
|
decode_arbitration_haltItself = 1'b0;
|
|
if(((DBusSimplePlugin_mmuBus_busy && decode_arbitration_isValid) && decode_MEMORY_ENABLE))begin
|
|
decode_arbitration_haltItself = 1'b1;
|
|
end
|
|
case(_zz_104_)
|
|
2'b00 : begin
|
|
if(MmuPlugin_dBusAccess_cmd_valid)begin
|
|
decode_arbitration_haltItself = 1'b1;
|
|
end
|
|
end
|
|
2'b01 : begin
|
|
decode_arbitration_haltItself = 1'b1;
|
|
end
|
|
2'b10 : begin
|
|
decode_arbitration_haltItself = 1'b1;
|
|
end
|
|
default : begin
|
|
end
|
|
endcase
|
|
end
|
|
|
|
always @ (*) begin
|
|
decode_arbitration_haltByOther = 1'b0;
|
|
if((CsrPlugin_interrupt_valid && CsrPlugin_allowInterrupts))begin
|
|
decode_arbitration_haltByOther = decode_arbitration_isValid;
|
|
end
|
|
if(((execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)) != (1'b0)))begin
|
|
decode_arbitration_haltByOther = 1'b1;
|
|
end
|
|
end
|
|
|
|
always @ (*) begin
|
|
decode_arbitration_removeIt = 1'b0;
|
|
if(_zz_173_)begin
|
|
decode_arbitration_removeIt = 1'b1;
|
|
end
|
|
if(decode_arbitration_isFlushed)begin
|
|
decode_arbitration_removeIt = 1'b1;
|
|
end
|
|
end
|
|
|
|
assign decode_arbitration_flushIt = 1'b0;
|
|
always @ (*) begin
|
|
decode_arbitration_flushNext = 1'b0;
|
|
if(IBusCachedPlugin_redoBranch_valid)begin
|
|
decode_arbitration_flushNext = 1'b1;
|
|
end
|
|
if(_zz_173_)begin
|
|
decode_arbitration_flushNext = 1'b1;
|
|
end
|
|
end
|
|
|
|
always @ (*) begin
|
|
execute_arbitration_haltItself = 1'b0;
|
|
if(((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! dBus_cmd_ready)) && (! execute_DBusSimplePlugin_skipCmd)) && (! _zz_97_)))begin
|
|
execute_arbitration_haltItself = 1'b1;
|
|
end
|
|
if((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! execute_MEMORY_STORE)) && ((! dBus_rsp_ready) || (! _zz_97_))))begin
|
|
execute_arbitration_haltItself = 1'b1;
|
|
end
|
|
if(_zz_167_)begin
|
|
if(_zz_174_)begin
|
|
if(! execute_LightShifterPlugin_done) begin
|
|
execute_arbitration_haltItself = 1'b1;
|
|
end
|
|
end
|
|
end
|
|
if(_zz_168_)begin
|
|
if(execute_CsrPlugin_blockedBySideEffects)begin
|
|
execute_arbitration_haltItself = 1'b1;
|
|
end
|
|
end
|
|
end
|
|
|
|
assign execute_arbitration_haltByOther = 1'b0;
|
|
always @ (*) begin
|
|
execute_arbitration_removeIt = 1'b0;
|
|
if(_zz_175_)begin
|
|
execute_arbitration_removeIt = 1'b1;
|
|
end
|
|
if(execute_arbitration_isFlushed)begin
|
|
execute_arbitration_removeIt = 1'b1;
|
|
end
|
|
end
|
|
|
|
always @ (*) begin
|
|
execute_arbitration_flushIt = 1'b0;
|
|
if(DBusSimplePlugin_redoBranch_valid)begin
|
|
execute_arbitration_flushIt = 1'b1;
|
|
end
|
|
end
|
|
|
|
always @ (*) begin
|
|
execute_arbitration_flushNext = 1'b0;
|
|
if(DBusSimplePlugin_redoBranch_valid)begin
|
|
execute_arbitration_flushNext = 1'b1;
|
|
end
|
|
if(BranchPlugin_jumpInterface_valid)begin
|
|
execute_arbitration_flushNext = 1'b1;
|
|
end
|
|
if(_zz_175_)begin
|
|
execute_arbitration_flushNext = 1'b1;
|
|
end
|
|
if(_zz_176_)begin
|
|
execute_arbitration_flushNext = 1'b1;
|
|
end
|
|
if(_zz_177_)begin
|
|
execute_arbitration_flushNext = 1'b1;
|
|
end
|
|
end
|
|
|
|
assign lastStageInstruction = execute_INSTRUCTION;
|
|
assign lastStagePc = execute_PC;
|
|
assign lastStageIsValid = execute_arbitration_isValid;
|
|
assign lastStageIsFiring = execute_arbitration_isFiring;
|
|
always @ (*) begin
|
|
IBusCachedPlugin_fetcherHalt = 1'b0;
|
|
if(({CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode} != (2'b00)))begin
|
|
IBusCachedPlugin_fetcherHalt = 1'b1;
|
|
end
|
|
if(_zz_176_)begin
|
|
IBusCachedPlugin_fetcherHalt = 1'b1;
|
|
end
|
|
if(_zz_177_)begin
|
|
IBusCachedPlugin_fetcherHalt = 1'b1;
|
|
end
|
|
end
|
|
|
|
always @ (*) begin
|
|
IBusCachedPlugin_fetcherflushIt = 1'b0;
|
|
if(({execute_arbitration_flushNext,decode_arbitration_flushNext} != (2'b00)))begin
|
|
IBusCachedPlugin_fetcherflushIt = 1'b1;
|
|
end
|
|
end
|
|
|
|
always @ (*) begin
|
|
IBusCachedPlugin_incomingInstruction = 1'b0;
|
|
if(IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid)begin
|
|
IBusCachedPlugin_incomingInstruction = 1'b1;
|
|
end
|
|
if(IBusCachedPlugin_injector_decodeInput_valid)begin
|
|
IBusCachedPlugin_incomingInstruction = 1'b1;
|
|
end
|
|
end
|
|
|
|
always @ (*) begin
|
|
CsrPlugin_jumpInterface_valid = 1'b0;
|
|
if(_zz_176_)begin
|
|
CsrPlugin_jumpInterface_valid = 1'b1;
|
|
end
|
|
if(_zz_177_)begin
|
|
CsrPlugin_jumpInterface_valid = 1'b1;
|
|
end
|
|
end
|
|
|
|
always @ (*) begin
|
|
CsrPlugin_jumpInterface_payload = (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx);
|
|
if(_zz_176_)begin
|
|
CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,(2'b00)};
|
|
end
|
|
if(_zz_177_)begin
|
|
case(_zz_178_)
|
|
2'b11 : begin
|
|
CsrPlugin_jumpInterface_payload = CsrPlugin_mepc;
|
|
end
|
|
default : begin
|
|
end
|
|
endcase
|
|
end
|
|
end
|
|
|
|
assign CsrPlugin_forceMachineWire = 1'b0;
|
|
assign CsrPlugin_allowInterrupts = 1'b1;
|
|
assign CsrPlugin_allowException = 1'b1;
|
|
assign IBusCachedPlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,{DBusSimplePlugin_redoBranch_valid,IBusCachedPlugin_redoBranch_valid}}} != (4'b0000));
|
|
assign _zz_81_ = {IBusCachedPlugin_redoBranch_valid,{CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,DBusSimplePlugin_redoBranch_valid}}};
|
|
assign _zz_82_ = (_zz_81_ & (~ _zz_201_));
|
|
assign _zz_83_ = _zz_82_[3];
|
|
assign _zz_84_ = (_zz_82_[1] || _zz_83_);
|
|
assign _zz_85_ = (_zz_82_[2] || _zz_83_);
|
|
assign IBusCachedPlugin_jump_pcLoad_payload = _zz_164_;
|
|
always @ (*) begin
|
|
IBusCachedPlugin_fetchPc_corrected = 1'b0;
|
|
if(IBusCachedPlugin_jump_pcLoad_valid)begin
|
|
IBusCachedPlugin_fetchPc_corrected = 1'b1;
|
|
end
|
|
end
|
|
|
|
always @ (*) begin
|
|
IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b0;
|
|
if(IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready)begin
|
|
IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b1;
|
|
end
|
|
end
|
|
|
|
always @ (*) begin
|
|
IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_203_);
|
|
if(IBusCachedPlugin_jump_pcLoad_valid)begin
|
|
IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_jump_pcLoad_payload;
|
|
end
|
|
IBusCachedPlugin_fetchPc_pc[0] = 1'b0;
|
|
IBusCachedPlugin_fetchPc_pc[1] = 1'b0;
|
|
end
|
|
|
|
assign IBusCachedPlugin_fetchPc_output_valid = ((! IBusCachedPlugin_fetcherHalt) && IBusCachedPlugin_fetchPc_booted);
|
|
assign IBusCachedPlugin_fetchPc_output_payload = IBusCachedPlugin_fetchPc_pc;
|
|
assign IBusCachedPlugin_iBusRsp_stages_0_input_valid = IBusCachedPlugin_fetchPc_output_valid;
|
|
assign IBusCachedPlugin_fetchPc_output_ready = IBusCachedPlugin_iBusRsp_stages_0_input_ready;
|
|
assign IBusCachedPlugin_iBusRsp_stages_0_input_payload = IBusCachedPlugin_fetchPc_output_payload;
|
|
assign IBusCachedPlugin_iBusRsp_stages_0_inputSample = 1'b1;
|
|
always @ (*) begin
|
|
IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b0;
|
|
if(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt)begin
|
|
IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b1;
|
|
end
|
|
end
|
|
|
|
assign _zz_86_ = (! IBusCachedPlugin_iBusRsp_stages_0_halt);
|
|
assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_86_);
|
|
assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_86_);
|
|
assign IBusCachedPlugin_iBusRsp_stages_0_output_payload = IBusCachedPlugin_iBusRsp_stages_0_input_payload;
|
|
always @ (*) begin
|
|
IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt = 1'b0;
|
|
if(IBusCachedPlugin_cache_io_cpu_fetch_haltIt)begin
|
|
IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt = 1'b1;
|
|
end
|
|
if((IBusCachedPlugin_rsp_issueDetected || IBusCachedPlugin_rsp_iBusRspOutputHalt))begin
|
|
IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt = 1'b1;
|
|
end
|
|
end
|
|
|
|
assign _zz_87_ = (! IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt);
|
|
assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready = (IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_ready && _zz_87_);
|
|
assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_valid = (IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid && _zz_87_);
|
|
assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_payload = IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload;
|
|
assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_88_;
|
|
assign _zz_88_ = ((1'b0 && (! _zz_89_)) || IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready);
|
|
assign _zz_89_ = _zz_90_;
|
|
assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid = _zz_89_;
|
|
assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload = IBusCachedPlugin_fetchPc_pcReg;
|
|
always @ (*) begin
|
|
IBusCachedPlugin_iBusRsp_readyForError = 1'b1;
|
|
if(IBusCachedPlugin_injector_decodeInput_valid)begin
|
|
IBusCachedPlugin_iBusRsp_readyForError = 1'b0;
|
|
end
|
|
if((! IBusCachedPlugin_pcValids_0))begin
|
|
IBusCachedPlugin_iBusRsp_readyForError = 1'b0;
|
|
end
|
|
end
|
|
|
|
assign IBusCachedPlugin_iBusRsp_inputBeforeStage_ready = ((1'b0 && (! IBusCachedPlugin_injector_decodeInput_valid)) || IBusCachedPlugin_injector_decodeInput_ready);
|
|
assign IBusCachedPlugin_injector_decodeInput_valid = _zz_91_;
|
|
assign IBusCachedPlugin_injector_decodeInput_payload_pc = _zz_92_;
|
|
assign IBusCachedPlugin_injector_decodeInput_payload_rsp_error = _zz_93_;
|
|
assign IBusCachedPlugin_injector_decodeInput_payload_rsp_inst = _zz_94_;
|
|
assign IBusCachedPlugin_injector_decodeInput_payload_isRvc = _zz_95_;
|
|
assign IBusCachedPlugin_pcValids_0 = IBusCachedPlugin_injector_nextPcCalc_valids_1;
|
|
assign IBusCachedPlugin_pcValids_1 = IBusCachedPlugin_injector_nextPcCalc_valids_2;
|
|
assign IBusCachedPlugin_injector_decodeInput_ready = (! decode_arbitration_isStuck);
|
|
assign decode_arbitration_isValid = (IBusCachedPlugin_injector_decodeInput_valid && (! IBusCachedPlugin_injector_decodeRemoved));
|
|
assign _zz_80_ = IBusCachedPlugin_injector_decodeInput_payload_pc;
|
|
assign _zz_79_ = IBusCachedPlugin_injector_decodeInput_payload_rsp_inst;
|
|
assign _zz_78_ = (decode_PC + (32'b00000000000000000000000000000100));
|
|
assign iBus_cmd_valid = IBusCachedPlugin_cache_io_mem_cmd_valid;
|
|
always @ (*) begin
|
|
iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address;
|
|
iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address;
|
|
end
|
|
|
|
assign iBus_cmd_payload_size = IBusCachedPlugin_cache_io_mem_cmd_payload_size;
|
|
assign IBusCachedPlugin_s0_tightlyCoupledHit = 1'b0;
|
|
assign _zz_153_ = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit));
|
|
assign _zz_156_ = (32'b00000000000000000000000000000000);
|
|
assign _zz_154_ = (IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit));
|
|
assign _zz_155_ = (! IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready);
|
|
assign _zz_157_ = (CsrPlugin_privilege == (2'b00));
|
|
assign IBusCachedPlugin_rsp_iBusRspOutputHalt = 1'b0;
|
|
always @ (*) begin
|
|
IBusCachedPlugin_rsp_redoFetch = 1'b0;
|
|
if(_zz_172_)begin
|
|
IBusCachedPlugin_rsp_redoFetch = 1'b1;
|
|
end
|
|
if(_zz_170_)begin
|
|
IBusCachedPlugin_rsp_redoFetch = 1'b1;
|
|
end
|
|
if(_zz_179_)begin
|
|
IBusCachedPlugin_rsp_redoFetch = 1'b0;
|
|
end
|
|
end
|
|
|
|
always @ (*) begin
|
|
_zz_161_ = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_fetch_mmuRefilling));
|
|
if(_zz_170_)begin
|
|
_zz_161_ = 1'b1;
|
|
end
|
|
if(_zz_179_)begin
|
|
_zz_161_ = 1'b0;
|
|
end
|
|
end
|
|
|
|
always @ (*) begin
|
|
IBusCachedPlugin_decodeExceptionPort_valid = 1'b0;
|
|
if(_zz_171_)begin
|
|
IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError;
|
|
end
|
|
if(_zz_169_)begin
|
|
IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError;
|
|
end
|
|
end
|
|
|
|
always @ (*) begin
|
|
IBusCachedPlugin_decodeExceptionPort_payload_code = (4'bxxxx);
|
|
if(_zz_171_)begin
|
|
IBusCachedPlugin_decodeExceptionPort_payload_code = (4'b1100);
|
|
end
|
|
if(_zz_169_)begin
|
|
IBusCachedPlugin_decodeExceptionPort_payload_code = (4'b0001);
|
|
end
|
|
end
|
|
|
|
assign IBusCachedPlugin_decodeExceptionPort_payload_badAddr = {IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload[31 : 2],(2'b00)};
|
|
assign IBusCachedPlugin_redoBranch_valid = IBusCachedPlugin_rsp_redoFetch;
|
|
assign IBusCachedPlugin_redoBranch_payload = IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload;
|
|
assign IBusCachedPlugin_iBusRsp_inputBeforeStage_valid = IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_valid;
|
|
assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_ready = IBusCachedPlugin_iBusRsp_inputBeforeStage_ready;
|
|
assign IBusCachedPlugin_iBusRsp_inputBeforeStage_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_fetch_data;
|
|
assign IBusCachedPlugin_iBusRsp_inputBeforeStage_payload_pc = IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_payload;
|
|
assign IBusCachedPlugin_mmuBus_cmd_isValid = IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_isValid;
|
|
assign IBusCachedPlugin_mmuBus_cmd_virtualAddress = IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_virtualAddress;
|
|
assign IBusCachedPlugin_mmuBus_cmd_bypassTranslation = IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_bypassTranslation;
|
|
assign IBusCachedPlugin_mmuBus_end = IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_end;
|
|
assign _zz_152_ = (decode_arbitration_isValid && decode_FLUSH_ALL);
|
|
assign _zz_73_ = (((dBus_cmd_payload_size == (2'b10)) && (dBus_cmd_payload_address[1 : 0] != (2'b00))) || ((dBus_cmd_payload_size == (2'b01)) && (dBus_cmd_payload_address[0 : 0] != (1'b0))));
|
|
always @ (*) begin
|
|
execute_DBusSimplePlugin_skipCmd = 1'b0;
|
|
if(execute_ALIGNEMENT_FAULT)begin
|
|
execute_DBusSimplePlugin_skipCmd = 1'b1;
|
|
end
|
|
if((execute_MMU_FAULT || execute_MMU_RSP_refilling))begin
|
|
execute_DBusSimplePlugin_skipCmd = 1'b1;
|
|
end
|
|
if(((execute_MEMORY_STORE && execute_MEMORY_ATOMIC) && (! execute_ATOMIC_HIT)))begin
|
|
execute_DBusSimplePlugin_skipCmd = 1'b1;
|
|
end
|
|
end
|
|
|
|
always @ (*) begin
|
|
dBus_cmd_valid = (((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! execute_arbitration_isStuckByOthers)) && (! execute_arbitration_isFlushed)) && (! execute_DBusSimplePlugin_skipCmd)) && (! _zz_97_));
|
|
case(_zz_104_)
|
|
2'b00 : begin
|
|
end
|
|
2'b01 : begin
|
|
dBus_cmd_valid = 1'b1;
|
|
end
|
|
2'b10 : begin
|
|
end
|
|
default : begin
|
|
end
|
|
endcase
|
|
end
|
|
|
|
always @ (*) begin
|
|
dBus_cmd_payload_wr = execute_MEMORY_STORE;
|
|
case(_zz_104_)
|
|
2'b00 : begin
|
|
end
|
|
2'b01 : begin
|
|
dBus_cmd_payload_wr = MmuPlugin_dBusAccess_cmd_payload_write;
|
|
end
|
|
2'b10 : begin
|
|
end
|
|
default : begin
|
|
end
|
|
endcase
|
|
end
|
|
|
|
always @ (*) begin
|
|
dBus_cmd_payload_size = execute_INSTRUCTION[13 : 12];
|
|
case(_zz_104_)
|
|
2'b00 : begin
|
|
end
|
|
2'b01 : begin
|
|
dBus_cmd_payload_size = MmuPlugin_dBusAccess_cmd_payload_size;
|
|
end
|
|
2'b10 : begin
|
|
end
|
|
default : begin
|
|
end
|
|
endcase
|
|
end
|
|
|
|
always @ (*) begin
|
|
case(dBus_cmd_payload_size)
|
|
2'b00 : begin
|
|
_zz_98_ = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]};
|
|
end
|
|
2'b01 : begin
|
|
_zz_98_ = {execute_RS2[15 : 0],execute_RS2[15 : 0]};
|
|
end
|
|
default : begin
|
|
_zz_98_ = execute_RS2[31 : 0];
|
|
end
|
|
endcase
|
|
end
|
|
|
|
always @ (*) begin
|
|
dBus_cmd_payload_data = _zz_98_;
|
|
case(_zz_104_)
|
|
2'b00 : begin
|
|
end
|
|
2'b01 : begin
|
|
dBus_cmd_payload_data = MmuPlugin_dBusAccess_cmd_payload_data;
|
|
end
|
|
2'b10 : begin
|
|
end
|
|
default : begin
|
|
end
|
|
endcase
|
|
end
|
|
|
|
assign _zz_72_ = dBus_cmd_payload_address[1 : 0];
|
|
always @ (*) begin
|
|
case(dBus_cmd_payload_size)
|
|
2'b00 : begin
|
|
_zz_99_ = (4'b0001);
|
|
end
|
|
2'b01 : begin
|
|
_zz_99_ = (4'b0011);
|
|
end
|
|
default : begin
|
|
_zz_99_ = (4'b1111);
|
|
end
|
|
endcase
|
|
end
|
|
|
|
assign execute_DBusSimplePlugin_formalMask = (_zz_99_ <<< dBus_cmd_payload_address[1 : 0]);
|
|
assign DBusSimplePlugin_mmuBus_cmd_isValid = (execute_arbitration_isValid && execute_MEMORY_ENABLE);
|
|
assign DBusSimplePlugin_mmuBus_cmd_virtualAddress = execute_SRC_ADD;
|
|
assign DBusSimplePlugin_mmuBus_cmd_bypassTranslation = 1'b0;
|
|
assign DBusSimplePlugin_mmuBus_end = ((! execute_arbitration_isStuck) || execute_arbitration_removeIt);
|
|
always @ (*) begin
|
|
dBus_cmd_payload_address = DBusSimplePlugin_mmuBus_rsp_physicalAddress;
|
|
case(_zz_104_)
|
|
2'b00 : begin
|
|
end
|
|
2'b01 : begin
|
|
dBus_cmd_payload_address = MmuPlugin_dBusAccess_cmd_payload_address;
|
|
end
|
|
2'b10 : begin
|
|
end
|
|
default : begin
|
|
end
|
|
endcase
|
|
end
|
|
|
|
assign _zz_71_ = ((execute_MMU_RSP_exception || ((! execute_MMU_RSP_allowWrite) && execute_MEMORY_STORE)) || ((! execute_MMU_RSP_allowRead) && (! execute_MEMORY_STORE)));
|
|
assign _zz_64_ = DBusSimplePlugin_mmuBus_rsp_physicalAddress;
|
|
assign _zz_65_ = DBusSimplePlugin_mmuBus_rsp_isIoAccess;
|
|
assign _zz_66_ = DBusSimplePlugin_mmuBus_rsp_allowRead;
|
|
assign _zz_67_ = DBusSimplePlugin_mmuBus_rsp_allowWrite;
|
|
assign _zz_68_ = DBusSimplePlugin_mmuBus_rsp_allowExecute;
|
|
assign _zz_69_ = DBusSimplePlugin_mmuBus_rsp_exception;
|
|
assign _zz_70_ = DBusSimplePlugin_mmuBus_rsp_refilling;
|
|
assign _zz_63_ = execute_DBusSimplePlugin_atomic_reserved;
|
|
assign _zz_62_ = dBus_rsp_data;
|
|
always @ (*) begin
|
|
DBusSimplePlugin_memoryExceptionPort_valid = 1'b0;
|
|
if(execute_ALIGNEMENT_FAULT)begin
|
|
DBusSimplePlugin_memoryExceptionPort_valid = 1'b1;
|
|
end
|
|
if(execute_MMU_RSP_refilling)begin
|
|
DBusSimplePlugin_memoryExceptionPort_valid = 1'b0;
|
|
end else begin
|
|
if(execute_MMU_FAULT)begin
|
|
DBusSimplePlugin_memoryExceptionPort_valid = 1'b1;
|
|
end
|
|
end
|
|
if(_zz_180_)begin
|
|
DBusSimplePlugin_memoryExceptionPort_valid = 1'b0;
|
|
end
|
|
end
|
|
|
|
always @ (*) begin
|
|
DBusSimplePlugin_memoryExceptionPort_payload_code = (4'bxxxx);
|
|
if(execute_ALIGNEMENT_FAULT)begin
|
|
DBusSimplePlugin_memoryExceptionPort_payload_code = {1'd0, _zz_204_};
|
|
end
|
|
if(! execute_MMU_RSP_refilling) begin
|
|
if(execute_MMU_FAULT)begin
|
|
DBusSimplePlugin_memoryExceptionPort_payload_code = (execute_MEMORY_STORE ? (4'b1111) : (4'b1101));
|
|
end
|
|
end
|
|
end
|
|
|
|
assign DBusSimplePlugin_memoryExceptionPort_payload_badAddr = execute_REGFILE_WRITE_DATA;
|
|
always @ (*) begin
|
|
DBusSimplePlugin_redoBranch_valid = 1'b0;
|
|
if(execute_MMU_RSP_refilling)begin
|
|
DBusSimplePlugin_redoBranch_valid = 1'b1;
|
|
end
|
|
if(_zz_180_)begin
|
|
DBusSimplePlugin_redoBranch_valid = 1'b0;
|
|
end
|
|
end
|
|
|
|
assign DBusSimplePlugin_redoBranch_payload = execute_PC;
|
|
always @ (*) begin
|
|
execute_DBusSimplePlugin_rspShifted = execute_MEMORY_READ_DATA;
|
|
case(execute_MEMORY_ADDRESS_LOW)
|
|
2'b01 : begin
|
|
execute_DBusSimplePlugin_rspShifted[7 : 0] = execute_MEMORY_READ_DATA[15 : 8];
|
|
end
|
|
2'b10 : begin
|
|
execute_DBusSimplePlugin_rspShifted[15 : 0] = execute_MEMORY_READ_DATA[31 : 16];
|
|
end
|
|
2'b11 : begin
|
|
execute_DBusSimplePlugin_rspShifted[7 : 0] = execute_MEMORY_READ_DATA[31 : 24];
|
|
end
|
|
default : begin
|
|
end
|
|
endcase
|
|
end
|
|
|
|
assign _zz_100_ = (execute_DBusSimplePlugin_rspShifted[7] && (! execute_INSTRUCTION[14]));
|
|
always @ (*) begin
|
|
_zz_101_[31] = _zz_100_;
|
|
_zz_101_[30] = _zz_100_;
|
|
_zz_101_[29] = _zz_100_;
|
|
_zz_101_[28] = _zz_100_;
|
|
_zz_101_[27] = _zz_100_;
|
|
_zz_101_[26] = _zz_100_;
|
|
_zz_101_[25] = _zz_100_;
|
|
_zz_101_[24] = _zz_100_;
|
|
_zz_101_[23] = _zz_100_;
|
|
_zz_101_[22] = _zz_100_;
|
|
_zz_101_[21] = _zz_100_;
|
|
_zz_101_[20] = _zz_100_;
|
|
_zz_101_[19] = _zz_100_;
|
|
_zz_101_[18] = _zz_100_;
|
|
_zz_101_[17] = _zz_100_;
|
|
_zz_101_[16] = _zz_100_;
|
|
_zz_101_[15] = _zz_100_;
|
|
_zz_101_[14] = _zz_100_;
|
|
_zz_101_[13] = _zz_100_;
|
|
_zz_101_[12] = _zz_100_;
|
|
_zz_101_[11] = _zz_100_;
|
|
_zz_101_[10] = _zz_100_;
|
|
_zz_101_[9] = _zz_100_;
|
|
_zz_101_[8] = _zz_100_;
|
|
_zz_101_[7 : 0] = execute_DBusSimplePlugin_rspShifted[7 : 0];
|
|
end
|
|
|
|
assign _zz_102_ = (execute_DBusSimplePlugin_rspShifted[15] && (! execute_INSTRUCTION[14]));
|
|
always @ (*) begin
|
|
_zz_103_[31] = _zz_102_;
|
|
_zz_103_[30] = _zz_102_;
|
|
_zz_103_[29] = _zz_102_;
|
|
_zz_103_[28] = _zz_102_;
|
|
_zz_103_[27] = _zz_102_;
|
|
_zz_103_[26] = _zz_102_;
|
|
_zz_103_[25] = _zz_102_;
|
|
_zz_103_[24] = _zz_102_;
|
|
_zz_103_[23] = _zz_102_;
|
|
_zz_103_[22] = _zz_102_;
|
|
_zz_103_[21] = _zz_102_;
|
|
_zz_103_[20] = _zz_102_;
|
|
_zz_103_[19] = _zz_102_;
|
|
_zz_103_[18] = _zz_102_;
|
|
_zz_103_[17] = _zz_102_;
|
|
_zz_103_[16] = _zz_102_;
|
|
_zz_103_[15 : 0] = execute_DBusSimplePlugin_rspShifted[15 : 0];
|
|
end
|
|
|
|
always @ (*) begin
|
|
case(_zz_199_)
|
|
2'b00 : begin
|
|
execute_DBusSimplePlugin_rspFormated = _zz_101_;
|
|
end
|
|
2'b01 : begin
|
|
execute_DBusSimplePlugin_rspFormated = _zz_103_;
|
|
end
|
|
default : begin
|
|
execute_DBusSimplePlugin_rspFormated = execute_DBusSimplePlugin_rspShifted;
|
|
end
|
|
endcase
|
|
end
|
|
|
|
always @ (*) begin
|
|
MmuPlugin_dBusAccess_cmd_ready = 1'b0;
|
|
case(_zz_104_)
|
|
2'b00 : begin
|
|
end
|
|
2'b01 : begin
|
|
if(dBus_cmd_ready)begin
|
|
MmuPlugin_dBusAccess_cmd_ready = 1'b1;
|
|
end
|
|
end
|
|
2'b10 : begin
|
|
end
|
|
default : begin
|
|
end
|
|
endcase
|
|
end
|
|
|
|
always @ (*) begin
|
|
MmuPlugin_dBusAccess_rsp_valid = 1'b0;
|
|
case(_zz_104_)
|
|
2'b00 : begin
|
|
end
|
|
2'b01 : begin
|
|
end
|
|
2'b10 : begin
|
|
if(dBus_rsp_ready)begin
|
|
MmuPlugin_dBusAccess_rsp_valid = 1'b1;
|
|
end
|
|
end
|
|
default : begin
|
|
end
|
|
endcase
|
|
end
|
|
|
|
assign MmuPlugin_dBusAccess_rsp_payload_data = dBus_rsp_data;
|
|
assign MmuPlugin_dBusAccess_rsp_payload_error = dBus_rsp_error;
|
|
assign MmuPlugin_dBusAccess_rsp_payload_redo = 1'b0;
|
|
assign _zz_106_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001001000)) == (32'b00000000000000000000000001001000));
|
|
assign _zz_107_ = ((decode_INSTRUCTION & (32'b00000000000000000010000001010000)) == (32'b00000000000000000010000000000000));
|
|
assign _zz_108_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001010000)) == (32'b00000000000000000000000000010000));
|
|
assign _zz_109_ = ((decode_INSTRUCTION & (32'b00000000000000000100000001010000)) == (32'b00000000000000000100000001010000));
|
|
assign _zz_110_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000000100)) == (32'b00000000000000000000000000000100));
|
|
assign _zz_105_ = {({(_zz_260_ == _zz_261_),(_zz_262_ == _zz_263_)} != (2'b00)),{((_zz_264_ == _zz_265_) != (1'b0)),{({_zz_266_,_zz_267_} != (7'b0000000)),{(_zz_268_ != _zz_269_),{_zz_270_,{_zz_271_,_zz_272_}}}}}};
|
|
assign _zz_60_ = ({((decode_INSTRUCTION & (32'b00000000000000000000000001011111)) == (32'b00000000000000000000000000010111)),{((decode_INSTRUCTION & (32'b00000000000000000000000001111111)) == (32'b00000000000000000000000001101111)),{((decode_INSTRUCTION & (32'b00000000000000000001000001101111)) == (32'b00000000000000000000000000000011)),{((decode_INSTRUCTION & _zz_383_) == (32'b00000000000000000001000001110011)),{(_zz_384_ == _zz_385_),{_zz_386_,{_zz_387_,_zz_388_}}}}}}} != (23'b00000000000000000000000));
|
|
assign _zz_59_ = _zz_206_[0];
|
|
assign _zz_111_ = _zz_105_[2 : 1];
|
|
assign _zz_58_ = _zz_111_;
|
|
assign _zz_57_ = _zz_207_[0];
|
|
assign _zz_56_ = _zz_208_[0];
|
|
assign _zz_55_ = _zz_209_[0];
|
|
assign _zz_112_ = _zz_105_[9 : 8];
|
|
assign _zz_54_ = _zz_112_;
|
|
assign _zz_113_ = _zz_105_[12 : 11];
|
|
assign _zz_53_ = _zz_113_;
|
|
assign _zz_52_ = _zz_210_[0];
|
|
assign _zz_51_ = _zz_211_[0];
|
|
assign _zz_50_ = _zz_212_[0];
|
|
assign _zz_114_ = _zz_105_[18 : 17];
|
|
assign _zz_49_ = _zz_114_;
|
|
assign _zz_115_ = _zz_105_[20 : 19];
|
|
assign _zz_48_ = _zz_115_;
|
|
assign _zz_47_ = _zz_213_[0];
|
|
assign _zz_46_ = _zz_214_[0];
|
|
assign _zz_116_ = _zz_105_[25 : 24];
|
|
assign _zz_45_ = _zz_116_;
|
|
assign _zz_44_ = _zz_215_[0];
|
|
assign _zz_117_ = _zz_105_[28 : 27];
|
|
assign _zz_43_ = _zz_117_;
|
|
assign decodeExceptionPort_valid = ((decode_arbitration_isValid && decode_INSTRUCTION_READY) && (! decode_LEGAL_INSTRUCTION));
|
|
assign decodeExceptionPort_payload_code = (4'b0010);
|
|
assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION;
|
|
assign execute_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION[19 : 15];
|
|
assign execute_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION[24 : 20];
|
|
assign _zz_118_ = (! execute_arbitration_isStuck);
|
|
assign execute_RegFilePlugin_rs1Data = _zz_162_;
|
|
assign execute_RegFilePlugin_rs2Data = _zz_163_;
|
|
assign _zz_42_ = execute_RegFilePlugin_rs1Data;
|
|
assign _zz_41_ = execute_RegFilePlugin_rs2Data;
|
|
assign lastStageRegFileWrite_valid = (execute_REGFILE_WRITE_VALID && execute_arbitration_isFiring);
|
|
assign lastStageRegFileWrite_payload_address = execute_INSTRUCTION[11 : 7];
|
|
assign lastStageRegFileWrite_payload_data = _zz_61_;
|
|
always @ (*) begin
|
|
case(execute_ALU_BITWISE_CTRL)
|
|
`AluBitwiseCtrlEnum_defaultEncoding_AND_1 : begin
|
|
execute_IntAluPlugin_bitwise = (execute_SRC1 & execute_SRC2);
|
|
end
|
|
`AluBitwiseCtrlEnum_defaultEncoding_OR_1 : begin
|
|
execute_IntAluPlugin_bitwise = (execute_SRC1 | execute_SRC2);
|
|
end
|
|
default : begin
|
|
execute_IntAluPlugin_bitwise = (execute_SRC1 ^ execute_SRC2);
|
|
end
|
|
endcase
|
|
end
|
|
|
|
always @ (*) begin
|
|
case(execute_ALU_CTRL)
|
|
`AluCtrlEnum_defaultEncoding_BITWISE : begin
|
|
_zz_119_ = execute_IntAluPlugin_bitwise;
|
|
end
|
|
`AluCtrlEnum_defaultEncoding_SLT_SLTU : begin
|
|
_zz_119_ = {31'd0, _zz_216_};
|
|
end
|
|
default : begin
|
|
_zz_119_ = execute_SRC_ADD_SUB;
|
|
end
|
|
endcase
|
|
end
|
|
|
|
assign _zz_38_ = _zz_119_;
|
|
assign _zz_36_ = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS));
|
|
always @ (*) begin
|
|
case(execute_SRC1_CTRL)
|
|
`Src1CtrlEnum_defaultEncoding_RS : begin
|
|
_zz_120_ = execute_RS1;
|
|
end
|
|
`Src1CtrlEnum_defaultEncoding_PC_INCREMENT : begin
|
|
_zz_120_ = {29'd0, _zz_217_};
|
|
end
|
|
`Src1CtrlEnum_defaultEncoding_IMU : begin
|
|
_zz_120_ = {execute_INSTRUCTION[31 : 12],(12'b000000000000)};
|
|
end
|
|
default : begin
|
|
_zz_120_ = {27'd0, _zz_218_};
|
|
end
|
|
endcase
|
|
end
|
|
|
|
assign _zz_35_ = _zz_120_;
|
|
assign _zz_121_ = _zz_219_[11];
|
|
always @ (*) begin
|
|
_zz_122_[19] = _zz_121_;
|
|
_zz_122_[18] = _zz_121_;
|
|
_zz_122_[17] = _zz_121_;
|
|
_zz_122_[16] = _zz_121_;
|
|
_zz_122_[15] = _zz_121_;
|
|
_zz_122_[14] = _zz_121_;
|
|
_zz_122_[13] = _zz_121_;
|
|
_zz_122_[12] = _zz_121_;
|
|
_zz_122_[11] = _zz_121_;
|
|
_zz_122_[10] = _zz_121_;
|
|
_zz_122_[9] = _zz_121_;
|
|
_zz_122_[8] = _zz_121_;
|
|
_zz_122_[7] = _zz_121_;
|
|
_zz_122_[6] = _zz_121_;
|
|
_zz_122_[5] = _zz_121_;
|
|
_zz_122_[4] = _zz_121_;
|
|
_zz_122_[3] = _zz_121_;
|
|
_zz_122_[2] = _zz_121_;
|
|
_zz_122_[1] = _zz_121_;
|
|
_zz_122_[0] = _zz_121_;
|
|
end
|
|
|
|
assign _zz_123_ = _zz_220_[11];
|
|
always @ (*) begin
|
|
_zz_124_[19] = _zz_123_;
|
|
_zz_124_[18] = _zz_123_;
|
|
_zz_124_[17] = _zz_123_;
|
|
_zz_124_[16] = _zz_123_;
|
|
_zz_124_[15] = _zz_123_;
|
|
_zz_124_[14] = _zz_123_;
|
|
_zz_124_[13] = _zz_123_;
|
|
_zz_124_[12] = _zz_123_;
|
|
_zz_124_[11] = _zz_123_;
|
|
_zz_124_[10] = _zz_123_;
|
|
_zz_124_[9] = _zz_123_;
|
|
_zz_124_[8] = _zz_123_;
|
|
_zz_124_[7] = _zz_123_;
|
|
_zz_124_[6] = _zz_123_;
|
|
_zz_124_[5] = _zz_123_;
|
|
_zz_124_[4] = _zz_123_;
|
|
_zz_124_[3] = _zz_123_;
|
|
_zz_124_[2] = _zz_123_;
|
|
_zz_124_[1] = _zz_123_;
|
|
_zz_124_[0] = _zz_123_;
|
|
end
|
|
|
|
always @ (*) begin
|
|
case(execute_SRC2_CTRL)
|
|
`Src2CtrlEnum_defaultEncoding_RS : begin
|
|
_zz_125_ = execute_RS2;
|
|
end
|
|
`Src2CtrlEnum_defaultEncoding_IMI : begin
|
|
_zz_125_ = {_zz_122_,execute_INSTRUCTION[31 : 20]};
|
|
end
|
|
`Src2CtrlEnum_defaultEncoding_IMS : begin
|
|
_zz_125_ = {_zz_124_,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}};
|
|
end
|
|
default : begin
|
|
_zz_125_ = execute_PC;
|
|
end
|
|
endcase
|
|
end
|
|
|
|
assign _zz_33_ = _zz_125_;
|
|
always @ (*) begin
|
|
execute_SrcPlugin_addSub = _zz_221_;
|
|
if(execute_SRC2_FORCE_ZERO)begin
|
|
execute_SrcPlugin_addSub = execute_SRC1;
|
|
end
|
|
end
|
|
|
|
assign execute_SrcPlugin_less = ((execute_SRC1[31] == execute_SRC2[31]) ? execute_SrcPlugin_addSub[31] : (execute_SRC_LESS_UNSIGNED ? execute_SRC2[31] : execute_SRC1[31]));
|
|
assign _zz_31_ = execute_SrcPlugin_addSub;
|
|
assign _zz_30_ = execute_SrcPlugin_addSub;
|
|
assign _zz_29_ = execute_SrcPlugin_less;
|
|
assign execute_LightShifterPlugin_isShift = (execute_SHIFT_CTRL != `ShiftCtrlEnum_defaultEncoding_DISABLE_1);
|
|
assign execute_LightShifterPlugin_amplitude = (execute_LightShifterPlugin_isActive ? execute_LightShifterPlugin_amplitudeReg : execute_SRC2[4 : 0]);
|
|
assign execute_LightShifterPlugin_shiftInput = (execute_LightShifterPlugin_isActive ? execute_LightShifterPlugin_shiftReg : execute_SRC1);
|
|
assign execute_LightShifterPlugin_done = (execute_LightShifterPlugin_amplitude[4 : 1] == (4'b0000));
|
|
always @ (*) begin
|
|
case(execute_SHIFT_CTRL)
|
|
`ShiftCtrlEnum_defaultEncoding_SLL_1 : begin
|
|
_zz_126_ = (execute_LightShifterPlugin_shiftInput <<< 1);
|
|
end
|
|
default : begin
|
|
_zz_126_ = _zz_228_;
|
|
end
|
|
endcase
|
|
end
|
|
|
|
assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2);
|
|
assign _zz_127_ = execute_INSTRUCTION[14 : 12];
|
|
always @ (*) begin
|
|
if((_zz_127_ == (3'b000))) begin
|
|
_zz_128_ = execute_BranchPlugin_eq;
|
|
end else if((_zz_127_ == (3'b001))) begin
|
|
_zz_128_ = (! execute_BranchPlugin_eq);
|
|
end else if((((_zz_127_ & (3'b101)) == (3'b101)))) begin
|
|
_zz_128_ = (! execute_SRC_LESS);
|
|
end else begin
|
|
_zz_128_ = execute_SRC_LESS;
|
|
end
|
|
end
|
|
|
|
always @ (*) begin
|
|
case(execute_BRANCH_CTRL)
|
|
`BranchCtrlEnum_defaultEncoding_INC : begin
|
|
_zz_129_ = 1'b0;
|
|
end
|
|
`BranchCtrlEnum_defaultEncoding_JAL : begin
|
|
_zz_129_ = 1'b1;
|
|
end
|
|
`BranchCtrlEnum_defaultEncoding_JALR : begin
|
|
_zz_129_ = 1'b1;
|
|
end
|
|
default : begin
|
|
_zz_129_ = _zz_128_;
|
|
end
|
|
endcase
|
|
end
|
|
|
|
assign _zz_27_ = _zz_129_;
|
|
assign execute_BranchPlugin_branch_src1 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JALR) ? execute_RS1 : execute_PC);
|
|
assign _zz_130_ = _zz_230_[19];
|
|
always @ (*) begin
|
|
_zz_131_[10] = _zz_130_;
|
|
_zz_131_[9] = _zz_130_;
|
|
_zz_131_[8] = _zz_130_;
|
|
_zz_131_[7] = _zz_130_;
|
|
_zz_131_[6] = _zz_130_;
|
|
_zz_131_[5] = _zz_130_;
|
|
_zz_131_[4] = _zz_130_;
|
|
_zz_131_[3] = _zz_130_;
|
|
_zz_131_[2] = _zz_130_;
|
|
_zz_131_[1] = _zz_130_;
|
|
_zz_131_[0] = _zz_130_;
|
|
end
|
|
|
|
assign _zz_132_ = _zz_231_[11];
|
|
always @ (*) begin
|
|
_zz_133_[19] = _zz_132_;
|
|
_zz_133_[18] = _zz_132_;
|
|
_zz_133_[17] = _zz_132_;
|
|
_zz_133_[16] = _zz_132_;
|
|
_zz_133_[15] = _zz_132_;
|
|
_zz_133_[14] = _zz_132_;
|
|
_zz_133_[13] = _zz_132_;
|
|
_zz_133_[12] = _zz_132_;
|
|
_zz_133_[11] = _zz_132_;
|
|
_zz_133_[10] = _zz_132_;
|
|
_zz_133_[9] = _zz_132_;
|
|
_zz_133_[8] = _zz_132_;
|
|
_zz_133_[7] = _zz_132_;
|
|
_zz_133_[6] = _zz_132_;
|
|
_zz_133_[5] = _zz_132_;
|
|
_zz_133_[4] = _zz_132_;
|
|
_zz_133_[3] = _zz_132_;
|
|
_zz_133_[2] = _zz_132_;
|
|
_zz_133_[1] = _zz_132_;
|
|
_zz_133_[0] = _zz_132_;
|
|
end
|
|
|
|
assign _zz_134_ = _zz_232_[11];
|
|
always @ (*) begin
|
|
_zz_135_[18] = _zz_134_;
|
|
_zz_135_[17] = _zz_134_;
|
|
_zz_135_[16] = _zz_134_;
|
|
_zz_135_[15] = _zz_134_;
|
|
_zz_135_[14] = _zz_134_;
|
|
_zz_135_[13] = _zz_134_;
|
|
_zz_135_[12] = _zz_134_;
|
|
_zz_135_[11] = _zz_134_;
|
|
_zz_135_[10] = _zz_134_;
|
|
_zz_135_[9] = _zz_134_;
|
|
_zz_135_[8] = _zz_134_;
|
|
_zz_135_[7] = _zz_134_;
|
|
_zz_135_[6] = _zz_134_;
|
|
_zz_135_[5] = _zz_134_;
|
|
_zz_135_[4] = _zz_134_;
|
|
_zz_135_[3] = _zz_134_;
|
|
_zz_135_[2] = _zz_134_;
|
|
_zz_135_[1] = _zz_134_;
|
|
_zz_135_[0] = _zz_134_;
|
|
end
|
|
|
|
always @ (*) begin
|
|
case(execute_BRANCH_CTRL)
|
|
`BranchCtrlEnum_defaultEncoding_JAL : begin
|
|
_zz_136_ = {{_zz_131_,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0};
|
|
end
|
|
`BranchCtrlEnum_defaultEncoding_JALR : begin
|
|
_zz_136_ = {_zz_133_,execute_INSTRUCTION[31 : 20]};
|
|
end
|
|
default : begin
|
|
_zz_136_ = {{_zz_135_,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0};
|
|
end
|
|
endcase
|
|
end
|
|
|
|
assign execute_BranchPlugin_branch_src2 = _zz_136_;
|
|
assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2);
|
|
assign _zz_25_ = {execute_BranchPlugin_branchAdder[31 : 1],(1'b0)};
|
|
assign BranchPlugin_jumpInterface_valid = ((execute_arbitration_isValid && execute_BRANCH_DO) && (! 1'b0));
|
|
assign BranchPlugin_jumpInterface_payload = execute_BRANCH_CALC;
|
|
always @ (*) begin
|
|
BranchPlugin_branchExceptionPort_valid = ((execute_arbitration_isValid && execute_BRANCH_DO) && BranchPlugin_jumpInterface_payload[1]);
|
|
if(1'b0)begin
|
|
BranchPlugin_branchExceptionPort_valid = 1'b0;
|
|
end
|
|
end
|
|
|
|
assign BranchPlugin_branchExceptionPort_payload_code = (4'b0000);
|
|
assign BranchPlugin_branchExceptionPort_payload_badAddr = BranchPlugin_jumpInterface_payload;
|
|
assign MmuPlugin_ports_0_cacheHits_0 = ((MmuPlugin_ports_0_cache_0_valid && (MmuPlugin_ports_0_cache_0_virtualAddress_1 == DBusSimplePlugin_mmuBus_cmd_virtualAddress[31 : 22])) && (MmuPlugin_ports_0_cache_0_superPage || (MmuPlugin_ports_0_cache_0_virtualAddress_0 == DBusSimplePlugin_mmuBus_cmd_virtualAddress[21 : 12])));
|
|
assign MmuPlugin_ports_0_cacheHits_1 = ((MmuPlugin_ports_0_cache_1_valid && (MmuPlugin_ports_0_cache_1_virtualAddress_1 == DBusSimplePlugin_mmuBus_cmd_virtualAddress[31 : 22])) && (MmuPlugin_ports_0_cache_1_superPage || (MmuPlugin_ports_0_cache_1_virtualAddress_0 == DBusSimplePlugin_mmuBus_cmd_virtualAddress[21 : 12])));
|
|
assign MmuPlugin_ports_0_cacheHit = ({MmuPlugin_ports_0_cacheHits_1,MmuPlugin_ports_0_cacheHits_0} != (2'b00));
|
|
assign MmuPlugin_ports_0_cacheLine_valid = (MmuPlugin_ports_0_cacheHits_0 ? MmuPlugin_ports_0_cache_0_valid : MmuPlugin_ports_0_cache_1_valid);
|
|
assign MmuPlugin_ports_0_cacheLine_exception = (MmuPlugin_ports_0_cacheHits_0 ? MmuPlugin_ports_0_cache_0_exception : MmuPlugin_ports_0_cache_1_exception);
|
|
assign MmuPlugin_ports_0_cacheLine_superPage = (MmuPlugin_ports_0_cacheHits_0 ? MmuPlugin_ports_0_cache_0_superPage : MmuPlugin_ports_0_cache_1_superPage);
|
|
assign MmuPlugin_ports_0_cacheLine_virtualAddress_0 = (MmuPlugin_ports_0_cacheHits_0 ? MmuPlugin_ports_0_cache_0_virtualAddress_0 : MmuPlugin_ports_0_cache_1_virtualAddress_0);
|
|
assign MmuPlugin_ports_0_cacheLine_virtualAddress_1 = (MmuPlugin_ports_0_cacheHits_0 ? MmuPlugin_ports_0_cache_0_virtualAddress_1 : MmuPlugin_ports_0_cache_1_virtualAddress_1);
|
|
assign MmuPlugin_ports_0_cacheLine_physicalAddress_0 = (MmuPlugin_ports_0_cacheHits_0 ? MmuPlugin_ports_0_cache_0_physicalAddress_0 : MmuPlugin_ports_0_cache_1_physicalAddress_0);
|
|
assign MmuPlugin_ports_0_cacheLine_physicalAddress_1 = (MmuPlugin_ports_0_cacheHits_0 ? MmuPlugin_ports_0_cache_0_physicalAddress_1 : MmuPlugin_ports_0_cache_1_physicalAddress_1);
|
|
assign MmuPlugin_ports_0_cacheLine_allowRead = (MmuPlugin_ports_0_cacheHits_0 ? MmuPlugin_ports_0_cache_0_allowRead : MmuPlugin_ports_0_cache_1_allowRead);
|
|
assign MmuPlugin_ports_0_cacheLine_allowWrite = (MmuPlugin_ports_0_cacheHits_0 ? MmuPlugin_ports_0_cache_0_allowWrite : MmuPlugin_ports_0_cache_1_allowWrite);
|
|
assign MmuPlugin_ports_0_cacheLine_allowExecute = (MmuPlugin_ports_0_cacheHits_0 ? MmuPlugin_ports_0_cache_0_allowExecute : MmuPlugin_ports_0_cache_1_allowExecute);
|
|
assign MmuPlugin_ports_0_cacheLine_allowUser = (MmuPlugin_ports_0_cacheHits_0 ? MmuPlugin_ports_0_cache_0_allowUser : MmuPlugin_ports_0_cache_1_allowUser);
|
|
always @ (*) begin
|
|
MmuPlugin_ports_0_entryToReplace_willIncrement = 1'b0;
|
|
if(_zz_181_)begin
|
|
if(_zz_182_)begin
|
|
MmuPlugin_ports_0_entryToReplace_willIncrement = 1'b1;
|
|
end
|
|
end
|
|
end
|
|
|
|
assign MmuPlugin_ports_0_entryToReplace_willClear = 1'b0;
|
|
assign MmuPlugin_ports_0_entryToReplace_willOverflowIfInc = (MmuPlugin_ports_0_entryToReplace_value == (1'b1));
|
|
assign MmuPlugin_ports_0_entryToReplace_willOverflow = (MmuPlugin_ports_0_entryToReplace_willOverflowIfInc && MmuPlugin_ports_0_entryToReplace_willIncrement);
|
|
always @ (*) begin
|
|
MmuPlugin_ports_0_entryToReplace_valueNext = (MmuPlugin_ports_0_entryToReplace_value + MmuPlugin_ports_0_entryToReplace_willIncrement);
|
|
if(MmuPlugin_ports_0_entryToReplace_willClear)begin
|
|
MmuPlugin_ports_0_entryToReplace_valueNext = (1'b0);
|
|
end
|
|
end
|
|
|
|
always @ (*) begin
|
|
MmuPlugin_ports_0_requireMmuLockup = ((1'b1 && (! DBusSimplePlugin_mmuBus_cmd_bypassTranslation)) && MmuPlugin_satp_mode);
|
|
if(((! MmuPlugin_status_mprv) && (CsrPlugin_privilege == (2'b11))))begin
|
|
MmuPlugin_ports_0_requireMmuLockup = 1'b0;
|
|
end
|
|
if((CsrPlugin_privilege == (2'b11)))begin
|
|
if(((! MmuPlugin_status_mprv) || (CsrPlugin_mstatus_MPP == (2'b11))))begin
|
|
MmuPlugin_ports_0_requireMmuLockup = 1'b0;
|
|
end
|
|
end
|
|
end
|
|
|
|
always @ (*) begin
|
|
if(MmuPlugin_ports_0_requireMmuLockup)begin
|
|
DBusSimplePlugin_mmuBus_rsp_physicalAddress = {{MmuPlugin_ports_0_cacheLine_physicalAddress_1,(MmuPlugin_ports_0_cacheLine_superPage ? DBusSimplePlugin_mmuBus_cmd_virtualAddress[21 : 12] : MmuPlugin_ports_0_cacheLine_physicalAddress_0)},DBusSimplePlugin_mmuBus_cmd_virtualAddress[11 : 0]};
|
|
end else begin
|
|
DBusSimplePlugin_mmuBus_rsp_physicalAddress = DBusSimplePlugin_mmuBus_cmd_virtualAddress;
|
|
end
|
|
end
|
|
|
|
always @ (*) begin
|
|
if(MmuPlugin_ports_0_requireMmuLockup)begin
|
|
DBusSimplePlugin_mmuBus_rsp_allowRead = (MmuPlugin_ports_0_cacheLine_allowRead || (MmuPlugin_status_mxr && MmuPlugin_ports_0_cacheLine_allowExecute));
|
|
end else begin
|
|
DBusSimplePlugin_mmuBus_rsp_allowRead = 1'b1;
|
|
end
|
|
end
|
|
|
|
always @ (*) begin
|
|
if(MmuPlugin_ports_0_requireMmuLockup)begin
|
|
DBusSimplePlugin_mmuBus_rsp_allowWrite = MmuPlugin_ports_0_cacheLine_allowWrite;
|
|
end else begin
|
|
DBusSimplePlugin_mmuBus_rsp_allowWrite = 1'b1;
|
|
end
|
|
end
|
|
|
|
always @ (*) begin
|
|
if(MmuPlugin_ports_0_requireMmuLockup)begin
|
|
DBusSimplePlugin_mmuBus_rsp_allowExecute = MmuPlugin_ports_0_cacheLine_allowExecute;
|
|
end else begin
|
|
DBusSimplePlugin_mmuBus_rsp_allowExecute = 1'b1;
|
|
end
|
|
end
|
|
|
|
always @ (*) begin
|
|
if(MmuPlugin_ports_0_requireMmuLockup)begin
|
|
DBusSimplePlugin_mmuBus_rsp_exception = (MmuPlugin_ports_0_cacheHit && ((MmuPlugin_ports_0_cacheLine_exception || ((MmuPlugin_ports_0_cacheLine_allowUser && (CsrPlugin_privilege == (2'b01))) && (! MmuPlugin_status_sum))) || ((! MmuPlugin_ports_0_cacheLine_allowUser) && (CsrPlugin_privilege == (2'b00)))));
|
|
end else begin
|
|
DBusSimplePlugin_mmuBus_rsp_exception = 1'b0;
|
|
end
|
|
end
|
|
|
|
always @ (*) begin
|
|
if(MmuPlugin_ports_0_requireMmuLockup)begin
|
|
DBusSimplePlugin_mmuBus_rsp_refilling = (! MmuPlugin_ports_0_cacheHit);
|
|
end else begin
|
|
DBusSimplePlugin_mmuBus_rsp_refilling = 1'b0;
|
|
end
|
|
end
|
|
|
|
assign DBusSimplePlugin_mmuBus_rsp_isIoAccess = (((DBusSimplePlugin_mmuBus_rsp_physicalAddress[31 : 28] == (4'b1011)) || (DBusSimplePlugin_mmuBus_rsp_physicalAddress[31 : 28] == (4'b1110))) || (DBusSimplePlugin_mmuBus_rsp_physicalAddress[31 : 28] == (4'b1111)));
|
|
assign MmuPlugin_ports_1_cacheHits_0 = ((MmuPlugin_ports_1_cache_0_valid && (MmuPlugin_ports_1_cache_0_virtualAddress_1 == IBusCachedPlugin_mmuBus_cmd_virtualAddress[31 : 22])) && (MmuPlugin_ports_1_cache_0_superPage || (MmuPlugin_ports_1_cache_0_virtualAddress_0 == IBusCachedPlugin_mmuBus_cmd_virtualAddress[21 : 12])));
|
|
assign MmuPlugin_ports_1_cacheHits_1 = ((MmuPlugin_ports_1_cache_1_valid && (MmuPlugin_ports_1_cache_1_virtualAddress_1 == IBusCachedPlugin_mmuBus_cmd_virtualAddress[31 : 22])) && (MmuPlugin_ports_1_cache_1_superPage || (MmuPlugin_ports_1_cache_1_virtualAddress_0 == IBusCachedPlugin_mmuBus_cmd_virtualAddress[21 : 12])));
|
|
assign MmuPlugin_ports_1_cacheHit = ({MmuPlugin_ports_1_cacheHits_1,MmuPlugin_ports_1_cacheHits_0} != (2'b00));
|
|
assign MmuPlugin_ports_1_cacheLine_valid = (MmuPlugin_ports_1_cacheHits_0 ? MmuPlugin_ports_1_cache_0_valid : MmuPlugin_ports_1_cache_1_valid);
|
|
assign MmuPlugin_ports_1_cacheLine_exception = (MmuPlugin_ports_1_cacheHits_0 ? MmuPlugin_ports_1_cache_0_exception : MmuPlugin_ports_1_cache_1_exception);
|
|
assign MmuPlugin_ports_1_cacheLine_superPage = (MmuPlugin_ports_1_cacheHits_0 ? MmuPlugin_ports_1_cache_0_superPage : MmuPlugin_ports_1_cache_1_superPage);
|
|
assign MmuPlugin_ports_1_cacheLine_virtualAddress_0 = (MmuPlugin_ports_1_cacheHits_0 ? MmuPlugin_ports_1_cache_0_virtualAddress_0 : MmuPlugin_ports_1_cache_1_virtualAddress_0);
|
|
assign MmuPlugin_ports_1_cacheLine_virtualAddress_1 = (MmuPlugin_ports_1_cacheHits_0 ? MmuPlugin_ports_1_cache_0_virtualAddress_1 : MmuPlugin_ports_1_cache_1_virtualAddress_1);
|
|
assign MmuPlugin_ports_1_cacheLine_physicalAddress_0 = (MmuPlugin_ports_1_cacheHits_0 ? MmuPlugin_ports_1_cache_0_physicalAddress_0 : MmuPlugin_ports_1_cache_1_physicalAddress_0);
|
|
assign MmuPlugin_ports_1_cacheLine_physicalAddress_1 = (MmuPlugin_ports_1_cacheHits_0 ? MmuPlugin_ports_1_cache_0_physicalAddress_1 : MmuPlugin_ports_1_cache_1_physicalAddress_1);
|
|
assign MmuPlugin_ports_1_cacheLine_allowRead = (MmuPlugin_ports_1_cacheHits_0 ? MmuPlugin_ports_1_cache_0_allowRead : MmuPlugin_ports_1_cache_1_allowRead);
|
|
assign MmuPlugin_ports_1_cacheLine_allowWrite = (MmuPlugin_ports_1_cacheHits_0 ? MmuPlugin_ports_1_cache_0_allowWrite : MmuPlugin_ports_1_cache_1_allowWrite);
|
|
assign MmuPlugin_ports_1_cacheLine_allowExecute = (MmuPlugin_ports_1_cacheHits_0 ? MmuPlugin_ports_1_cache_0_allowExecute : MmuPlugin_ports_1_cache_1_allowExecute);
|
|
assign MmuPlugin_ports_1_cacheLine_allowUser = (MmuPlugin_ports_1_cacheHits_0 ? MmuPlugin_ports_1_cache_0_allowUser : MmuPlugin_ports_1_cache_1_allowUser);
|
|
always @ (*) begin
|
|
MmuPlugin_ports_1_entryToReplace_willIncrement = 1'b0;
|
|
if(_zz_181_)begin
|
|
if(_zz_183_)begin
|
|
MmuPlugin_ports_1_entryToReplace_willIncrement = 1'b1;
|
|
end
|
|
end
|
|
end
|
|
|
|
assign MmuPlugin_ports_1_entryToReplace_willClear = 1'b0;
|
|
assign MmuPlugin_ports_1_entryToReplace_willOverflowIfInc = (MmuPlugin_ports_1_entryToReplace_value == (1'b1));
|
|
assign MmuPlugin_ports_1_entryToReplace_willOverflow = (MmuPlugin_ports_1_entryToReplace_willOverflowIfInc && MmuPlugin_ports_1_entryToReplace_willIncrement);
|
|
always @ (*) begin
|
|
MmuPlugin_ports_1_entryToReplace_valueNext = (MmuPlugin_ports_1_entryToReplace_value + MmuPlugin_ports_1_entryToReplace_willIncrement);
|
|
if(MmuPlugin_ports_1_entryToReplace_willClear)begin
|
|
MmuPlugin_ports_1_entryToReplace_valueNext = (1'b0);
|
|
end
|
|
end
|
|
|
|
always @ (*) begin
|
|
MmuPlugin_ports_1_requireMmuLockup = ((1'b1 && (! IBusCachedPlugin_mmuBus_cmd_bypassTranslation)) && MmuPlugin_satp_mode);
|
|
if(((! MmuPlugin_status_mprv) && (CsrPlugin_privilege == (2'b11))))begin
|
|
MmuPlugin_ports_1_requireMmuLockup = 1'b0;
|
|
end
|
|
if((CsrPlugin_privilege == (2'b11)))begin
|
|
MmuPlugin_ports_1_requireMmuLockup = 1'b0;
|
|
end
|
|
end
|
|
|
|
always @ (*) begin
|
|
if(MmuPlugin_ports_1_requireMmuLockup)begin
|
|
IBusCachedPlugin_mmuBus_rsp_physicalAddress = {{MmuPlugin_ports_1_cacheLine_physicalAddress_1,(MmuPlugin_ports_1_cacheLine_superPage ? IBusCachedPlugin_mmuBus_cmd_virtualAddress[21 : 12] : MmuPlugin_ports_1_cacheLine_physicalAddress_0)},IBusCachedPlugin_mmuBus_cmd_virtualAddress[11 : 0]};
|
|
end else begin
|
|
IBusCachedPlugin_mmuBus_rsp_physicalAddress = IBusCachedPlugin_mmuBus_cmd_virtualAddress;
|
|
end
|
|
end
|
|
|
|
always @ (*) begin
|
|
if(MmuPlugin_ports_1_requireMmuLockup)begin
|
|
IBusCachedPlugin_mmuBus_rsp_allowRead = (MmuPlugin_ports_1_cacheLine_allowRead || (MmuPlugin_status_mxr && MmuPlugin_ports_1_cacheLine_allowExecute));
|
|
end else begin
|
|
IBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1;
|
|
end
|
|
end
|
|
|
|
always @ (*) begin
|
|
if(MmuPlugin_ports_1_requireMmuLockup)begin
|
|
IBusCachedPlugin_mmuBus_rsp_allowWrite = MmuPlugin_ports_1_cacheLine_allowWrite;
|
|
end else begin
|
|
IBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1;
|
|
end
|
|
end
|
|
|
|
always @ (*) begin
|
|
if(MmuPlugin_ports_1_requireMmuLockup)begin
|
|
IBusCachedPlugin_mmuBus_rsp_allowExecute = MmuPlugin_ports_1_cacheLine_allowExecute;
|
|
end else begin
|
|
IBusCachedPlugin_mmuBus_rsp_allowExecute = 1'b1;
|
|
end
|
|
end
|
|
|
|
always @ (*) begin
|
|
if(MmuPlugin_ports_1_requireMmuLockup)begin
|
|
IBusCachedPlugin_mmuBus_rsp_exception = (MmuPlugin_ports_1_cacheHit && ((MmuPlugin_ports_1_cacheLine_exception || ((MmuPlugin_ports_1_cacheLine_allowUser && (CsrPlugin_privilege == (2'b01))) && (! MmuPlugin_status_sum))) || ((! MmuPlugin_ports_1_cacheLine_allowUser) && (CsrPlugin_privilege == (2'b00)))));
|
|
end else begin
|
|
IBusCachedPlugin_mmuBus_rsp_exception = 1'b0;
|
|
end
|
|
end
|
|
|
|
always @ (*) begin
|
|
if(MmuPlugin_ports_1_requireMmuLockup)begin
|
|
IBusCachedPlugin_mmuBus_rsp_refilling = (! MmuPlugin_ports_1_cacheHit);
|
|
end else begin
|
|
IBusCachedPlugin_mmuBus_rsp_refilling = 1'b0;
|
|
end
|
|
end
|
|
|
|
assign IBusCachedPlugin_mmuBus_rsp_isIoAccess = (((IBusCachedPlugin_mmuBus_rsp_physicalAddress[31 : 28] == (4'b1011)) || (IBusCachedPlugin_mmuBus_rsp_physicalAddress[31 : 28] == (4'b1110))) || (IBusCachedPlugin_mmuBus_rsp_physicalAddress[31 : 28] == (4'b1111)));
|
|
assign MmuPlugin_shared_dBusRsp_pte_V = _zz_233_[0];
|
|
assign MmuPlugin_shared_dBusRsp_pte_R = _zz_234_[0];
|
|
assign MmuPlugin_shared_dBusRsp_pte_W = _zz_235_[0];
|
|
assign MmuPlugin_shared_dBusRsp_pte_X = _zz_236_[0];
|
|
assign MmuPlugin_shared_dBusRsp_pte_U = _zz_237_[0];
|
|
assign MmuPlugin_shared_dBusRsp_pte_G = _zz_238_[0];
|
|
assign MmuPlugin_shared_dBusRsp_pte_A = _zz_239_[0];
|
|
assign MmuPlugin_shared_dBusRsp_pte_D = _zz_240_[0];
|
|
assign MmuPlugin_shared_dBusRsp_pte_RSW = MmuPlugin_dBusAccess_rsp_payload_data[9 : 8];
|
|
assign MmuPlugin_shared_dBusRsp_pte_PPN0 = MmuPlugin_dBusAccess_rsp_payload_data[19 : 10];
|
|
assign MmuPlugin_shared_dBusRsp_pte_PPN1 = MmuPlugin_dBusAccess_rsp_payload_data[31 : 20];
|
|
assign MmuPlugin_shared_dBusRsp_exception = (((! MmuPlugin_shared_dBusRsp_pte_V) || ((! MmuPlugin_shared_dBusRsp_pte_R) && MmuPlugin_shared_dBusRsp_pte_W)) || MmuPlugin_dBusAccess_rsp_payload_error);
|
|
assign MmuPlugin_shared_dBusRsp_leaf = (MmuPlugin_shared_dBusRsp_pte_R || MmuPlugin_shared_dBusRsp_pte_X);
|
|
always @ (*) begin
|
|
MmuPlugin_dBusAccess_cmd_valid = 1'b0;
|
|
case(MmuPlugin_shared_state_1_)
|
|
`MmuPlugin_shared_State_defaultEncoding_IDLE : begin
|
|
end
|
|
`MmuPlugin_shared_State_defaultEncoding_L1_CMD : begin
|
|
MmuPlugin_dBusAccess_cmd_valid = 1'b1;
|
|
end
|
|
`MmuPlugin_shared_State_defaultEncoding_L1_RSP : begin
|
|
end
|
|
`MmuPlugin_shared_State_defaultEncoding_L0_CMD : begin
|
|
MmuPlugin_dBusAccess_cmd_valid = 1'b1;
|
|
end
|
|
default : begin
|
|
end
|
|
endcase
|
|
end
|
|
|
|
assign MmuPlugin_dBusAccess_cmd_payload_write = 1'b0;
|
|
assign MmuPlugin_dBusAccess_cmd_payload_size = (2'b10);
|
|
always @ (*) begin
|
|
MmuPlugin_dBusAccess_cmd_payload_address = (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx);
|
|
case(MmuPlugin_shared_state_1_)
|
|
`MmuPlugin_shared_State_defaultEncoding_IDLE : begin
|
|
end
|
|
`MmuPlugin_shared_State_defaultEncoding_L1_CMD : begin
|
|
MmuPlugin_dBusAccess_cmd_payload_address = {{MmuPlugin_satp_ppn,MmuPlugin_shared_vpn_1},(2'b00)};
|
|
end
|
|
`MmuPlugin_shared_State_defaultEncoding_L1_RSP : begin
|
|
end
|
|
`MmuPlugin_shared_State_defaultEncoding_L0_CMD : begin
|
|
MmuPlugin_dBusAccess_cmd_payload_address = {{{MmuPlugin_shared_pteBuffer_PPN1[9 : 0],MmuPlugin_shared_pteBuffer_PPN0},MmuPlugin_shared_vpn_0},(2'b00)};
|
|
end
|
|
default : begin
|
|
end
|
|
endcase
|
|
end
|
|
|
|
assign MmuPlugin_dBusAccess_cmd_payload_data = (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx);
|
|
assign MmuPlugin_dBusAccess_cmd_payload_writeMask = (4'bxxxx);
|
|
assign DBusSimplePlugin_mmuBus_busy = ((MmuPlugin_shared_state_1_ != `MmuPlugin_shared_State_defaultEncoding_IDLE) && (MmuPlugin_shared_portId == (1'b1)));
|
|
assign IBusCachedPlugin_mmuBus_busy = ((MmuPlugin_shared_state_1_ != `MmuPlugin_shared_State_defaultEncoding_IDLE) && (MmuPlugin_shared_portId == (1'b0)));
|
|
always @ (*) begin
|
|
CsrPlugin_privilege = (2'b11);
|
|
if(CsrPlugin_forceMachineWire)begin
|
|
CsrPlugin_privilege = (2'b11);
|
|
end
|
|
end
|
|
|
|
assign CsrPlugin_misa_base = (2'b01);
|
|
assign CsrPlugin_misa_extensions = (26'b00000000000000000000000000);
|
|
assign _zz_137_ = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE);
|
|
assign _zz_138_ = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE);
|
|
assign _zz_139_ = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE);
|
|
assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = (2'b11);
|
|
assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege);
|
|
assign _zz_140_ = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid};
|
|
assign _zz_141_ = _zz_241_[0];
|
|
assign _zz_142_ = {CsrPlugin_selfException_valid,{BranchPlugin_branchExceptionPort_valid,DBusSimplePlugin_memoryExceptionPort_valid}};
|
|
assign _zz_143_ = (_zz_142_ & (~ _zz_243_));
|
|
assign _zz_144_ = _zz_143_[1];
|
|
assign _zz_145_ = _zz_143_[2];
|
|
assign _zz_146_ = {_zz_145_,_zz_144_};
|
|
always @ (*) begin
|
|
CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode;
|
|
if(_zz_173_)begin
|
|
CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b1;
|
|
end
|
|
if(decode_arbitration_isFlushed)begin
|
|
CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b0;
|
|
end
|
|
end
|
|
|
|
always @ (*) begin
|
|
CsrPlugin_exceptionPortCtrl_exceptionValids_execute = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute;
|
|
if(_zz_175_)begin
|
|
CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b1;
|
|
end
|
|
if(execute_arbitration_isFlushed)begin
|
|
CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b0;
|
|
end
|
|
end
|
|
|
|
assign CsrPlugin_exceptionPendings_0 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode;
|
|
assign CsrPlugin_exceptionPendings_1 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute;
|
|
assign CsrPlugin_exception = (CsrPlugin_exceptionPortCtrl_exceptionValids_execute && CsrPlugin_allowException);
|
|
assign CsrPlugin_lastStageWasWfi = 1'b0;
|
|
always @ (*) begin
|
|
CsrPlugin_pipelineLiberator_done = ((! (execute_arbitration_isValid != (1'b0))) && IBusCachedPlugin_pcValids_1);
|
|
if((CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute != (1'b0)))begin
|
|
CsrPlugin_pipelineLiberator_done = 1'b0;
|
|
end
|
|
if(CsrPlugin_hadException)begin
|
|
CsrPlugin_pipelineLiberator_done = 1'b0;
|
|
end
|
|
end
|
|
|
|
assign CsrPlugin_interruptJump = ((CsrPlugin_interrupt_valid && CsrPlugin_pipelineLiberator_done) && CsrPlugin_allowInterrupts);
|
|
always @ (*) begin
|
|
CsrPlugin_targetPrivilege = CsrPlugin_interrupt_targetPrivilege;
|
|
if(CsrPlugin_hadException)begin
|
|
CsrPlugin_targetPrivilege = CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege;
|
|
end
|
|
end
|
|
|
|
always @ (*) begin
|
|
CsrPlugin_trapCause = CsrPlugin_interrupt_code;
|
|
if(CsrPlugin_hadException)begin
|
|
CsrPlugin_trapCause = CsrPlugin_exceptionPortCtrl_exceptionContext_code;
|
|
end
|
|
end
|
|
|
|
always @ (*) begin
|
|
CsrPlugin_xtvec_mode = (2'bxx);
|
|
case(CsrPlugin_targetPrivilege)
|
|
2'b11 : begin
|
|
CsrPlugin_xtvec_mode = CsrPlugin_mtvec_mode;
|
|
end
|
|
default : begin
|
|
end
|
|
endcase
|
|
end
|
|
|
|
always @ (*) begin
|
|
CsrPlugin_xtvec_base = (30'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx);
|
|
case(CsrPlugin_targetPrivilege)
|
|
2'b11 : begin
|
|
CsrPlugin_xtvec_base = CsrPlugin_mtvec_base;
|
|
end
|
|
default : begin
|
|
end
|
|
endcase
|
|
end
|
|
|
|
assign contextSwitching = CsrPlugin_jumpInterface_valid;
|
|
assign _zz_23_ = (! (((decode_INSTRUCTION[14 : 13] == (2'b01)) && (decode_INSTRUCTION[19 : 15] == (5'b00000))) || ((decode_INSTRUCTION[14 : 13] == (2'b11)) && (decode_INSTRUCTION[19 : 15] == (5'b00000)))));
|
|
assign _zz_22_ = (decode_INSTRUCTION[13 : 7] != (7'b0100000));
|
|
assign execute_CsrPlugin_inWfi = 1'b0;
|
|
assign execute_CsrPlugin_blockedBySideEffects = 1'b0;
|
|
always @ (*) begin
|
|
execute_CsrPlugin_illegalAccess = 1'b1;
|
|
case(execute_CsrPlugin_csrAddress)
|
|
12'b101111000000 : begin
|
|
execute_CsrPlugin_illegalAccess = 1'b0;
|
|
end
|
|
12'b001100000000 : begin
|
|
execute_CsrPlugin_illegalAccess = 1'b0;
|
|
end
|
|
12'b000100000000 : begin
|
|
execute_CsrPlugin_illegalAccess = 1'b0;
|
|
end
|
|
12'b001101000001 : begin
|
|
execute_CsrPlugin_illegalAccess = 1'b0;
|
|
end
|
|
12'b101100000000 : begin
|
|
if(execute_CSR_READ_OPCODE)begin
|
|
execute_CsrPlugin_illegalAccess = 1'b0;
|
|
end
|
|
end
|
|
12'b101110000000 : begin
|
|
if(execute_CSR_READ_OPCODE)begin
|
|
execute_CsrPlugin_illegalAccess = 1'b0;
|
|
end
|
|
end
|
|
12'b001101000100 : begin
|
|
execute_CsrPlugin_illegalAccess = 1'b0;
|
|
end
|
|
12'b001100000101 : begin
|
|
if(execute_CSR_WRITE_OPCODE)begin
|
|
execute_CsrPlugin_illegalAccess = 1'b0;
|
|
end
|
|
end
|
|
12'b000110000000 : begin
|
|
execute_CsrPlugin_illegalAccess = 1'b0;
|
|
end
|
|
12'b101100000010 : begin
|
|
if(execute_CSR_READ_OPCODE)begin
|
|
execute_CsrPlugin_illegalAccess = 1'b0;
|
|
end
|
|
end
|
|
12'b001101000011 : begin
|
|
if(execute_CSR_READ_OPCODE)begin
|
|
execute_CsrPlugin_illegalAccess = 1'b0;
|
|
end
|
|
end
|
|
12'b111111000000 : begin
|
|
if(execute_CSR_READ_OPCODE)begin
|
|
execute_CsrPlugin_illegalAccess = 1'b0;
|
|
end
|
|
end
|
|
12'b001101000000 : begin
|
|
execute_CsrPlugin_illegalAccess = 1'b0;
|
|
end
|
|
12'b001100000100 : begin
|
|
execute_CsrPlugin_illegalAccess = 1'b0;
|
|
end
|
|
12'b101110000010 : begin
|
|
if(execute_CSR_READ_OPCODE)begin
|
|
execute_CsrPlugin_illegalAccess = 1'b0;
|
|
end
|
|
end
|
|
12'b001101000010 : begin
|
|
if(execute_CSR_READ_OPCODE)begin
|
|
execute_CsrPlugin_illegalAccess = 1'b0;
|
|
end
|
|
end
|
|
default : begin
|
|
end
|
|
endcase
|
|
if((CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]))begin
|
|
execute_CsrPlugin_illegalAccess = 1'b1;
|
|
end
|
|
if(((! execute_arbitration_isValid) || (! execute_IS_CSR)))begin
|
|
execute_CsrPlugin_illegalAccess = 1'b0;
|
|
end
|
|
end
|
|
|
|
always @ (*) begin
|
|
execute_CsrPlugin_illegalInstruction = 1'b0;
|
|
if((execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)))begin
|
|
if((CsrPlugin_privilege < execute_INSTRUCTION[29 : 28]))begin
|
|
execute_CsrPlugin_illegalInstruction = 1'b1;
|
|
end
|
|
end
|
|
end
|
|
|
|
always @ (*) begin
|
|
CsrPlugin_selfException_valid = 1'b0;
|
|
if(_zz_184_)begin
|
|
CsrPlugin_selfException_valid = 1'b1;
|
|
end
|
|
if(_zz_185_)begin
|
|
CsrPlugin_selfException_valid = 1'b1;
|
|
end
|
|
if(_zz_186_)begin
|
|
CsrPlugin_selfException_valid = 1'b1;
|
|
end
|
|
end
|
|
|
|
always @ (*) begin
|
|
CsrPlugin_selfException_payload_code = (4'bxxxx);
|
|
if(_zz_184_)begin
|
|
CsrPlugin_selfException_payload_code = (4'b0010);
|
|
end
|
|
if(_zz_185_)begin
|
|
case(CsrPlugin_privilege)
|
|
2'b00 : begin
|
|
CsrPlugin_selfException_payload_code = (4'b1000);
|
|
end
|
|
default : begin
|
|
CsrPlugin_selfException_payload_code = (4'b1011);
|
|
end
|
|
endcase
|
|
end
|
|
if(_zz_186_)begin
|
|
CsrPlugin_selfException_payload_code = (4'b0011);
|
|
end
|
|
end
|
|
|
|
assign CsrPlugin_selfException_payload_badAddr = execute_INSTRUCTION;
|
|
always @ (*) begin
|
|
execute_CsrPlugin_readData = (32'b00000000000000000000000000000000);
|
|
case(execute_CsrPlugin_csrAddress)
|
|
12'b101111000000 : begin
|
|
execute_CsrPlugin_readData[31 : 0] = _zz_147_;
|
|
end
|
|
12'b001100000000 : begin
|
|
execute_CsrPlugin_readData[19 : 19] = MmuPlugin_status_mxr;
|
|
execute_CsrPlugin_readData[18 : 18] = MmuPlugin_status_sum;
|
|
execute_CsrPlugin_readData[17 : 17] = MmuPlugin_status_mprv;
|
|
execute_CsrPlugin_readData[12 : 11] = CsrPlugin_mstatus_MPP;
|
|
execute_CsrPlugin_readData[7 : 7] = CsrPlugin_mstatus_MPIE;
|
|
execute_CsrPlugin_readData[3 : 3] = CsrPlugin_mstatus_MIE;
|
|
end
|
|
12'b000100000000 : begin
|
|
execute_CsrPlugin_readData[19 : 19] = MmuPlugin_status_mxr;
|
|
execute_CsrPlugin_readData[18 : 18] = MmuPlugin_status_sum;
|
|
execute_CsrPlugin_readData[17 : 17] = MmuPlugin_status_mprv;
|
|
end
|
|
12'b001101000001 : begin
|
|
execute_CsrPlugin_readData[31 : 0] = CsrPlugin_mepc;
|
|
end
|
|
12'b101100000000 : begin
|
|
execute_CsrPlugin_readData[31 : 0] = CsrPlugin_mcycle[31 : 0];
|
|
end
|
|
12'b101110000000 : begin
|
|
execute_CsrPlugin_readData[31 : 0] = CsrPlugin_mcycle[63 : 32];
|
|
end
|
|
12'b001101000100 : begin
|
|
execute_CsrPlugin_readData[11 : 11] = CsrPlugin_mip_MEIP;
|
|
execute_CsrPlugin_readData[7 : 7] = CsrPlugin_mip_MTIP;
|
|
execute_CsrPlugin_readData[3 : 3] = CsrPlugin_mip_MSIP;
|
|
end
|
|
12'b001100000101 : begin
|
|
end
|
|
12'b000110000000 : begin
|
|
execute_CsrPlugin_readData[31 : 31] = MmuPlugin_satp_mode;
|
|
execute_CsrPlugin_readData[19 : 0] = MmuPlugin_satp_ppn;
|
|
end
|
|
12'b101100000010 : begin
|
|
execute_CsrPlugin_readData[31 : 0] = CsrPlugin_minstret[31 : 0];
|
|
end
|
|
12'b001101000011 : begin
|
|
execute_CsrPlugin_readData[31 : 0] = CsrPlugin_mtval;
|
|
end
|
|
12'b111111000000 : begin
|
|
execute_CsrPlugin_readData[31 : 0] = _zz_148_;
|
|
end
|
|
12'b001101000000 : begin
|
|
execute_CsrPlugin_readData[31 : 0] = CsrPlugin_mscratch;
|
|
end
|
|
12'b001100000100 : begin
|
|
execute_CsrPlugin_readData[11 : 11] = CsrPlugin_mie_MEIE;
|
|
execute_CsrPlugin_readData[7 : 7] = CsrPlugin_mie_MTIE;
|
|
execute_CsrPlugin_readData[3 : 3] = CsrPlugin_mie_MSIE;
|
|
end
|
|
12'b101110000010 : begin
|
|
execute_CsrPlugin_readData[31 : 0] = CsrPlugin_minstret[63 : 32];
|
|
end
|
|
12'b001101000010 : begin
|
|
execute_CsrPlugin_readData[31 : 31] = CsrPlugin_mcause_interrupt;
|
|
execute_CsrPlugin_readData[3 : 0] = CsrPlugin_mcause_exceptionCode;
|
|
end
|
|
default : begin
|
|
end
|
|
endcase
|
|
end
|
|
|
|
assign execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE);
|
|
assign execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE);
|
|
assign execute_CsrPlugin_writeEnable = ((execute_CsrPlugin_writeInstruction && (! execute_CsrPlugin_blockedBySideEffects)) && (! execute_arbitration_isStuckByOthers));
|
|
assign execute_CsrPlugin_readEnable = ((execute_CsrPlugin_readInstruction && (! execute_CsrPlugin_blockedBySideEffects)) && (! execute_arbitration_isStuckByOthers));
|
|
assign execute_CsrPlugin_readToWriteData = execute_CsrPlugin_readData;
|
|
always @ (*) begin
|
|
case(_zz_200_)
|
|
1'b0 : begin
|
|
execute_CsrPlugin_writeData = execute_SRC1;
|
|
end
|
|
default : begin
|
|
execute_CsrPlugin_writeData = (execute_INSTRUCTION[12] ? (execute_CsrPlugin_readToWriteData & (~ execute_SRC1)) : (execute_CsrPlugin_readToWriteData | execute_SRC1));
|
|
end
|
|
endcase
|
|
end
|
|
|
|
assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20];
|
|
assign _zz_148_ = (_zz_147_ & externalInterruptArray_regNext);
|
|
assign externalInterrupt = (_zz_148_ != (32'b00000000000000000000000000000000));
|
|
assign _zz_21_ = decode_SRC1_CTRL;
|
|
assign _zz_19_ = _zz_53_;
|
|
assign _zz_34_ = decode_to_execute_SRC1_CTRL;
|
|
assign _zz_18_ = decode_ALU_BITWISE_CTRL;
|
|
assign _zz_16_ = _zz_54_;
|
|
assign _zz_39_ = decode_to_execute_ALU_BITWISE_CTRL;
|
|
assign _zz_15_ = decode_BRANCH_CTRL;
|
|
assign _zz_13_ = _zz_58_;
|
|
assign _zz_26_ = decode_to_execute_BRANCH_CTRL;
|
|
assign _zz_12_ = decode_SRC2_CTRL;
|
|
assign _zz_10_ = _zz_48_;
|
|
assign _zz_32_ = decode_to_execute_SRC2_CTRL;
|
|
assign _zz_9_ = decode_ALU_CTRL;
|
|
assign _zz_7_ = _zz_43_;
|
|
assign _zz_37_ = decode_to_execute_ALU_CTRL;
|
|
assign _zz_6_ = decode_SHIFT_CTRL;
|
|
assign _zz_4_ = _zz_49_;
|
|
assign _zz_28_ = decode_to_execute_SHIFT_CTRL;
|
|
assign _zz_3_ = decode_ENV_CTRL;
|
|
assign _zz_1_ = _zz_45_;
|
|
assign _zz_24_ = decode_to_execute_ENV_CTRL;
|
|
assign decode_arbitration_isFlushed = ((execute_arbitration_flushNext != (1'b0)) || ({execute_arbitration_flushIt,decode_arbitration_flushIt} != (2'b00)));
|
|
assign execute_arbitration_isFlushed = (1'b0 || (execute_arbitration_flushIt != (1'b0)));
|
|
assign decode_arbitration_isStuckByOthers = (decode_arbitration_haltByOther || (1'b0 || execute_arbitration_isStuck));
|
|
assign decode_arbitration_isStuck = (decode_arbitration_haltItself || decode_arbitration_isStuckByOthers);
|
|
assign decode_arbitration_isMoving = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt));
|
|
assign decode_arbitration_isFiring = ((decode_arbitration_isValid && (! decode_arbitration_isStuck)) && (! decode_arbitration_removeIt));
|
|
assign execute_arbitration_isStuckByOthers = (execute_arbitration_haltByOther || 1'b0);
|
|
assign execute_arbitration_isStuck = (execute_arbitration_haltItself || execute_arbitration_isStuckByOthers);
|
|
assign execute_arbitration_isMoving = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt));
|
|
assign execute_arbitration_isFiring = ((execute_arbitration_isValid && (! execute_arbitration_isStuck)) && (! execute_arbitration_removeIt));
|
|
assign iBusWishbone_ADR = {_zz_257_,_zz_149_};
|
|
assign iBusWishbone_CTI = ((_zz_149_ == (3'b111)) ? (3'b111) : (3'b010));
|
|
assign iBusWishbone_BTE = (2'b00);
|
|
assign iBusWishbone_SEL = (4'b1111);
|
|
assign iBusWishbone_WE = 1'b0;
|
|
assign iBusWishbone_DAT_MOSI = (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx);
|
|
always @ (*) begin
|
|
iBusWishbone_CYC = 1'b0;
|
|
if(_zz_187_)begin
|
|
iBusWishbone_CYC = 1'b1;
|
|
end
|
|
end
|
|
|
|
always @ (*) begin
|
|
iBusWishbone_STB = 1'b0;
|
|
if(_zz_187_)begin
|
|
iBusWishbone_STB = 1'b1;
|
|
end
|
|
end
|
|
|
|
assign iBus_cmd_ready = (iBus_cmd_valid && iBusWishbone_ACK);
|
|
assign iBus_rsp_valid = _zz_150_;
|
|
assign iBus_rsp_payload_data = iBusWishbone_DAT_MISO_regNext;
|
|
assign iBus_rsp_payload_error = 1'b0;
|
|
assign dBus_cmd_halfPipe_valid = dBus_cmd_halfPipe_regs_valid;
|
|
assign dBus_cmd_halfPipe_payload_wr = dBus_cmd_halfPipe_regs_payload_wr;
|
|
assign dBus_cmd_halfPipe_payload_address = dBus_cmd_halfPipe_regs_payload_address;
|
|
assign dBus_cmd_halfPipe_payload_data = dBus_cmd_halfPipe_regs_payload_data;
|
|
assign dBus_cmd_halfPipe_payload_size = dBus_cmd_halfPipe_regs_payload_size;
|
|
assign dBus_cmd_ready = dBus_cmd_halfPipe_regs_ready;
|
|
assign dBusWishbone_ADR = (dBus_cmd_halfPipe_payload_address >>> 2);
|
|
assign dBusWishbone_CTI = (3'b000);
|
|
assign dBusWishbone_BTE = (2'b00);
|
|
always @ (*) begin
|
|
case(dBus_cmd_halfPipe_payload_size)
|
|
2'b00 : begin
|
|
_zz_151_ = (4'b0001);
|
|
end
|
|
2'b01 : begin
|
|
_zz_151_ = (4'b0011);
|
|
end
|
|
default : begin
|
|
_zz_151_ = (4'b1111);
|
|
end
|
|
endcase
|
|
end
|
|
|
|
always @ (*) begin
|
|
dBusWishbone_SEL = _zz_258_[3:0];
|
|
if((! dBus_cmd_halfPipe_payload_wr))begin
|
|
dBusWishbone_SEL = (4'b1111);
|
|
end
|
|
end
|
|
|
|
assign dBusWishbone_WE = dBus_cmd_halfPipe_payload_wr;
|
|
assign dBusWishbone_DAT_MOSI = dBus_cmd_halfPipe_payload_data;
|
|
assign dBus_cmd_halfPipe_ready = (dBus_cmd_halfPipe_valid && dBusWishbone_ACK);
|
|
assign dBusWishbone_CYC = dBus_cmd_halfPipe_valid;
|
|
assign dBusWishbone_STB = dBus_cmd_halfPipe_valid;
|
|
assign dBus_rsp_ready = ((dBus_cmd_halfPipe_valid && (! dBusWishbone_WE)) && dBusWishbone_ACK);
|
|
assign dBus_rsp_data = dBusWishbone_DAT_MISO;
|
|
assign dBus_rsp_error = 1'b0;
|
|
always @ (posedge clk) begin
|
|
if(reset) begin
|
|
IBusCachedPlugin_fetchPc_pcReg <= externalResetVector;
|
|
IBusCachedPlugin_fetchPc_booted <= 1'b0;
|
|
IBusCachedPlugin_fetchPc_inc <= 1'b0;
|
|
_zz_90_ <= 1'b0;
|
|
_zz_91_ <= 1'b0;
|
|
IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0;
|
|
IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0;
|
|
IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0;
|
|
IBusCachedPlugin_injector_decodeRemoved <= 1'b0;
|
|
IBusCachedPlugin_rspCounter <= _zz_96_;
|
|
IBusCachedPlugin_rspCounter <= (32'b00000000000000000000000000000000);
|
|
_zz_97_ <= 1'b0;
|
|
execute_DBusSimplePlugin_atomic_reserved <= 1'b0;
|
|
_zz_104_ <= (2'b00);
|
|
execute_LightShifterPlugin_isActive <= 1'b0;
|
|
MmuPlugin_status_sum <= 1'b0;
|
|
MmuPlugin_status_mxr <= 1'b0;
|
|
MmuPlugin_status_mprv <= 1'b0;
|
|
MmuPlugin_satp_mode <= 1'b0;
|
|
MmuPlugin_ports_0_cache_0_valid <= 1'b0;
|
|
MmuPlugin_ports_0_cache_1_valid <= 1'b0;
|
|
MmuPlugin_ports_0_entryToReplace_value <= (1'b0);
|
|
MmuPlugin_ports_1_cache_0_valid <= 1'b0;
|
|
MmuPlugin_ports_1_cache_1_valid <= 1'b0;
|
|
MmuPlugin_ports_1_entryToReplace_value <= (1'b0);
|
|
MmuPlugin_shared_state_1_ <= `MmuPlugin_shared_State_defaultEncoding_IDLE;
|
|
CsrPlugin_mstatus_MIE <= 1'b0;
|
|
CsrPlugin_mstatus_MPIE <= 1'b0;
|
|
CsrPlugin_mstatus_MPP <= (2'b11);
|
|
CsrPlugin_mie_MEIE <= 1'b0;
|
|
CsrPlugin_mie_MTIE <= 1'b0;
|
|
CsrPlugin_mie_MSIE <= 1'b0;
|
|
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0;
|
|
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= 1'b0;
|
|
CsrPlugin_interrupt_valid <= 1'b0;
|
|
CsrPlugin_hadException <= 1'b0;
|
|
execute_CsrPlugin_wfiWake <= 1'b0;
|
|
_zz_147_ <= (32'b00000000000000000000000000000000);
|
|
execute_arbitration_isValid <= 1'b0;
|
|
_zz_149_ <= (3'b000);
|
|
_zz_150_ <= 1'b0;
|
|
dBus_cmd_halfPipe_regs_valid <= 1'b0;
|
|
dBus_cmd_halfPipe_regs_ready <= 1'b1;
|
|
end else begin
|
|
IBusCachedPlugin_fetchPc_booted <= 1'b1;
|
|
if((IBusCachedPlugin_fetchPc_corrected || IBusCachedPlugin_fetchPc_pcRegPropagate))begin
|
|
IBusCachedPlugin_fetchPc_inc <= 1'b0;
|
|
end
|
|
if((IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready))begin
|
|
IBusCachedPlugin_fetchPc_inc <= 1'b1;
|
|
end
|
|
if(((! IBusCachedPlugin_fetchPc_output_valid) && IBusCachedPlugin_fetchPc_output_ready))begin
|
|
IBusCachedPlugin_fetchPc_inc <= 1'b0;
|
|
end
|
|
if((IBusCachedPlugin_fetchPc_booted && ((IBusCachedPlugin_fetchPc_output_ready || IBusCachedPlugin_fetcherflushIt) || IBusCachedPlugin_fetchPc_pcRegPropagate)))begin
|
|
IBusCachedPlugin_fetchPc_pcReg <= IBusCachedPlugin_fetchPc_pc;
|
|
end
|
|
if(IBusCachedPlugin_fetcherflushIt)begin
|
|
_zz_90_ <= 1'b0;
|
|
end
|
|
if(_zz_88_)begin
|
|
_zz_90_ <= IBusCachedPlugin_iBusRsp_stages_0_output_valid;
|
|
end
|
|
if(IBusCachedPlugin_iBusRsp_inputBeforeStage_ready)begin
|
|
_zz_91_ <= IBusCachedPlugin_iBusRsp_inputBeforeStage_valid;
|
|
end
|
|
if(IBusCachedPlugin_fetcherflushIt)begin
|
|
_zz_91_ <= 1'b0;
|
|
end
|
|
if(IBusCachedPlugin_fetcherflushIt)begin
|
|
IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0;
|
|
end
|
|
if((! (! IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready)))begin
|
|
IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b1;
|
|
end
|
|
if(IBusCachedPlugin_fetcherflushIt)begin
|
|
IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0;
|
|
end
|
|
if((! (! IBusCachedPlugin_injector_decodeInput_ready)))begin
|
|
IBusCachedPlugin_injector_nextPcCalc_valids_1 <= IBusCachedPlugin_injector_nextPcCalc_valids_0;
|
|
end
|
|
if(IBusCachedPlugin_fetcherflushIt)begin
|
|
IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0;
|
|
end
|
|
if(IBusCachedPlugin_fetcherflushIt)begin
|
|
IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0;
|
|
end
|
|
if((! execute_arbitration_isStuck))begin
|
|
IBusCachedPlugin_injector_nextPcCalc_valids_2 <= IBusCachedPlugin_injector_nextPcCalc_valids_1;
|
|
end
|
|
if(IBusCachedPlugin_fetcherflushIt)begin
|
|
IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0;
|
|
end
|
|
if(decode_arbitration_removeIt)begin
|
|
IBusCachedPlugin_injector_decodeRemoved <= 1'b1;
|
|
end
|
|
if(IBusCachedPlugin_fetcherflushIt)begin
|
|
IBusCachedPlugin_injector_decodeRemoved <= 1'b0;
|
|
end
|
|
if(iBus_rsp_valid)begin
|
|
IBusCachedPlugin_rspCounter <= (IBusCachedPlugin_rspCounter + (32'b00000000000000000000000000000001));
|
|
end
|
|
if((dBus_cmd_valid && dBus_cmd_ready))begin
|
|
_zz_97_ <= 1'b1;
|
|
end
|
|
if((! execute_arbitration_isStuck))begin
|
|
_zz_97_ <= 1'b0;
|
|
end
|
|
if((((execute_arbitration_isFiring && execute_MEMORY_ENABLE) && execute_MEMORY_ATOMIC) && (! execute_MEMORY_STORE)))begin
|
|
execute_DBusSimplePlugin_atomic_reserved <= 1'b1;
|
|
end
|
|
if(contextSwitching)begin
|
|
execute_DBusSimplePlugin_atomic_reserved <= 1'b0;
|
|
end
|
|
case(_zz_104_)
|
|
2'b00 : begin
|
|
if(MmuPlugin_dBusAccess_cmd_valid)begin
|
|
if((! (execute_arbitration_isValid != (1'b0))))begin
|
|
_zz_104_ <= (2'b01);
|
|
end
|
|
end
|
|
end
|
|
2'b01 : begin
|
|
if(dBus_cmd_ready)begin
|
|
_zz_104_ <= (MmuPlugin_dBusAccess_cmd_payload_write ? (2'b00) : (2'b10));
|
|
end
|
|
end
|
|
2'b10 : begin
|
|
if(dBus_rsp_ready)begin
|
|
_zz_104_ <= (2'b00);
|
|
end
|
|
end
|
|
default : begin
|
|
end
|
|
endcase
|
|
if(_zz_167_)begin
|
|
if(_zz_174_)begin
|
|
execute_LightShifterPlugin_isActive <= 1'b1;
|
|
if(execute_LightShifterPlugin_done)begin
|
|
execute_LightShifterPlugin_isActive <= 1'b0;
|
|
end
|
|
end
|
|
end
|
|
if(execute_arbitration_removeIt)begin
|
|
execute_LightShifterPlugin_isActive <= 1'b0;
|
|
end
|
|
MmuPlugin_ports_0_entryToReplace_value <= MmuPlugin_ports_0_entryToReplace_valueNext;
|
|
if(contextSwitching)begin
|
|
if(MmuPlugin_ports_0_cache_0_exception)begin
|
|
MmuPlugin_ports_0_cache_0_valid <= 1'b0;
|
|
end
|
|
if(MmuPlugin_ports_0_cache_1_exception)begin
|
|
MmuPlugin_ports_0_cache_1_valid <= 1'b0;
|
|
end
|
|
end
|
|
MmuPlugin_ports_1_entryToReplace_value <= MmuPlugin_ports_1_entryToReplace_valueNext;
|
|
if(contextSwitching)begin
|
|
if(MmuPlugin_ports_1_cache_0_exception)begin
|
|
MmuPlugin_ports_1_cache_0_valid <= 1'b0;
|
|
end
|
|
if(MmuPlugin_ports_1_cache_1_exception)begin
|
|
MmuPlugin_ports_1_cache_1_valid <= 1'b0;
|
|
end
|
|
end
|
|
case(MmuPlugin_shared_state_1_)
|
|
`MmuPlugin_shared_State_defaultEncoding_IDLE : begin
|
|
if(_zz_188_)begin
|
|
MmuPlugin_shared_state_1_ <= `MmuPlugin_shared_State_defaultEncoding_L1_CMD;
|
|
end
|
|
if(_zz_189_)begin
|
|
MmuPlugin_shared_state_1_ <= `MmuPlugin_shared_State_defaultEncoding_L1_CMD;
|
|
end
|
|
end
|
|
`MmuPlugin_shared_State_defaultEncoding_L1_CMD : begin
|
|
if(MmuPlugin_dBusAccess_cmd_ready)begin
|
|
MmuPlugin_shared_state_1_ <= `MmuPlugin_shared_State_defaultEncoding_L1_RSP;
|
|
end
|
|
end
|
|
`MmuPlugin_shared_State_defaultEncoding_L1_RSP : begin
|
|
if(MmuPlugin_dBusAccess_rsp_valid)begin
|
|
MmuPlugin_shared_state_1_ <= `MmuPlugin_shared_State_defaultEncoding_L0_CMD;
|
|
if((MmuPlugin_shared_dBusRsp_leaf || MmuPlugin_shared_dBusRsp_exception))begin
|
|
MmuPlugin_shared_state_1_ <= `MmuPlugin_shared_State_defaultEncoding_IDLE;
|
|
end
|
|
if(MmuPlugin_dBusAccess_rsp_payload_redo)begin
|
|
MmuPlugin_shared_state_1_ <= `MmuPlugin_shared_State_defaultEncoding_L1_CMD;
|
|
end
|
|
end
|
|
end
|
|
`MmuPlugin_shared_State_defaultEncoding_L0_CMD : begin
|
|
if(MmuPlugin_dBusAccess_cmd_ready)begin
|
|
MmuPlugin_shared_state_1_ <= `MmuPlugin_shared_State_defaultEncoding_L0_RSP;
|
|
end
|
|
end
|
|
default : begin
|
|
if(MmuPlugin_dBusAccess_rsp_valid)begin
|
|
MmuPlugin_shared_state_1_ <= `MmuPlugin_shared_State_defaultEncoding_IDLE;
|
|
if(MmuPlugin_dBusAccess_rsp_payload_redo)begin
|
|
MmuPlugin_shared_state_1_ <= `MmuPlugin_shared_State_defaultEncoding_L0_CMD;
|
|
end
|
|
end
|
|
end
|
|
endcase
|
|
if(_zz_181_)begin
|
|
if(_zz_182_)begin
|
|
if(_zz_190_)begin
|
|
MmuPlugin_ports_0_cache_0_valid <= 1'b1;
|
|
end
|
|
if(_zz_191_)begin
|
|
MmuPlugin_ports_0_cache_1_valid <= 1'b1;
|
|
end
|
|
end
|
|
if(_zz_183_)begin
|
|
if(_zz_192_)begin
|
|
MmuPlugin_ports_1_cache_0_valid <= 1'b1;
|
|
end
|
|
if(_zz_193_)begin
|
|
MmuPlugin_ports_1_cache_1_valid <= 1'b1;
|
|
end
|
|
end
|
|
end
|
|
if((execute_arbitration_isValid && execute_IS_SFENCE_VMA))begin
|
|
MmuPlugin_ports_0_cache_0_valid <= 1'b0;
|
|
MmuPlugin_ports_0_cache_1_valid <= 1'b0;
|
|
MmuPlugin_ports_1_cache_0_valid <= 1'b0;
|
|
MmuPlugin_ports_1_cache_1_valid <= 1'b0;
|
|
end
|
|
if((! decode_arbitration_isStuck))begin
|
|
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0;
|
|
end else begin
|
|
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= CsrPlugin_exceptionPortCtrl_exceptionValids_decode;
|
|
end
|
|
if((! execute_arbitration_isStuck))begin
|
|
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= (CsrPlugin_exceptionPortCtrl_exceptionValids_decode && (! decode_arbitration_isStuck));
|
|
end else begin
|
|
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= 1'b0;
|
|
end
|
|
CsrPlugin_interrupt_valid <= 1'b0;
|
|
if(_zz_194_)begin
|
|
if(_zz_195_)begin
|
|
CsrPlugin_interrupt_valid <= 1'b1;
|
|
end
|
|
if(_zz_196_)begin
|
|
CsrPlugin_interrupt_valid <= 1'b1;
|
|
end
|
|
if(_zz_197_)begin
|
|
CsrPlugin_interrupt_valid <= 1'b1;
|
|
end
|
|
end
|
|
CsrPlugin_hadException <= CsrPlugin_exception;
|
|
if(_zz_176_)begin
|
|
case(CsrPlugin_targetPrivilege)
|
|
2'b11 : begin
|
|
CsrPlugin_mstatus_MIE <= 1'b0;
|
|
CsrPlugin_mstatus_MPIE <= CsrPlugin_mstatus_MIE;
|
|
CsrPlugin_mstatus_MPP <= CsrPlugin_privilege;
|
|
end
|
|
default : begin
|
|
end
|
|
endcase
|
|
end
|
|
if(_zz_177_)begin
|
|
case(_zz_178_)
|
|
2'b11 : begin
|
|
CsrPlugin_mstatus_MPP <= (2'b00);
|
|
CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE;
|
|
CsrPlugin_mstatus_MPIE <= 1'b1;
|
|
end
|
|
default : begin
|
|
end
|
|
endcase
|
|
end
|
|
execute_CsrPlugin_wfiWake <= ({_zz_139_,{_zz_138_,_zz_137_}} != (3'b000));
|
|
if(((! execute_arbitration_isStuck) || execute_arbitration_removeIt))begin
|
|
execute_arbitration_isValid <= 1'b0;
|
|
end
|
|
if(((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)))begin
|
|
execute_arbitration_isValid <= decode_arbitration_isValid;
|
|
end
|
|
case(execute_CsrPlugin_csrAddress)
|
|
12'b101111000000 : begin
|
|
if(execute_CsrPlugin_writeEnable)begin
|
|
_zz_147_ <= execute_CsrPlugin_writeData[31 : 0];
|
|
end
|
|
end
|
|
12'b001100000000 : begin
|
|
if(execute_CsrPlugin_writeEnable)begin
|
|
MmuPlugin_status_mxr <= _zz_244_[0];
|
|
MmuPlugin_status_sum <= _zz_245_[0];
|
|
MmuPlugin_status_mprv <= _zz_246_[0];
|
|
CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11];
|
|
CsrPlugin_mstatus_MPIE <= _zz_247_[0];
|
|
CsrPlugin_mstatus_MIE <= _zz_248_[0];
|
|
end
|
|
end
|
|
12'b000100000000 : begin
|
|
if(execute_CsrPlugin_writeEnable)begin
|
|
MmuPlugin_status_mxr <= _zz_249_[0];
|
|
MmuPlugin_status_sum <= _zz_250_[0];
|
|
MmuPlugin_status_mprv <= _zz_251_[0];
|
|
end
|
|
end
|
|
12'b001101000001 : begin
|
|
end
|
|
12'b101100000000 : begin
|
|
end
|
|
12'b101110000000 : begin
|
|
end
|
|
12'b001101000100 : begin
|
|
end
|
|
12'b001100000101 : begin
|
|
end
|
|
12'b000110000000 : begin
|
|
if(execute_CsrPlugin_writeEnable)begin
|
|
MmuPlugin_satp_mode <= _zz_253_[0];
|
|
end
|
|
end
|
|
12'b101100000010 : begin
|
|
end
|
|
12'b001101000011 : begin
|
|
end
|
|
12'b111111000000 : begin
|
|
end
|
|
12'b001101000000 : begin
|
|
end
|
|
12'b001100000100 : begin
|
|
if(execute_CsrPlugin_writeEnable)begin
|
|
CsrPlugin_mie_MEIE <= _zz_254_[0];
|
|
CsrPlugin_mie_MTIE <= _zz_255_[0];
|
|
CsrPlugin_mie_MSIE <= _zz_256_[0];
|
|
end
|
|
end
|
|
12'b101110000010 : begin
|
|
end
|
|
12'b001101000010 : begin
|
|
end
|
|
default : begin
|
|
end
|
|
endcase
|
|
if(_zz_187_)begin
|
|
if(iBusWishbone_ACK)begin
|
|
_zz_149_ <= (_zz_149_ + (3'b001));
|
|
end
|
|
end
|
|
_zz_150_ <= (iBusWishbone_CYC && iBusWishbone_ACK);
|
|
if(_zz_198_)begin
|
|
dBus_cmd_halfPipe_regs_valid <= dBus_cmd_valid;
|
|
dBus_cmd_halfPipe_regs_ready <= (! dBus_cmd_valid);
|
|
end else begin
|
|
dBus_cmd_halfPipe_regs_valid <= (! dBus_cmd_halfPipe_ready);
|
|
dBus_cmd_halfPipe_regs_ready <= dBus_cmd_halfPipe_ready;
|
|
end
|
|
end
|
|
end
|
|
|
|
always @ (posedge clk) begin
|
|
if(IBusCachedPlugin_iBusRsp_inputBeforeStage_ready)begin
|
|
_zz_92_ <= IBusCachedPlugin_iBusRsp_inputBeforeStage_payload_pc;
|
|
_zz_93_ <= IBusCachedPlugin_iBusRsp_inputBeforeStage_payload_rsp_error;
|
|
_zz_94_ <= IBusCachedPlugin_iBusRsp_inputBeforeStage_payload_rsp_inst;
|
|
_zz_95_ <= IBusCachedPlugin_iBusRsp_inputBeforeStage_payload_isRvc;
|
|
end
|
|
if(IBusCachedPlugin_injector_decodeInput_ready)begin
|
|
IBusCachedPlugin_injector_formal_rawInDecode <= IBusCachedPlugin_iBusRsp_inputBeforeStage_payload_rsp_inst;
|
|
end
|
|
if(IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready)begin
|
|
IBusCachedPlugin_s1_tightlyCoupledHit <= IBusCachedPlugin_s0_tightlyCoupledHit;
|
|
end
|
|
if((! execute_arbitration_isStuckByOthers))begin
|
|
execute_LightShifterPlugin_shiftReg <= _zz_61_;
|
|
end
|
|
if(_zz_167_)begin
|
|
if(_zz_174_)begin
|
|
execute_LightShifterPlugin_amplitudeReg <= (execute_LightShifterPlugin_amplitude - (5'b00001));
|
|
end
|
|
end
|
|
if((MmuPlugin_dBusAccess_rsp_valid && (! MmuPlugin_dBusAccess_rsp_payload_redo)))begin
|
|
MmuPlugin_shared_pteBuffer_V <= MmuPlugin_shared_dBusRsp_pte_V;
|
|
MmuPlugin_shared_pteBuffer_R <= MmuPlugin_shared_dBusRsp_pte_R;
|
|
MmuPlugin_shared_pteBuffer_W <= MmuPlugin_shared_dBusRsp_pte_W;
|
|
MmuPlugin_shared_pteBuffer_X <= MmuPlugin_shared_dBusRsp_pte_X;
|
|
MmuPlugin_shared_pteBuffer_U <= MmuPlugin_shared_dBusRsp_pte_U;
|
|
MmuPlugin_shared_pteBuffer_G <= MmuPlugin_shared_dBusRsp_pte_G;
|
|
MmuPlugin_shared_pteBuffer_A <= MmuPlugin_shared_dBusRsp_pte_A;
|
|
MmuPlugin_shared_pteBuffer_D <= MmuPlugin_shared_dBusRsp_pte_D;
|
|
MmuPlugin_shared_pteBuffer_RSW <= MmuPlugin_shared_dBusRsp_pte_RSW;
|
|
MmuPlugin_shared_pteBuffer_PPN0 <= MmuPlugin_shared_dBusRsp_pte_PPN0;
|
|
MmuPlugin_shared_pteBuffer_PPN1 <= MmuPlugin_shared_dBusRsp_pte_PPN1;
|
|
end
|
|
case(MmuPlugin_shared_state_1_)
|
|
`MmuPlugin_shared_State_defaultEncoding_IDLE : begin
|
|
if(_zz_188_)begin
|
|
MmuPlugin_shared_vpn_1 <= IBusCachedPlugin_mmuBus_cmd_virtualAddress[31 : 22];
|
|
MmuPlugin_shared_vpn_0 <= IBusCachedPlugin_mmuBus_cmd_virtualAddress[21 : 12];
|
|
MmuPlugin_shared_portId <= (1'b0);
|
|
end
|
|
if(_zz_189_)begin
|
|
MmuPlugin_shared_vpn_1 <= DBusSimplePlugin_mmuBus_cmd_virtualAddress[31 : 22];
|
|
MmuPlugin_shared_vpn_0 <= DBusSimplePlugin_mmuBus_cmd_virtualAddress[21 : 12];
|
|
MmuPlugin_shared_portId <= (1'b1);
|
|
end
|
|
end
|
|
`MmuPlugin_shared_State_defaultEncoding_L1_CMD : begin
|
|
end
|
|
`MmuPlugin_shared_State_defaultEncoding_L1_RSP : begin
|
|
end
|
|
`MmuPlugin_shared_State_defaultEncoding_L0_CMD : begin
|
|
end
|
|
default : begin
|
|
end
|
|
endcase
|
|
if(_zz_181_)begin
|
|
if(_zz_182_)begin
|
|
if(_zz_190_)begin
|
|
MmuPlugin_ports_0_cache_0_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1_ == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != (10'b0000000000))));
|
|
MmuPlugin_ports_0_cache_0_virtualAddress_0 <= MmuPlugin_shared_vpn_0;
|
|
MmuPlugin_ports_0_cache_0_virtualAddress_1 <= MmuPlugin_shared_vpn_1;
|
|
MmuPlugin_ports_0_cache_0_physicalAddress_0 <= MmuPlugin_shared_dBusRsp_pte_PPN0;
|
|
MmuPlugin_ports_0_cache_0_physicalAddress_1 <= MmuPlugin_shared_dBusRsp_pte_PPN1[9 : 0];
|
|
MmuPlugin_ports_0_cache_0_allowRead <= MmuPlugin_shared_dBusRsp_pte_R;
|
|
MmuPlugin_ports_0_cache_0_allowWrite <= MmuPlugin_shared_dBusRsp_pte_W;
|
|
MmuPlugin_ports_0_cache_0_allowExecute <= MmuPlugin_shared_dBusRsp_pte_X;
|
|
MmuPlugin_ports_0_cache_0_allowUser <= MmuPlugin_shared_dBusRsp_pte_U;
|
|
MmuPlugin_ports_0_cache_0_superPage <= (MmuPlugin_shared_state_1_ == `MmuPlugin_shared_State_defaultEncoding_L1_RSP);
|
|
end
|
|
if(_zz_191_)begin
|
|
MmuPlugin_ports_0_cache_1_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1_ == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != (10'b0000000000))));
|
|
MmuPlugin_ports_0_cache_1_virtualAddress_0 <= MmuPlugin_shared_vpn_0;
|
|
MmuPlugin_ports_0_cache_1_virtualAddress_1 <= MmuPlugin_shared_vpn_1;
|
|
MmuPlugin_ports_0_cache_1_physicalAddress_0 <= MmuPlugin_shared_dBusRsp_pte_PPN0;
|
|
MmuPlugin_ports_0_cache_1_physicalAddress_1 <= MmuPlugin_shared_dBusRsp_pte_PPN1[9 : 0];
|
|
MmuPlugin_ports_0_cache_1_allowRead <= MmuPlugin_shared_dBusRsp_pte_R;
|
|
MmuPlugin_ports_0_cache_1_allowWrite <= MmuPlugin_shared_dBusRsp_pte_W;
|
|
MmuPlugin_ports_0_cache_1_allowExecute <= MmuPlugin_shared_dBusRsp_pte_X;
|
|
MmuPlugin_ports_0_cache_1_allowUser <= MmuPlugin_shared_dBusRsp_pte_U;
|
|
MmuPlugin_ports_0_cache_1_superPage <= (MmuPlugin_shared_state_1_ == `MmuPlugin_shared_State_defaultEncoding_L1_RSP);
|
|
end
|
|
end
|
|
if(_zz_183_)begin
|
|
if(_zz_192_)begin
|
|
MmuPlugin_ports_1_cache_0_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1_ == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != (10'b0000000000))));
|
|
MmuPlugin_ports_1_cache_0_virtualAddress_0 <= MmuPlugin_shared_vpn_0;
|
|
MmuPlugin_ports_1_cache_0_virtualAddress_1 <= MmuPlugin_shared_vpn_1;
|
|
MmuPlugin_ports_1_cache_0_physicalAddress_0 <= MmuPlugin_shared_dBusRsp_pte_PPN0;
|
|
MmuPlugin_ports_1_cache_0_physicalAddress_1 <= MmuPlugin_shared_dBusRsp_pte_PPN1[9 : 0];
|
|
MmuPlugin_ports_1_cache_0_allowRead <= MmuPlugin_shared_dBusRsp_pte_R;
|
|
MmuPlugin_ports_1_cache_0_allowWrite <= MmuPlugin_shared_dBusRsp_pte_W;
|
|
MmuPlugin_ports_1_cache_0_allowExecute <= MmuPlugin_shared_dBusRsp_pte_X;
|
|
MmuPlugin_ports_1_cache_0_allowUser <= MmuPlugin_shared_dBusRsp_pte_U;
|
|
MmuPlugin_ports_1_cache_0_superPage <= (MmuPlugin_shared_state_1_ == `MmuPlugin_shared_State_defaultEncoding_L1_RSP);
|
|
end
|
|
if(_zz_193_)begin
|
|
MmuPlugin_ports_1_cache_1_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1_ == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != (10'b0000000000))));
|
|
MmuPlugin_ports_1_cache_1_virtualAddress_0 <= MmuPlugin_shared_vpn_0;
|
|
MmuPlugin_ports_1_cache_1_virtualAddress_1 <= MmuPlugin_shared_vpn_1;
|
|
MmuPlugin_ports_1_cache_1_physicalAddress_0 <= MmuPlugin_shared_dBusRsp_pte_PPN0;
|
|
MmuPlugin_ports_1_cache_1_physicalAddress_1 <= MmuPlugin_shared_dBusRsp_pte_PPN1[9 : 0];
|
|
MmuPlugin_ports_1_cache_1_allowRead <= MmuPlugin_shared_dBusRsp_pte_R;
|
|
MmuPlugin_ports_1_cache_1_allowWrite <= MmuPlugin_shared_dBusRsp_pte_W;
|
|
MmuPlugin_ports_1_cache_1_allowExecute <= MmuPlugin_shared_dBusRsp_pte_X;
|
|
MmuPlugin_ports_1_cache_1_allowUser <= MmuPlugin_shared_dBusRsp_pte_U;
|
|
MmuPlugin_ports_1_cache_1_superPage <= (MmuPlugin_shared_state_1_ == `MmuPlugin_shared_State_defaultEncoding_L1_RSP);
|
|
end
|
|
end
|
|
end
|
|
CsrPlugin_mip_MEIP <= externalInterrupt;
|
|
CsrPlugin_mip_MTIP <= timerInterrupt;
|
|
CsrPlugin_mip_MSIP <= softwareInterrupt;
|
|
CsrPlugin_mcycle <= (CsrPlugin_mcycle + (64'b0000000000000000000000000000000000000000000000000000000000000001));
|
|
if(execute_arbitration_isFiring)begin
|
|
CsrPlugin_minstret <= (CsrPlugin_minstret + (64'b0000000000000000000000000000000000000000000000000000000000000001));
|
|
end
|
|
if(_zz_173_)begin
|
|
CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_141_ ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code);
|
|
CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_141_ ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr);
|
|
end
|
|
if(_zz_175_)begin
|
|
CsrPlugin_exceptionPortCtrl_exceptionContext_code <= _zz_165_;
|
|
CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= _zz_166_;
|
|
end
|
|
if(_zz_194_)begin
|
|
if(_zz_195_)begin
|
|
CsrPlugin_interrupt_code <= (4'b0111);
|
|
CsrPlugin_interrupt_targetPrivilege <= (2'b11);
|
|
end
|
|
if(_zz_196_)begin
|
|
CsrPlugin_interrupt_code <= (4'b0011);
|
|
CsrPlugin_interrupt_targetPrivilege <= (2'b11);
|
|
end
|
|
if(_zz_197_)begin
|
|
CsrPlugin_interrupt_code <= (4'b1011);
|
|
CsrPlugin_interrupt_targetPrivilege <= (2'b11);
|
|
end
|
|
end
|
|
if(_zz_176_)begin
|
|
case(CsrPlugin_targetPrivilege)
|
|
2'b11 : begin
|
|
CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException);
|
|
CsrPlugin_mcause_exceptionCode <= CsrPlugin_trapCause;
|
|
CsrPlugin_mepc <= execute_PC;
|
|
if(CsrPlugin_hadException)begin
|
|
CsrPlugin_mtval <= CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr;
|
|
end
|
|
end
|
|
default : begin
|
|
end
|
|
endcase
|
|
end
|
|
externalInterruptArray_regNext <= externalInterruptArray;
|
|
if((! execute_arbitration_isStuck))begin
|
|
decode_to_execute_MEMORY_ATOMIC <= decode_MEMORY_ATOMIC;
|
|
end
|
|
if((! execute_arbitration_isStuck))begin
|
|
decode_to_execute_IS_SFENCE_VMA <= decode_IS_SFENCE_VMA;
|
|
end
|
|
if((! execute_arbitration_isStuck))begin
|
|
decode_to_execute_SRC1_CTRL <= _zz_20_;
|
|
end
|
|
if((! execute_arbitration_isStuck))begin
|
|
decode_to_execute_SRC2_FORCE_ZERO <= decode_SRC2_FORCE_ZERO;
|
|
end
|
|
if((! execute_arbitration_isStuck))begin
|
|
decode_to_execute_FORMAL_PC_NEXT <= _zz_77_;
|
|
end
|
|
if((! execute_arbitration_isStuck))begin
|
|
decode_to_execute_ALU_BITWISE_CTRL <= _zz_17_;
|
|
end
|
|
if((! execute_arbitration_isStuck))begin
|
|
decode_to_execute_SRC_USE_SUB_LESS <= decode_SRC_USE_SUB_LESS;
|
|
end
|
|
if((! execute_arbitration_isStuck))begin
|
|
decode_to_execute_CSR_WRITE_OPCODE <= decode_CSR_WRITE_OPCODE;
|
|
end
|
|
if((! execute_arbitration_isStuck))begin
|
|
decode_to_execute_BRANCH_CTRL <= _zz_14_;
|
|
end
|
|
if((! execute_arbitration_isStuck))begin
|
|
decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID;
|
|
end
|
|
if((! execute_arbitration_isStuck))begin
|
|
decode_to_execute_SRC2_CTRL <= _zz_11_;
|
|
end
|
|
if((! execute_arbitration_isStuck))begin
|
|
decode_to_execute_ALU_CTRL <= _zz_8_;
|
|
end
|
|
if((! execute_arbitration_isStuck))begin
|
|
decode_to_execute_CSR_READ_OPCODE <= decode_CSR_READ_OPCODE;
|
|
end
|
|
if(((! execute_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_execute)))begin
|
|
decode_to_execute_PC <= decode_PC;
|
|
end
|
|
if((! execute_arbitration_isStuck))begin
|
|
decode_to_execute_SHIFT_CTRL <= _zz_5_;
|
|
end
|
|
if((! execute_arbitration_isStuck))begin
|
|
decode_to_execute_MEMORY_STORE <= decode_MEMORY_STORE;
|
|
end
|
|
if((! execute_arbitration_isStuck))begin
|
|
decode_to_execute_IS_CSR <= decode_IS_CSR;
|
|
end
|
|
if((! execute_arbitration_isStuck))begin
|
|
decode_to_execute_INSTRUCTION <= decode_INSTRUCTION;
|
|
end
|
|
if((! execute_arbitration_isStuck))begin
|
|
decode_to_execute_ENV_CTRL <= _zz_2_;
|
|
end
|
|
if((! execute_arbitration_isStuck))begin
|
|
decode_to_execute_MEMORY_ENABLE <= decode_MEMORY_ENABLE;
|
|
end
|
|
if((! execute_arbitration_isStuck))begin
|
|
decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED;
|
|
end
|
|
case(execute_CsrPlugin_csrAddress)
|
|
12'b101111000000 : begin
|
|
end
|
|
12'b001100000000 : begin
|
|
end
|
|
12'b000100000000 : begin
|
|
end
|
|
12'b001101000001 : begin
|
|
if(execute_CsrPlugin_writeEnable)begin
|
|
CsrPlugin_mepc <= execute_CsrPlugin_writeData[31 : 0];
|
|
end
|
|
end
|
|
12'b101100000000 : begin
|
|
end
|
|
12'b101110000000 : begin
|
|
end
|
|
12'b001101000100 : begin
|
|
if(execute_CsrPlugin_writeEnable)begin
|
|
CsrPlugin_mip_MSIP <= _zz_252_[0];
|
|
end
|
|
end
|
|
12'b001100000101 : begin
|
|
if(execute_CsrPlugin_writeEnable)begin
|
|
CsrPlugin_mtvec_base <= execute_CsrPlugin_writeData[31 : 2];
|
|
CsrPlugin_mtvec_mode <= execute_CsrPlugin_writeData[1 : 0];
|
|
end
|
|
end
|
|
12'b000110000000 : begin
|
|
if(execute_CsrPlugin_writeEnable)begin
|
|
MmuPlugin_satp_ppn <= execute_CsrPlugin_writeData[19 : 0];
|
|
end
|
|
end
|
|
12'b101100000010 : begin
|
|
end
|
|
12'b001101000011 : begin
|
|
end
|
|
12'b111111000000 : begin
|
|
end
|
|
12'b001101000000 : begin
|
|
if(execute_CsrPlugin_writeEnable)begin
|
|
CsrPlugin_mscratch <= execute_CsrPlugin_writeData[31 : 0];
|
|
end
|
|
end
|
|
12'b001100000100 : begin
|
|
end
|
|
12'b101110000010 : begin
|
|
end
|
|
12'b001101000010 : begin
|
|
end
|
|
default : begin
|
|
end
|
|
endcase
|
|
iBusWishbone_DAT_MISO_regNext <= iBusWishbone_DAT_MISO;
|
|
if(_zz_198_)begin
|
|
dBus_cmd_halfPipe_regs_payload_wr <= dBus_cmd_payload_wr;
|
|
dBus_cmd_halfPipe_regs_payload_address <= dBus_cmd_payload_address;
|
|
dBus_cmd_halfPipe_regs_payload_data <= dBus_cmd_payload_data;
|
|
dBus_cmd_halfPipe_regs_payload_size <= dBus_cmd_payload_size;
|
|
end
|
|
end
|
|
|
|
endmodule
|
|
|