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45e3b5b617
These are all independent modules, so break each one out into its own file. Signed-off-by: Sean Cross <sean@xobs.io>
44 lines
1.5 KiB
Python
44 lines
1.5 KiB
Python
from litex.soc.interconnect import wishbone
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class RandomFirmwareROM(wishbone.SRAM):
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"""
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Seed the random data with a fixed number, so different bitstreams
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can all share firmware.
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"""
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def __init__(self, size, seed=2373):
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def xorshift32(x):
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x = x ^ (x << 13) & 0xffffffff
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x = x ^ (x >> 17) & 0xffffffff
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x = x ^ (x << 5) & 0xffffffff
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return x & 0xffffffff
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def get_rand(x):
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out = 0
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for i in range(32):
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x = xorshift32(x)
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if (x & 1) == 1:
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out = out | (1 << i)
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return out & 0xffffffff
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data = []
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seed = 1
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for d in range(int(size / 4)):
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seed = get_rand(seed)
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data.append(seed)
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wishbone.SRAM.__init__(self, size, read_only=True, init=data)
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class FirmwareROM(wishbone.SRAM):
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def __init__(self, size, filename):
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data = []
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with open(filename, 'rb') as inp:
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data = inp.read()
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wishbone.SRAM.__init__(self, size, read_only=True, init=data)
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class JumpToAddressROM(wishbone.SRAM):
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def __init__(self, size, addr):
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data = [
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0x00000537 | ((addr & 0xfffff000) << 0 ), # lui a0,%hi(addr)
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0x00052503 | ((addr & 0x00000fff) << 20), # lw a0,%lo(addr)(a0)
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0x000500e7, # jalr a0
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]
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wishbone.SRAM.__init__(self, size, read_only=True, init=data)
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