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https://github.com/im-tomu/foboot.git
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58 lines
3.0 KiB
Python
58 lines
3.0 KiB
Python
from migen import Module, Signal, If, Instance
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from litex.soc.integration.doc import ModuleDoc
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from litex.soc.interconnect.csr import AutoCSR, CSRStatus, CSRStorage, CSRField
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import litex.soc.doc as lxsocdoc
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class SBWarmBoot(Module, AutoCSR):
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def __init__(self, parent, offsets=None):
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table = ""
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if offsets is not None:
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arr = [["Image", "Offset"]]
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for i,offset in enumerate(offsets):
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arr.append([str(i), str(offset)])
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table = "\nYou can use this block to reboot into one of these four addresses:\n\n" \
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+ lxsocdoc.rst.make_table(arr)
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self.intro = ModuleDoc("""FPGA Reboot Interface
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This module provides the ability to reboot the FPGA. It is based on the
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``SB_WARMBOOT`` primitive built in to the FPGA.
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When power is applied to the FPGA, it reads configuration data from the
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onboard flash chip. This contains reboot offsets for four images. It then
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booted from the first image, but kept note of the other addresses.
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{}""".format(table))
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self.ctrl = CSRStorage(fields=[
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CSRField("image", size=2, description="""
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Which image to reboot to. ``SB_WARMBOOT`` supports four images that
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are configured at FPGA startup. The bootloader is image 0, so set
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these bits to 0 to reboot back into the bootloader.
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"""),
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CSRField("key", size=6, description="""
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A reboot key used to prevent accidental reboots when writing to random
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areas of memory. To initiate a reboot, set this to ``0b101011``.""")
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], description="""
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Provides support for rebooting the FPGA. You can select which of the four images
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to reboot to, just be sure to OR the image number with ``0xac``. For example,
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to reboot to the bootloader (image 0), write ``0xac``` to this register."""
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)
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self.addr = CSRStorage(size=32, description="""
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This sets the reset vector for the VexRiscv. This address will be used whenever
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the CPU is reset, for example through a debug bridge. You should update this
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address whenever you load a new program, to enable the debugger to run ``mon reset``
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"""
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)
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do_reset = Signal()
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self.comb += [
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# "Reset Key" is 0xac (0b101011xx)
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do_reset.eq(self.ctrl.storage[2] & self.ctrl.storage[3] & ~self.ctrl.storage[4]
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& self.ctrl.storage[5] & ~self.ctrl.storage[6] & self.ctrl.storage[7])
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]
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self.specials += Instance("SB_WARMBOOT",
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i_S0 = self.ctrl.storage[0],
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i_S1 = self.ctrl.storage[1],
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i_BOOT = do_reset,
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)
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parent.config["BITSTREAM_SYNC_HEADER1"] = 0x7e99aa7e
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parent.config["BITSTREAM_SYNC_HEADER2"] = 0x7eaa997e
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