mirror of
https://github.com/im-tomu/foboot.git
synced 2024-09-20 02:40:09 +00:00
9b264dc7c4
Signed-off-by: Sean Cross <sean@xobs.io>
1025 lines
47 KiB
XML
1025 lines
47 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
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<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd" >
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<vendor>Foosn</vendor>
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<name>FOMU</name>
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<addressUnitBits>8</addressUnitBits>
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<width>32</width>
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<size>32</size>
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<access>read-write</access>
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<resetValue>0x00000000</resetValue>
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<resetMask>0xFFFFFFFF</resetMask>
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<peripherals>
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<peripheral>
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<name>CTRL</name>
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<baseAddress>0xE0000000</baseAddress>
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<groupName>CTRL</groupName>
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<registers>
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<register>
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<name>RESET</name>
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<addressOffset>0x0000</addressOffset>
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<resetValue>0x00</resetValue>
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</register>
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<register>
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<name>SCRATCH3</name>
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<description>Bits 24-31 of `CTRL_SCRATCH`.</description>
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<addressOffset>0x0004</addressOffset>
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<resetValue>0x12</resetValue>
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</register>
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<register>
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<name>SCRATCH2</name>
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<description>Bits 16-23 of `CTRL_SCRATCH`.</description>
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<addressOffset>0x0008</addressOffset>
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<resetValue>0x34</resetValue>
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</register>
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<register>
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<name>SCRATCH1</name>
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<description>Bits 8-15 of `CTRL_SCRATCH`.</description>
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<addressOffset>0x000c</addressOffset>
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<resetValue>0x56</resetValue>
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</register>
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<register>
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<name>SCRATCH0</name>
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<description>Bits 0-7 of `CTRL_SCRATCH`.</description>
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<addressOffset>0x0010</addressOffset>
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<resetValue>0x78</resetValue>
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</register>
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<register>
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<name>BUS_ERRORS3</name>
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<description>Bits 24-31 of `CTRL_BUS_ERRORS`.</description>
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<addressOffset>0x0014</addressOffset>
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<resetValue>0x00</resetValue>
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</register>
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<register>
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<name>BUS_ERRORS2</name>
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<description>Bits 16-23 of `CTRL_BUS_ERRORS`.</description>
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<addressOffset>0x0018</addressOffset>
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<resetValue>0x00</resetValue>
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</register>
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<register>
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<name>BUS_ERRORS1</name>
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<description>Bits 8-15 of `CTRL_BUS_ERRORS`.</description>
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<addressOffset>0x001c</addressOffset>
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<resetValue>0x00</resetValue>
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</register>
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<register>
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<name>BUS_ERRORS0</name>
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<description>Bits 0-7 of `CTRL_BUS_ERRORS`.</description>
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<addressOffset>0x0020</addressOffset>
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<resetValue>0x00</resetValue>
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</register>
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</registers>
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<addressBlock>
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<offset>0</offset>
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<size>0x24</size>
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<usage>registers</usage>
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</addressBlock>
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</peripheral>
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<peripheral>
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<name>LXSPI</name>
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<baseAddress>0xE0007800</baseAddress>
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<groupName>LXSPI</groupName>
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<registers>
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<register>
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<name>BITBANG</name>
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<description>Bitbang controls for SPI output. Only standard 1x SPI is supported,
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meaning the IO2 and IO3 lines will be hardwired to `1` during bitbang mode.</description>
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<addressOffset>0x0000</addressOffset>
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<resetValue>0x00</resetValue>
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<fields>
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<field>
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<name>mosi</name>
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<msb>0</msb>
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<bitRange>[0:0]</bitRange>
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<lsb>0</lsb>
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<description><![CDATA[MOSI output pin, valid whenever `dir` is `0`.]]></description>
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</field>
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<field>
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<name>clk</name>
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<msb>1</msb>
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<bitRange>[1:1]</bitRange>
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<lsb>1</lsb>
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<description><![CDATA[Output value for SPI CLK line.]]></description>
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</field>
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<field>
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<name>cs_n</name>
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<msb>2</msb>
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<bitRange>[2:2]</bitRange>
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<lsb>2</lsb>
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<description><![CDATA[Output value of SPI CSn line.]]></description>
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</field>
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<field>
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<name>dir</name>
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<msb>3</msb>
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<bitRange>[3:3]</bitRange>
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<lsb>3</lsb>
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<description><![CDATA[Dual/Quad SPI reuses pins SPI pin direction.]]></description>
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</field>
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</fields>
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</register>
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<register>
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<name>MISO</name>
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<description>Incoming value of MISO signal.</description>
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<addressOffset>0x0004</addressOffset>
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<resetValue>0x00</resetValue>
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</register>
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<register>
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<name>BITBANG_EN</name>
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<description>Write a `1` here to disable memory-mapped mode and enable bitbang mode.</description>
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<addressOffset>0x0008</addressOffset>
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<resetValue>0x00</resetValue>
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</register>
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</registers>
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<addressBlock>
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<offset>0</offset>
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<size>0xc</size>
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<usage>registers</usage>
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</addressBlock>
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</peripheral>
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<peripheral>
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<name>MESSIBLE</name>
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<baseAddress>0xE0008000</baseAddress>
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<groupName>MESSIBLE</groupName>
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<registers>
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<register>
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<name>IN</name>
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<description>Write half of the FIFO to send data out the Messible. Writing to this register
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advances the write pointer automatically.</description>
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<addressOffset>0x0000</addressOffset>
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<resetValue>0x00</resetValue>
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</register>
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<register>
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<name>OUT</name>
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<description>Read half of the FIFO to receive data on the Messible. Reading from this
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register advances the read pointer automatically.</description>
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<addressOffset>0x0004</addressOffset>
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<resetValue>0x00</resetValue>
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</register>
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<register>
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<name>STATUS</name>
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<addressOffset>0x0008</addressOffset>
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<resetValue>0x00</resetValue>
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<fields>
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<field>
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<name>full</name>
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<msb>0</msb>
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<bitRange>[0:0]</bitRange>
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<lsb>0</lsb>
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<description><![CDATA[``0`` if more data can fit into the IN FIFO.]]></description>
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</field>
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<field>
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<name>have</name>
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<msb>1</msb>
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<bitRange>[1:1]</bitRange>
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<lsb>1</lsb>
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<description><![CDATA[``1`` if data can be read from the OUT FIFO.]]></description>
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</field>
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</fields>
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</register>
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</registers>
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<addressBlock>
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<offset>0</offset>
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<size>0xc</size>
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<usage>registers</usage>
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</addressBlock>
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</peripheral>
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<peripheral>
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<name>REBOOT</name>
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<baseAddress>0xE0006000</baseAddress>
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<groupName>REBOOT</groupName>
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<registers>
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<register>
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<name>CTRL</name>
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<description>Provides support for rebooting the FPGA. You can select which of the four
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images to reboot to, just be sure to OR the image number with ``0xac``. For
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example, to reboot to the bootloader (image 0), write ``0xac``` to this
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register.</description>
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<addressOffset>0x0000</addressOffset>
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<resetValue>0x00</resetValue>
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<fields>
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<field>
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<name>image</name>
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<msb>1</msb>
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<bitRange>[1:0]</bitRange>
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<lsb>0</lsb>
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<description><![CDATA[Which image to reboot to. ``SB_WARMBOOT`` supports four images that are
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configured at FPGA startup. The bootloader is image 0, so set these bits to 0
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to reboot back into the bootloader.]]></description>
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</field>
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<field>
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<name>key</name>
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<msb>7</msb>
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<bitRange>[7:2]</bitRange>
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<lsb>2</lsb>
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<description><![CDATA[A reboot key used to prevent accidental reboots when writing to random areas of
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memory. To initiate a reboot, set this to ``0b101011``.]]></description>
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</field>
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</fields>
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</register>
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<register>
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<name>ADDR3</name>
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<description>Bits 24-31 of `REBOOT_ADDR`. This sets the reset vector for the VexRiscv. This
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address will be used whenever the CPU is reset, for example through a debug
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bridge. You should update this address whenever you load a new program, to
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enable the debugger to run ``mon reset``</description>
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<addressOffset>0x0004</addressOffset>
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<resetValue>0x00</resetValue>
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</register>
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<register>
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<name>ADDR2</name>
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<description>Bits 16-23 of `REBOOT_ADDR`.</description>
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<addressOffset>0x0008</addressOffset>
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<resetValue>0x00</resetValue>
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</register>
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<register>
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<name>ADDR1</name>
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<description>Bits 8-15 of `REBOOT_ADDR`.</description>
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<addressOffset>0x000c</addressOffset>
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<resetValue>0x00</resetValue>
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</register>
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<register>
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<name>ADDR0</name>
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<description>Bits 0-7 of `REBOOT_ADDR`.</description>
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<addressOffset>0x0010</addressOffset>
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<resetValue>0x00</resetValue>
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</register>
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</registers>
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<addressBlock>
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<offset>0</offset>
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<size>0x14</size>
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<usage>registers</usage>
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</addressBlock>
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</peripheral>
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<peripheral>
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<name>RGB</name>
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<baseAddress>0xE0006800</baseAddress>
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<groupName>RGB</groupName>
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<registers>
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<register>
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<name>DAT</name>
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<description>This is the value for the ``SB_LEDDA_IP.DAT`` register. It is directly written
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into the ``SB_LEDDA_IP`` hardware block, so you should refer to
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http://www.latticesemi.com/view_document?document_id=50668. The contents of this
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register are written to the address specified in ``ADDR`` immediately upon
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writing this register.</description>
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<addressOffset>0x0000</addressOffset>
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<resetValue>0x00</resetValue>
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</register>
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<register>
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<name>ADDR</name>
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<description>This register is directly connected to ``SB_LEDDA_IP.ADDR``. This register
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controls the address that is updated whenever ``DAT`` is written. Writing to
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this register has no immediate effect -- data isn't written until the ``DAT``
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register is written.</description>
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<addressOffset>0x0004</addressOffset>
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<resetValue>0x00</resetValue>
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</register>
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<register>
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<name>CTRL</name>
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<description>Control logic for the RGB LED and LEDDA hardware PWM LED block.</description>
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<addressOffset>0x0008</addressOffset>
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<resetValue>0x00</resetValue>
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<fields>
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<field>
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<name>exe</name>
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<msb>0</msb>
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<bitRange>[0:0]</bitRange>
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<lsb>0</lsb>
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<description><![CDATA[Connected to ``SB_LEDDA_IP.LEDDEXE``. Set this to ``1`` to enable the fading
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pattern.]]></description>
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</field>
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<field>
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<name>curren</name>
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<msb>1</msb>
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<bitRange>[1:1]</bitRange>
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<lsb>1</lsb>
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<description><![CDATA[Connected to ``SB_RGBA_DRV.CURREN``. Set this to ``1`` to enable the current
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source.]]></description>
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</field>
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<field>
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<name>rgbleden</name>
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<msb>2</msb>
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<bitRange>[2:2]</bitRange>
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<lsb>2</lsb>
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<description><![CDATA[Connected to ``SB_RGBA_DRV.RGBLEDEN``. Set this to ``1`` to enable the RGB PWM
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control logic.]]></description>
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</field>
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<field>
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<name>rraw</name>
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<msb>3</msb>
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<bitRange>[3:3]</bitRange>
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<lsb>3</lsb>
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<description><![CDATA[Set this to ``1`` to enable raw control of the red LED via the ``RAW.R``
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register.]]></description>
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</field>
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<field>
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<name>graw</name>
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<msb>4</msb>
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<bitRange>[4:4]</bitRange>
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<lsb>4</lsb>
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<description><![CDATA[Set this to ``1`` to enable raw control of the green LED via the ``RAW.G``
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register.]]></description>
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</field>
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<field>
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<name>braw</name>
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<msb>5</msb>
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<bitRange>[5:5]</bitRange>
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<lsb>5</lsb>
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<description><![CDATA[Set this to ``1`` to enable raw control of the blue LED via the ``RAW.B``
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register.]]></description>
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</field>
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</fields>
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</register>
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<register>
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<name>RAW</name>
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<description>Normally the hardware ``SB_LEDDA_IP`` block controls the brightness of the LED,
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creating a gentle fading pattern. However, by setting the appropriate bit in
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``CTRL``, it is possible to manually control the three individual LEDs.</description>
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<addressOffset>0x000c</addressOffset>
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<resetValue>0x00</resetValue>
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<fields>
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<field>
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<name>r</name>
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<msb>0</msb>
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<bitRange>[0:0]</bitRange>
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<lsb>0</lsb>
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<description><![CDATA[Raw value for the red LED when ``CTRL.RRAW`` is ``1``.]]></description>
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</field>
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<field>
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<name>g</name>
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<msb>1</msb>
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<bitRange>[1:1]</bitRange>
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<lsb>1</lsb>
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<description><![CDATA[Raw value for the green LED when ``CTRL.GRAW`` is ``1``.]]></description>
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</field>
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<field>
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<name>b</name>
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<msb>2</msb>
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<bitRange>[2:2]</bitRange>
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<lsb>2</lsb>
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<description><![CDATA[Raw value for the blue LED when ``CTRL.BRAW`` is ``1``.]]></description>
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</field>
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</fields>
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</register>
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</registers>
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<addressBlock>
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<offset>0</offset>
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<size>0x10</size>
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<usage>registers</usage>
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</addressBlock>
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</peripheral>
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<peripheral>
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<name>TIMER0</name>
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<baseAddress>0xE0002800</baseAddress>
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<groupName>TIMER0</groupName>
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<registers>
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<register>
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<name>LOAD3</name>
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<description>Bits 24-31 of `TIMER0_LOAD`. Load value when Timer is (re-)enabled.In One-Shot
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mode, the value written to this register specify the Timer's duration in
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clock cycles.</description>
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<addressOffset>0x0000</addressOffset>
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<resetValue>0x00</resetValue>
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</register>
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<register>
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<name>LOAD2</name>
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<description>Bits 16-23 of `TIMER0_LOAD`.</description>
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<addressOffset>0x0004</addressOffset>
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<resetValue>0x00</resetValue>
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</register>
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<register>
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<name>LOAD1</name>
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<description>Bits 8-15 of `TIMER0_LOAD`.</description>
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<addressOffset>0x0008</addressOffset>
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<resetValue>0x00</resetValue>
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</register>
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<register>
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<name>LOAD0</name>
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<description>Bits 0-7 of `TIMER0_LOAD`.</description>
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<addressOffset>0x000c</addressOffset>
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<resetValue>0x00</resetValue>
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</register>
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<register>
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<name>RELOAD3</name>
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<description>Bits 24-31 of `TIMER0_RELOAD`. Reload value when Timer reaches 0.In Periodic
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mode, the value written to this register specify the Timer's period in
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clock cycles.</description>
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<addressOffset>0x0010</addressOffset>
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<resetValue>0x00</resetValue>
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</register>
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<register>
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<name>RELOAD2</name>
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<description>Bits 16-23 of `TIMER0_RELOAD`.</description>
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<addressOffset>0x0014</addressOffset>
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<resetValue>0x00</resetValue>
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</register>
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<register>
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<name>RELOAD1</name>
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<description>Bits 8-15 of `TIMER0_RELOAD`.</description>
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<addressOffset>0x0018</addressOffset>
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<resetValue>0x00</resetValue>
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</register>
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<register>
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<name>RELOAD0</name>
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<description>Bits 0-7 of `TIMER0_RELOAD`.</description>
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<addressOffset>0x001c</addressOffset>
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<resetValue>0x00</resetValue>
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</register>
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<register>
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<name>EN</name>
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<description>Enable of the Timer.Set if to 1 to enable/start the Timer and 0 to disable the
|
|
Timer</description>
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<addressOffset>0x0020</addressOffset>
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<resetValue>0x00</resetValue>
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</register>
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|
<register>
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|
<name>UPDATE_VALUE</name>
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|
<description>Update of the current countdown value.A write to this register latches the
|
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current countdown value to `value` register.</description>
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<addressOffset>0x0024</addressOffset>
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<resetValue>0x00</resetValue>
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</register>
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<register>
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|
<name>VALUE3</name>
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<description>Bits 24-31 of `TIMER0_VALUE`. Latched countdown value</description>
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<addressOffset>0x0028</addressOffset>
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<resetValue>0x00</resetValue>
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</register>
|
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<register>
|
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<name>VALUE2</name>
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<description>Bits 16-23 of `TIMER0_VALUE`.</description>
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<addressOffset>0x002c</addressOffset>
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<resetValue>0x00</resetValue>
|
|
</register>
|
|
<register>
|
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<name>VALUE1</name>
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<description>Bits 8-15 of `TIMER0_VALUE`.</description>
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<addressOffset>0x0030</addressOffset>
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<resetValue>0x00</resetValue>
|
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</register>
|
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<register>
|
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<name>VALUE0</name>
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<description>Bits 0-7 of `TIMER0_VALUE`.</description>
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<addressOffset>0x0034</addressOffset>
|
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<resetValue>0x00</resetValue>
|
|
</register>
|
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<register>
|
|
<name>EV_STATUS</name>
|
|
<addressOffset>0x0038</addressOffset>
|
|
<resetValue>0x00</resetValue>
|
|
</register>
|
|
<register>
|
|
<name>EV_PENDING</name>
|
|
<addressOffset>0x003c</addressOffset>
|
|
<resetValue>0x00</resetValue>
|
|
</register>
|
|
<register>
|
|
<name>EV_ENABLE</name>
|
|
<addressOffset>0x0040</addressOffset>
|
|
<resetValue>0x00</resetValue>
|
|
</register>
|
|
</registers>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x44</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>timer0</name>
|
|
<value>2</value>
|
|
</interrupt>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>TOUCH</name>
|
|
<baseAddress>0xE0005800</baseAddress>
|
|
<groupName>TOUCH</groupName>
|
|
<registers>
|
|
<register>
|
|
<name>O</name>
|
|
<description>Output values for pads 1-4</description>
|
|
<addressOffset>0x0000</addressOffset>
|
|
<resetValue>0x00</resetValue>
|
|
</register>
|
|
<register>
|
|
<name>OE</name>
|
|
<description>Output enable control for pads 1-4</description>
|
|
<addressOffset>0x0004</addressOffset>
|
|
<resetValue>0x00</resetValue>
|
|
</register>
|
|
<register>
|
|
<name>I</name>
|
|
<description>Input value for pads 1-4</description>
|
|
<addressOffset>0x0008</addressOffset>
|
|
<resetValue>0x00</resetValue>
|
|
</register>
|
|
</registers>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0xc</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>USB</name>
|
|
<baseAddress>0xE0004800</baseAddress>
|
|
<groupName>USB</groupName>
|
|
<registers>
|
|
<register>
|
|
<name>PULLUP_OUT</name>
|
|
<addressOffset>0x0000</addressOffset>
|
|
<resetValue>0x00</resetValue>
|
|
</register>
|
|
<register>
|
|
<name>ADDRESS</name>
|
|
<description>Sets the USB device address, in order to ignore packets going to other devices
|
|
on the bus. This value is reset when the host issues a USB Device Reset
|
|
condition.</description>
|
|
<addressOffset>0x0004</addressOffset>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>addr</name>
|
|
<msb>6</msb>
|
|
<bitRange>[6:0]</bitRange>
|
|
<lsb>0</lsb>
|
|
<description><![CDATA[Write the USB address from USB ``SET_ADDRESS`` packets.]]></description>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NEXT_EV</name>
|
|
<description>In ``eptri``, there are three endpoints. It is possible for an IRQ to fire and
|
|
have all three bits set. Under these circumstances it can be difficult to know
|
|
which event to process first. Use this register to determine which event needs
|
|
to be processed first. Only one bit will ever be set at a time.</description>
|
|
<addressOffset>0x0008</addressOffset>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>in</name>
|
|
<msb>0</msb>
|
|
<bitRange>[0:0]</bitRange>
|
|
<lsb>0</lsb>
|
|
<description><![CDATA[``1`` if the next event is an ``IN`` event]]></description>
|
|
</field>
|
|
<field>
|
|
<name>out</name>
|
|
<msb>1</msb>
|
|
<bitRange>[1:1]</bitRange>
|
|
<lsb>1</lsb>
|
|
<description><![CDATA[``1`` if the next event is an ``OUT`` event]]></description>
|
|
</field>
|
|
<field>
|
|
<name>setup</name>
|
|
<msb>2</msb>
|
|
<bitRange>[2:2]</bitRange>
|
|
<lsb>2</lsb>
|
|
<description><![CDATA[``1`` if the next event is an ``SETUP`` event]]></description>
|
|
</field>
|
|
<field>
|
|
<name>reset</name>
|
|
<msb>3</msb>
|
|
<bitRange>[3:3]</bitRange>
|
|
<lsb>3</lsb>
|
|
<description><![CDATA[``1`` if the next event is a ``RESET`` event]]></description>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SETUP_DATA</name>
|
|
<description>Data from the last ``SETUP`` transactions. It will be 10 bytes long, because
|
|
it will include the CRC16. This is a FIFO, and the queue is advanced
|
|
automatically.</description>
|
|
<addressOffset>0x000c</addressOffset>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>data</name>
|
|
<msb>7</msb>
|
|
<bitRange>[7:0]</bitRange>
|
|
<lsb>0</lsb>
|
|
<description><![CDATA[The next byte of ``SETUP`` data]]></description>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SETUP_CTRL</name>
|
|
<description>Controls for managing how to handle ``SETUP`` transactions.</description>
|
|
<addressOffset>0x0010</addressOffset>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>reset</name>
|
|
<msb>5</msb>
|
|
<bitRange>[5:5]</bitRange>
|
|
<lsb>5</lsb>
|
|
<description><![CDATA[Write a ``1`` here to reset the `SETUP` handler.]]></description>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SETUP_STATUS</name>
|
|
<description>Status about the most recent ``SETUP`` transactions, and the state of the FIFO.</description>
|
|
<addressOffset>0x0014</addressOffset>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>epno</name>
|
|
<msb>3</msb>
|
|
<bitRange>[3:0]</bitRange>
|
|
<lsb>0</lsb>
|
|
<description><![CDATA[The destination endpoint for the most recent SETUP token.]]></description>
|
|
</field>
|
|
<field>
|
|
<name>have</name>
|
|
<msb>4</msb>
|
|
<bitRange>[4:4]</bitRange>
|
|
<lsb>4</lsb>
|
|
<description><![CDATA[``1`` if there is data in the FIFO.]]></description>
|
|
</field>
|
|
<field>
|
|
<name>pend</name>
|
|
<msb>5</msb>
|
|
<bitRange>[5:5]</bitRange>
|
|
<lsb>5</lsb>
|
|
<description><![CDATA[``1`` if there is an IRQ pending.]]></description>
|
|
</field>
|
|
<field>
|
|
<name>is_in</name>
|
|
<msb>6</msb>
|
|
<bitRange>[6:6]</bitRange>
|
|
<lsb>6</lsb>
|
|
<description><![CDATA[``1`` if an IN stage was detected.]]></description>
|
|
</field>
|
|
<field>
|
|
<name>data</name>
|
|
<msb>7</msb>
|
|
<bitRange>[7:7]</bitRange>
|
|
<lsb>7</lsb>
|
|
<description><![CDATA[``1`` if a DATA stage is expected.]]></description>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SETUP_EV_STATUS</name>
|
|
<addressOffset>0x0018</addressOffset>
|
|
<resetValue>0x00</resetValue>
|
|
</register>
|
|
<register>
|
|
<name>SETUP_EV_PENDING</name>
|
|
<addressOffset>0x001c</addressOffset>
|
|
<resetValue>0x00</resetValue>
|
|
</register>
|
|
<register>
|
|
<name>SETUP_EV_ENABLE</name>
|
|
<addressOffset>0x0020</addressOffset>
|
|
<resetValue>0x00</resetValue>
|
|
</register>
|
|
<register>
|
|
<name>IN_DATA</name>
|
|
<description>Each byte written into this register gets added to an outgoing FIFO. Any bytes
|
|
that are written here will be transmitted in the order in which they were added.
|
|
The FIFO queue is automatically advanced with each write. The FIFO queue is 64
|
|
bytes deep. If you exceed this amount, the result is undefined.</description>
|
|
<addressOffset>0x0024</addressOffset>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>data</name>
|
|
<msb>7</msb>
|
|
<bitRange>[7:0]</bitRange>
|
|
<lsb>0</lsb>
|
|
<description><![CDATA[The next byte to add to the queue.]]></description>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IN_CTRL</name>
|
|
<description>Enables transmission of data in response to ``IN`` tokens, or resets the
|
|
contents of the FIFO.</description>
|
|
<addressOffset>0x0028</addressOffset>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>epno</name>
|
|
<msb>3</msb>
|
|
<bitRange>[3:0]</bitRange>
|
|
<lsb>0</lsb>
|
|
<description><![CDATA[The endpoint number for the transaction that is queued in the FIFO.]]></description>
|
|
</field>
|
|
<field>
|
|
<name>reset</name>
|
|
<msb>5</msb>
|
|
<bitRange>[5:5]</bitRange>
|
|
<lsb>5</lsb>
|
|
<description><![CDATA[Write a ``1`` here to clear the contents of the FIFO.]]></description>
|
|
</field>
|
|
<field>
|
|
<name>stall</name>
|
|
<msb>6</msb>
|
|
<bitRange>[6:6]</bitRange>
|
|
<lsb>6</lsb>
|
|
<description><![CDATA[Write a ``1`` here to stall the EP written in ``EP``.]]></description>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IN_STATUS</name>
|
|
<description>Status about the IN handler. As soon as you write to `IN_DATA`,
|
|
``IN_STATUS.HAVE`` should go to ``1``.</description>
|
|
<addressOffset>0x002c</addressOffset>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>idle</name>
|
|
<msb>0</msb>
|
|
<bitRange>[0:0]</bitRange>
|
|
<lsb>0</lsb>
|
|
<description><![CDATA[This value is ``1`` if the packet has finished transmitting.]]></description>
|
|
</field>
|
|
<field>
|
|
<name>have</name>
|
|
<msb>4</msb>
|
|
<bitRange>[4:4]</bitRange>
|
|
<lsb>4</lsb>
|
|
<description><![CDATA[This value is ``0`` if the FIFO is empty.]]></description>
|
|
</field>
|
|
<field>
|
|
<name>pend</name>
|
|
<msb>5</msb>
|
|
<bitRange>[5:5]</bitRange>
|
|
<lsb>5</lsb>
|
|
<description><![CDATA[``1`` if there is an IRQ pending.]]></description>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IN_EV_STATUS</name>
|
|
<addressOffset>0x0030</addressOffset>
|
|
<resetValue>0x00</resetValue>
|
|
</register>
|
|
<register>
|
|
<name>IN_EV_PENDING</name>
|
|
<addressOffset>0x0034</addressOffset>
|
|
<resetValue>0x00</resetValue>
|
|
</register>
|
|
<register>
|
|
<name>IN_EV_ENABLE</name>
|
|
<addressOffset>0x0038</addressOffset>
|
|
<resetValue>0x00</resetValue>
|
|
</register>
|
|
<register>
|
|
<name>OUT_DATA</name>
|
|
<description>Data received from the host will go into a FIFO. This register reflects the
|
|
contents of the top byte in that FIFO. Reading from this register advances the
|
|
FIFO pointer.</description>
|
|
<addressOffset>0x003c</addressOffset>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>data</name>
|
|
<msb>7</msb>
|
|
<bitRange>[7:0]</bitRange>
|
|
<lsb>0</lsb>
|
|
<description><![CDATA[The top byte of the receive FIFO.]]></description>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OUT_CTRL</name>
|
|
<description>Controls for receiving packet data. To enable an endpoint, write its value to
|
|
``epno``, with the ``enable`` bit set to ``1`` to enable an endpoint, or ``0``
|
|
to disable it. Resetting the OutHandler will set all ``enable`` bits to 0.
|
|
|
|
Similarly, you can adjust the ``STALL`` state by setting or clearing the
|
|
``stall`` bit.</description>
|
|
<addressOffset>0x0040</addressOffset>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>epno</name>
|
|
<msb>3</msb>
|
|
<bitRange>[3:0]</bitRange>
|
|
<lsb>0</lsb>
|
|
<description><![CDATA[The endpoint number to update the ``enable`` and ``status`` bits for.]]></description>
|
|
</field>
|
|
<field>
|
|
<name>enable</name>
|
|
<msb>4</msb>
|
|
<bitRange>[4:4]</bitRange>
|
|
<lsb>4</lsb>
|
|
<description><![CDATA[Write a ``1`` here to enable receiving data]]></description>
|
|
</field>
|
|
<field>
|
|
<name>reset</name>
|
|
<msb>5</msb>
|
|
<bitRange>[5:5]</bitRange>
|
|
<lsb>5</lsb>
|
|
<description><![CDATA[Write a ``1`` here to reset the ``OUT`` handler]]></description>
|
|
</field>
|
|
<field>
|
|
<name>stall</name>
|
|
<msb>6</msb>
|
|
<bitRange>[6:6]</bitRange>
|
|
<lsb>6</lsb>
|
|
<description><![CDATA[Write a ``1`` here to stall an endpoint]]></description>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OUT_STATUS</name>
|
|
<description>Status about the current state of the `OUT` endpoint.</description>
|
|
<addressOffset>0x0044</addressOffset>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>epno</name>
|
|
<msb>3</msb>
|
|
<bitRange>[3:0]</bitRange>
|
|
<lsb>0</lsb>
|
|
<description><![CDATA[The destination endpoint for the most recent ``OUT`` packet.]]></description>
|
|
</field>
|
|
<field>
|
|
<name>have</name>
|
|
<msb>4</msb>
|
|
<bitRange>[4:4]</bitRange>
|
|
<lsb>4</lsb>
|
|
<description><![CDATA[``1`` if there is data in the FIFO.]]></description>
|
|
</field>
|
|
<field>
|
|
<name>pend</name>
|
|
<msb>5</msb>
|
|
<bitRange>[5:5]</bitRange>
|
|
<lsb>5</lsb>
|
|
<description><![CDATA[``1`` if there is an IRQ pending.]]></description>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OUT_EV_STATUS</name>
|
|
<addressOffset>0x0048</addressOffset>
|
|
<resetValue>0x00</resetValue>
|
|
</register>
|
|
<register>
|
|
<name>OUT_EV_PENDING</name>
|
|
<addressOffset>0x004c</addressOffset>
|
|
<resetValue>0x00</resetValue>
|
|
</register>
|
|
<register>
|
|
<name>OUT_EV_ENABLE</name>
|
|
<addressOffset>0x0050</addressOffset>
|
|
<resetValue>0x00</resetValue>
|
|
</register>
|
|
<register>
|
|
<name>OUT_ENABLE_STATUS</name>
|
|
<addressOffset>0x0054</addressOffset>
|
|
<resetValue>0x00</resetValue>
|
|
</register>
|
|
<register>
|
|
<name>OUT_STALL_STATUS</name>
|
|
<addressOffset>0x0058</addressOffset>
|
|
<resetValue>0x00</resetValue>
|
|
</register>
|
|
</registers>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x5c</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>usb</name>
|
|
<value>3</value>
|
|
</interrupt>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>VERSION</name>
|
|
<baseAddress>0xE0007000</baseAddress>
|
|
<groupName>VERSION</groupName>
|
|
<registers>
|
|
<register>
|
|
<name>MAJOR</name>
|
|
<description>Major git tag version. For example, this firmware was built from git tag
|
|
``v2.0.1``, so this value is ``2``.</description>
|
|
<addressOffset>0x0000</addressOffset>
|
|
<resetValue>0x02</resetValue>
|
|
</register>
|
|
<register>
|
|
<name>MINOR</name>
|
|
<description>Minor git tag version. For example, this firmware was built from git tag
|
|
``v2.0.1``, so this value is ``0``.</description>
|
|
<addressOffset>0x0004</addressOffset>
|
|
<resetValue>0x00</resetValue>
|
|
</register>
|
|
<register>
|
|
<name>REVISION</name>
|
|
<description>Revision git tag version. For example, this firmware was built from git tag
|
|
``v2.0.1``, so this value is ``1``.</description>
|
|
<addressOffset>0x0008</addressOffset>
|
|
<resetValue>0x01</resetValue>
|
|
</register>
|
|
<register>
|
|
<name>GITREV3</name>
|
|
<description>Bits 24-31 of `VERSION_GITREV`. First 32-bits of the git revision. This
|
|
documentation was built from git rev ``00000000``, so this value is 0, which
|
|
should be enough to check out the exact git version used to build this firmware.</description>
|
|
<addressOffset>0x000c</addressOffset>
|
|
<resetValue>0x00</resetValue>
|
|
</register>
|
|
<register>
|
|
<name>GITREV2</name>
|
|
<description>Bits 16-23 of `VERSION_GITREV`.</description>
|
|
<addressOffset>0x0010</addressOffset>
|
|
<resetValue>0x00</resetValue>
|
|
</register>
|
|
<register>
|
|
<name>GITREV1</name>
|
|
<description>Bits 8-15 of `VERSION_GITREV`.</description>
|
|
<addressOffset>0x0014</addressOffset>
|
|
<resetValue>0x00</resetValue>
|
|
</register>
|
|
<register>
|
|
<name>GITREV0</name>
|
|
<description>Bits 0-7 of `VERSION_GITREV`.</description>
|
|
<addressOffset>0x0018</addressOffset>
|
|
<resetValue>0x00</resetValue>
|
|
</register>
|
|
<register>
|
|
<name>GITEXTRA1</name>
|
|
<description>Bits 8-9 of `VERSION_GITEXTRA`. The number of additional commits beyond the git
|
|
tag. For example, if this value is ``1``, then the repository this was built
|
|
from has one additional commit beyond the tag indicated in `MAJOR`, `MINOR`, and
|
|
`REVISION`.</description>
|
|
<addressOffset>0x001c</addressOffset>
|
|
<resetValue>0x00</resetValue>
|
|
</register>
|
|
<register>
|
|
<name>GITEXTRA0</name>
|
|
<description>Bits 0-7 of `VERSION_GITEXTRA`.</description>
|
|
<addressOffset>0x0020</addressOffset>
|
|
<resetValue>0x01</resetValue>
|
|
</register>
|
|
<register>
|
|
<name>DIRTY</name>
|
|
<addressOffset>0x0024</addressOffset>
|
|
<resetValue>0x01</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>dirty</name>
|
|
<msb>0</msb>
|
|
<bitRange>[0:0]</bitRange>
|
|
<lsb>0</lsb>
|
|
<description><![CDATA[Set to ``1`` if this device was built from a git repo with uncommitted
|
|
modifications.]]></description>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MODEL</name>
|
|
<addressOffset>0x0028</addressOffset>
|
|
<resetValue>0x50</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>model</name>
|
|
<msb>7</msb>
|
|
<bitRange>[7:0]</bitRange>
|
|
<lsb>0</lsb>
|
|
<description><![CDATA[Contains information on which model device this was built for.]]></description>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SEED3</name>
|
|
<description>Bits 24-31 of `VERSION_SEED`. 32-bit seed used for the place-and-route.</description>
|
|
<addressOffset>0x002c</addressOffset>
|
|
<resetValue>0x00</resetValue>
|
|
</register>
|
|
<register>
|
|
<name>SEED2</name>
|
|
<description>Bits 16-23 of `VERSION_SEED`.</description>
|
|
<addressOffset>0x0030</addressOffset>
|
|
<resetValue>0x00</resetValue>
|
|
</register>
|
|
<register>
|
|
<name>SEED1</name>
|
|
<description>Bits 8-15 of `VERSION_SEED`.</description>
|
|
<addressOffset>0x0034</addressOffset>
|
|
<resetValue>0x00</resetValue>
|
|
</register>
|
|
<register>
|
|
<name>SEED0</name>
|
|
<description>Bits 0-7 of `VERSION_SEED`.</description>
|
|
<addressOffset>0x0038</addressOffset>
|
|
<resetValue>0x03</resetValue>
|
|
</register>
|
|
</registers>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x3c</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
</peripheral>
|
|
</peripherals>
|
|
</device>
|