mirror of
https://github.com/im-tomu/foboot.git
synced 2024-09-20 02:40:09 +00:00
6abbd84ec5
This adds release v2.0.4 to the build. This version fixes the wraparound issue. Signed-off-by: Sean Cross <sean@xobs.io>
587 lines
19 KiB
C
587 lines
19 KiB
C
//--------------------------------------------------------------------------------
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// Auto-generated by Migen (b1b2b29) & LiteX (4f82a36a) on 2021-11-25 10:25:09
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//--------------------------------------------------------------------------------
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#include <generated/soc.h>
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#ifndef __GENERATED_CSR_H
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#define __GENERATED_CSR_H
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#include <stdint.h>
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#include <system.h>
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#ifndef CSR_ACCESSORS_DEFINED
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#include <hw/common.h>
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#endif /* ! CSR_ACCESSORS_DEFINED */
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#ifndef CSR_BASE
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#define CSR_BASE 0xe0000000L
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#endif
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/* ctrl */
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#define CSR_CTRL_BASE (CSR_BASE + 0x0L)
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#define CSR_CTRL_RESET_ADDR (CSR_BASE + 0x0L)
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#define CSR_CTRL_RESET_SIZE 1
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static inline uint8_t ctrl_reset_read(void) {
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return csr_read_simple(CSR_BASE + 0x0L);
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}
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static inline void ctrl_reset_write(uint8_t v) {
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csr_write_simple(v, CSR_BASE + 0x0L);
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}
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#define CSR_CTRL_SCRATCH_ADDR (CSR_BASE + 0x4L)
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#define CSR_CTRL_SCRATCH_SIZE 4
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static inline uint32_t ctrl_scratch_read(void) {
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uint32_t r = csr_read_simple(CSR_BASE + 0x4L);
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r <<= 8;
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r |= csr_read_simple(CSR_BASE + 0x8L);
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r <<= 8;
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r |= csr_read_simple(CSR_BASE + 0xcL);
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r <<= 8;
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r |= csr_read_simple(CSR_BASE + 0x10L);
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return r;
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}
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static inline void ctrl_scratch_write(uint32_t v) {
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csr_write_simple(v >> 24, CSR_BASE + 0x4L);
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csr_write_simple(v >> 16, CSR_BASE + 0x8L);
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csr_write_simple(v >> 8, CSR_BASE + 0xcL);
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csr_write_simple(v, CSR_BASE + 0x10L);
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}
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#define CSR_CTRL_BUS_ERRORS_ADDR (CSR_BASE + 0x14L)
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#define CSR_CTRL_BUS_ERRORS_SIZE 4
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static inline uint32_t ctrl_bus_errors_read(void) {
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uint32_t r = csr_read_simple(CSR_BASE + 0x14L);
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r <<= 8;
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r |= csr_read_simple(CSR_BASE + 0x18L);
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r <<= 8;
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r |= csr_read_simple(CSR_BASE + 0x1cL);
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r <<= 8;
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r |= csr_read_simple(CSR_BASE + 0x20L);
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return r;
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}
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/* timer0 */
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#define CSR_TIMER0_BASE (CSR_BASE + 0x2800L)
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#define CSR_TIMER0_LOAD_ADDR (CSR_BASE + 0x2800L)
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#define CSR_TIMER0_LOAD_SIZE 4
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static inline uint32_t timer0_load_read(void) {
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uint32_t r = csr_read_simple(CSR_BASE + 0x2800L);
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r <<= 8;
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r |= csr_read_simple(CSR_BASE + 0x2804L);
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r <<= 8;
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r |= csr_read_simple(CSR_BASE + 0x2808L);
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r <<= 8;
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r |= csr_read_simple(CSR_BASE + 0x280cL);
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return r;
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}
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static inline void timer0_load_write(uint32_t v) {
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csr_write_simple(v >> 24, CSR_BASE + 0x2800L);
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csr_write_simple(v >> 16, CSR_BASE + 0x2804L);
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csr_write_simple(v >> 8, CSR_BASE + 0x2808L);
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csr_write_simple(v, CSR_BASE + 0x280cL);
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}
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#define CSR_TIMER0_RELOAD_ADDR (CSR_BASE + 0x2810L)
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#define CSR_TIMER0_RELOAD_SIZE 4
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static inline uint32_t timer0_reload_read(void) {
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uint32_t r = csr_read_simple(CSR_BASE + 0x2810L);
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r <<= 8;
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r |= csr_read_simple(CSR_BASE + 0x2814L);
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r <<= 8;
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r |= csr_read_simple(CSR_BASE + 0x2818L);
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r <<= 8;
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r |= csr_read_simple(CSR_BASE + 0x281cL);
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return r;
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}
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static inline void timer0_reload_write(uint32_t v) {
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csr_write_simple(v >> 24, CSR_BASE + 0x2810L);
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csr_write_simple(v >> 16, CSR_BASE + 0x2814L);
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csr_write_simple(v >> 8, CSR_BASE + 0x2818L);
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csr_write_simple(v, CSR_BASE + 0x281cL);
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}
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#define CSR_TIMER0_EN_ADDR (CSR_BASE + 0x2820L)
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#define CSR_TIMER0_EN_SIZE 1
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static inline uint8_t timer0_en_read(void) {
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return csr_read_simple(CSR_BASE + 0x2820L);
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}
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static inline void timer0_en_write(uint8_t v) {
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csr_write_simple(v, CSR_BASE + 0x2820L);
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}
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#define CSR_TIMER0_UPDATE_VALUE_ADDR (CSR_BASE + 0x2824L)
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#define CSR_TIMER0_UPDATE_VALUE_SIZE 1
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static inline uint8_t timer0_update_value_read(void) {
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return csr_read_simple(CSR_BASE + 0x2824L);
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}
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static inline void timer0_update_value_write(uint8_t v) {
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csr_write_simple(v, CSR_BASE + 0x2824L);
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}
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#define CSR_TIMER0_VALUE_ADDR (CSR_BASE + 0x2828L)
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#define CSR_TIMER0_VALUE_SIZE 4
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static inline uint32_t timer0_value_read(void) {
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uint32_t r = csr_read_simple(CSR_BASE + 0x2828L);
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r <<= 8;
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r |= csr_read_simple(CSR_BASE + 0x282cL);
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r <<= 8;
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r |= csr_read_simple(CSR_BASE + 0x2830L);
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r <<= 8;
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r |= csr_read_simple(CSR_BASE + 0x2834L);
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return r;
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}
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#define CSR_TIMER0_EV_STATUS_ADDR (CSR_BASE + 0x2838L)
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#define CSR_TIMER0_EV_STATUS_SIZE 1
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static inline uint8_t timer0_ev_status_read(void) {
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return csr_read_simple(CSR_BASE + 0x2838L);
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}
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static inline void timer0_ev_status_write(uint8_t v) {
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csr_write_simple(v, CSR_BASE + 0x2838L);
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}
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#define CSR_TIMER0_EV_PENDING_ADDR (CSR_BASE + 0x283cL)
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#define CSR_TIMER0_EV_PENDING_SIZE 1
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static inline uint8_t timer0_ev_pending_read(void) {
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return csr_read_simple(CSR_BASE + 0x283cL);
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}
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static inline void timer0_ev_pending_write(uint8_t v) {
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csr_write_simple(v, CSR_BASE + 0x283cL);
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}
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#define CSR_TIMER0_EV_ENABLE_ADDR (CSR_BASE + 0x2840L)
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#define CSR_TIMER0_EV_ENABLE_SIZE 1
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static inline uint8_t timer0_ev_enable_read(void) {
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return csr_read_simple(CSR_BASE + 0x2840L);
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}
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static inline void timer0_ev_enable_write(uint8_t v) {
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csr_write_simple(v, CSR_BASE + 0x2840L);
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}
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/* usb */
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#define CSR_USB_BASE (CSR_BASE + 0x4800L)
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#define CSR_USB_PULLUP_OUT_ADDR (CSR_BASE + 0x4800L)
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#define CSR_USB_PULLUP_OUT_SIZE 1
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static inline uint8_t usb_pullup_out_read(void) {
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return csr_read_simple(CSR_BASE + 0x4800L);
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}
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static inline void usb_pullup_out_write(uint8_t v) {
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csr_write_simple(v, CSR_BASE + 0x4800L);
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}
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#define CSR_USB_ADDRESS_ADDR (CSR_BASE + 0x4804L)
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#define CSR_USB_ADDRESS_SIZE 1
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static inline uint8_t usb_address_read(void) {
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return csr_read_simple(CSR_BASE + 0x4804L);
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}
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static inline void usb_address_write(uint8_t v) {
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csr_write_simple(v, CSR_BASE + 0x4804L);
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}
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#define CSR_USB_ADDRESS_ADDR_OFFSET 0
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#define CSR_USB_ADDRESS_ADDR_SIZE 7
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#define CSR_USB_NEXT_EV_ADDR (CSR_BASE + 0x4808L)
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#define CSR_USB_NEXT_EV_SIZE 1
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static inline uint8_t usb_next_ev_read(void) {
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return csr_read_simple(CSR_BASE + 0x4808L);
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}
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#define CSR_USB_NEXT_EV_IN_OFFSET 0
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#define CSR_USB_NEXT_EV_IN_SIZE 1
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#define CSR_USB_NEXT_EV_OUT_OFFSET 1
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#define CSR_USB_NEXT_EV_OUT_SIZE 1
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#define CSR_USB_NEXT_EV_SETUP_OFFSET 2
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#define CSR_USB_NEXT_EV_SETUP_SIZE 1
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#define CSR_USB_NEXT_EV_RESET_OFFSET 3
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#define CSR_USB_NEXT_EV_RESET_SIZE 1
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#define CSR_USB_SETUP_DATA_ADDR (CSR_BASE + 0x480cL)
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#define CSR_USB_SETUP_DATA_SIZE 1
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static inline uint8_t usb_setup_data_read(void) {
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return csr_read_simple(CSR_BASE + 0x480cL);
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}
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#define CSR_USB_SETUP_DATA_DATA_OFFSET 0
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#define CSR_USB_SETUP_DATA_DATA_SIZE 8
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#define CSR_USB_SETUP_CTRL_ADDR (CSR_BASE + 0x4810L)
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#define CSR_USB_SETUP_CTRL_SIZE 1
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static inline uint8_t usb_setup_ctrl_read(void) {
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return csr_read_simple(CSR_BASE + 0x4810L);
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}
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static inline void usb_setup_ctrl_write(uint8_t v) {
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csr_write_simple(v, CSR_BASE + 0x4810L);
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}
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#define CSR_USB_SETUP_CTRL_RESET_OFFSET 5
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#define CSR_USB_SETUP_CTRL_RESET_SIZE 1
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#define CSR_USB_SETUP_STATUS_ADDR (CSR_BASE + 0x4814L)
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#define CSR_USB_SETUP_STATUS_SIZE 1
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static inline uint8_t usb_setup_status_read(void) {
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return csr_read_simple(CSR_BASE + 0x4814L);
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}
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#define CSR_USB_SETUP_STATUS_EPNO_OFFSET 0
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#define CSR_USB_SETUP_STATUS_EPNO_SIZE 4
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#define CSR_USB_SETUP_STATUS_HAVE_OFFSET 4
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#define CSR_USB_SETUP_STATUS_HAVE_SIZE 1
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#define CSR_USB_SETUP_STATUS_PEND_OFFSET 5
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#define CSR_USB_SETUP_STATUS_PEND_SIZE 1
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#define CSR_USB_SETUP_STATUS_IS_IN_OFFSET 6
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#define CSR_USB_SETUP_STATUS_IS_IN_SIZE 1
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#define CSR_USB_SETUP_STATUS_DATA_OFFSET 7
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#define CSR_USB_SETUP_STATUS_DATA_SIZE 1
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#define CSR_USB_SETUP_EV_STATUS_ADDR (CSR_BASE + 0x4818L)
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#define CSR_USB_SETUP_EV_STATUS_SIZE 1
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static inline uint8_t usb_setup_ev_status_read(void) {
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return csr_read_simple(CSR_BASE + 0x4818L);
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}
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static inline void usb_setup_ev_status_write(uint8_t v) {
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csr_write_simple(v, CSR_BASE + 0x4818L);
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}
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#define CSR_USB_SETUP_EV_PENDING_ADDR (CSR_BASE + 0x481cL)
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#define CSR_USB_SETUP_EV_PENDING_SIZE 1
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static inline uint8_t usb_setup_ev_pending_read(void) {
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return csr_read_simple(CSR_BASE + 0x481cL);
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}
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static inline void usb_setup_ev_pending_write(uint8_t v) {
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csr_write_simple(v, CSR_BASE + 0x481cL);
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}
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#define CSR_USB_SETUP_EV_ENABLE_ADDR (CSR_BASE + 0x4820L)
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#define CSR_USB_SETUP_EV_ENABLE_SIZE 1
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static inline uint8_t usb_setup_ev_enable_read(void) {
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return csr_read_simple(CSR_BASE + 0x4820L);
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}
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static inline void usb_setup_ev_enable_write(uint8_t v) {
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csr_write_simple(v, CSR_BASE + 0x4820L);
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}
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#define CSR_USB_IN_DATA_ADDR (CSR_BASE + 0x4824L)
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#define CSR_USB_IN_DATA_SIZE 1
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static inline uint8_t usb_in_data_read(void) {
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return csr_read_simple(CSR_BASE + 0x4824L);
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}
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static inline void usb_in_data_write(uint8_t v) {
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csr_write_simple(v, CSR_BASE + 0x4824L);
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}
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#define CSR_USB_IN_DATA_DATA_OFFSET 0
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#define CSR_USB_IN_DATA_DATA_SIZE 8
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#define CSR_USB_IN_CTRL_ADDR (CSR_BASE + 0x4828L)
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#define CSR_USB_IN_CTRL_SIZE 1
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static inline uint8_t usb_in_ctrl_read(void) {
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return csr_read_simple(CSR_BASE + 0x4828L);
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}
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static inline void usb_in_ctrl_write(uint8_t v) {
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csr_write_simple(v, CSR_BASE + 0x4828L);
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}
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#define CSR_USB_IN_CTRL_EPNO_OFFSET 0
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#define CSR_USB_IN_CTRL_EPNO_SIZE 4
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#define CSR_USB_IN_CTRL_RESET_OFFSET 5
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#define CSR_USB_IN_CTRL_RESET_SIZE 1
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#define CSR_USB_IN_CTRL_STALL_OFFSET 6
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#define CSR_USB_IN_CTRL_STALL_SIZE 1
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#define CSR_USB_IN_STATUS_ADDR (CSR_BASE + 0x482cL)
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#define CSR_USB_IN_STATUS_SIZE 1
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static inline uint8_t usb_in_status_read(void) {
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return csr_read_simple(CSR_BASE + 0x482cL);
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}
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#define CSR_USB_IN_STATUS_IDLE_OFFSET 0
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#define CSR_USB_IN_STATUS_IDLE_SIZE 1
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#define CSR_USB_IN_STATUS_HAVE_OFFSET 4
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#define CSR_USB_IN_STATUS_HAVE_SIZE 1
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#define CSR_USB_IN_STATUS_PEND_OFFSET 5
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#define CSR_USB_IN_STATUS_PEND_SIZE 1
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#define CSR_USB_IN_EV_STATUS_ADDR (CSR_BASE + 0x4830L)
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#define CSR_USB_IN_EV_STATUS_SIZE 1
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static inline uint8_t usb_in_ev_status_read(void) {
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return csr_read_simple(CSR_BASE + 0x4830L);
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}
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static inline void usb_in_ev_status_write(uint8_t v) {
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csr_write_simple(v, CSR_BASE + 0x4830L);
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}
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#define CSR_USB_IN_EV_PENDING_ADDR (CSR_BASE + 0x4834L)
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#define CSR_USB_IN_EV_PENDING_SIZE 1
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static inline uint8_t usb_in_ev_pending_read(void) {
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return csr_read_simple(CSR_BASE + 0x4834L);
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}
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static inline void usb_in_ev_pending_write(uint8_t v) {
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csr_write_simple(v, CSR_BASE + 0x4834L);
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}
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#define CSR_USB_IN_EV_ENABLE_ADDR (CSR_BASE + 0x4838L)
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#define CSR_USB_IN_EV_ENABLE_SIZE 1
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static inline uint8_t usb_in_ev_enable_read(void) {
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return csr_read_simple(CSR_BASE + 0x4838L);
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}
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static inline void usb_in_ev_enable_write(uint8_t v) {
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csr_write_simple(v, CSR_BASE + 0x4838L);
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}
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#define CSR_USB_OUT_DATA_ADDR (CSR_BASE + 0x483cL)
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#define CSR_USB_OUT_DATA_SIZE 1
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static inline uint8_t usb_out_data_read(void) {
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return csr_read_simple(CSR_BASE + 0x483cL);
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}
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#define CSR_USB_OUT_DATA_DATA_OFFSET 0
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#define CSR_USB_OUT_DATA_DATA_SIZE 8
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#define CSR_USB_OUT_CTRL_ADDR (CSR_BASE + 0x4840L)
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#define CSR_USB_OUT_CTRL_SIZE 1
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static inline uint8_t usb_out_ctrl_read(void) {
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return csr_read_simple(CSR_BASE + 0x4840L);
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}
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static inline void usb_out_ctrl_write(uint8_t v) {
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csr_write_simple(v, CSR_BASE + 0x4840L);
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}
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#define CSR_USB_OUT_CTRL_EPNO_OFFSET 0
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#define CSR_USB_OUT_CTRL_EPNO_SIZE 4
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#define CSR_USB_OUT_CTRL_ENABLE_OFFSET 4
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#define CSR_USB_OUT_CTRL_ENABLE_SIZE 1
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#define CSR_USB_OUT_CTRL_RESET_OFFSET 5
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#define CSR_USB_OUT_CTRL_RESET_SIZE 1
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#define CSR_USB_OUT_CTRL_STALL_OFFSET 6
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#define CSR_USB_OUT_CTRL_STALL_SIZE 1
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#define CSR_USB_OUT_STATUS_ADDR (CSR_BASE + 0x4844L)
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#define CSR_USB_OUT_STATUS_SIZE 1
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static inline uint8_t usb_out_status_read(void) {
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return csr_read_simple(CSR_BASE + 0x4844L);
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}
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#define CSR_USB_OUT_STATUS_EPNO_OFFSET 0
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#define CSR_USB_OUT_STATUS_EPNO_SIZE 4
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#define CSR_USB_OUT_STATUS_HAVE_OFFSET 4
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#define CSR_USB_OUT_STATUS_HAVE_SIZE 1
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#define CSR_USB_OUT_STATUS_PEND_OFFSET 5
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#define CSR_USB_OUT_STATUS_PEND_SIZE 1
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#define CSR_USB_OUT_EV_STATUS_ADDR (CSR_BASE + 0x4848L)
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#define CSR_USB_OUT_EV_STATUS_SIZE 1
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static inline uint8_t usb_out_ev_status_read(void) {
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return csr_read_simple(CSR_BASE + 0x4848L);
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}
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static inline void usb_out_ev_status_write(uint8_t v) {
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csr_write_simple(v, CSR_BASE + 0x4848L);
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}
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#define CSR_USB_OUT_EV_PENDING_ADDR (CSR_BASE + 0x484cL)
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#define CSR_USB_OUT_EV_PENDING_SIZE 1
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static inline uint8_t usb_out_ev_pending_read(void) {
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return csr_read_simple(CSR_BASE + 0x484cL);
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}
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static inline void usb_out_ev_pending_write(uint8_t v) {
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csr_write_simple(v, CSR_BASE + 0x484cL);
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}
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#define CSR_USB_OUT_EV_ENABLE_ADDR (CSR_BASE + 0x4850L)
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#define CSR_USB_OUT_EV_ENABLE_SIZE 1
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static inline uint8_t usb_out_ev_enable_read(void) {
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return csr_read_simple(CSR_BASE + 0x4850L);
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}
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static inline void usb_out_ev_enable_write(uint8_t v) {
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csr_write_simple(v, CSR_BASE + 0x4850L);
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}
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/* touch */
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#define CSR_TOUCH_BASE (CSR_BASE + 0x5800L)
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#define CSR_TOUCH_O_ADDR (CSR_BASE + 0x5800L)
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#define CSR_TOUCH_O_SIZE 1
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static inline uint8_t touch_o_read(void) {
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return csr_read_simple(CSR_BASE + 0x5800L);
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}
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static inline void touch_o_write(uint8_t v) {
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csr_write_simple(v, CSR_BASE + 0x5800L);
|
|
}
|
|
#define CSR_TOUCH_OE_ADDR (CSR_BASE + 0x5804L)
|
|
#define CSR_TOUCH_OE_SIZE 1
|
|
static inline uint8_t touch_oe_read(void) {
|
|
return csr_read_simple(CSR_BASE + 0x5804L);
|
|
}
|
|
static inline void touch_oe_write(uint8_t v) {
|
|
csr_write_simple(v, CSR_BASE + 0x5804L);
|
|
}
|
|
#define CSR_TOUCH_I_ADDR (CSR_BASE + 0x5808L)
|
|
#define CSR_TOUCH_I_SIZE 1
|
|
static inline uint8_t touch_i_read(void) {
|
|
return csr_read_simple(CSR_BASE + 0x5808L);
|
|
}
|
|
|
|
/* reboot */
|
|
#define CSR_REBOOT_BASE (CSR_BASE + 0x6000L)
|
|
#define CSR_REBOOT_CTRL_ADDR (CSR_BASE + 0x6000L)
|
|
#define CSR_REBOOT_CTRL_SIZE 1
|
|
static inline uint8_t reboot_ctrl_read(void) {
|
|
return csr_read_simple(CSR_BASE + 0x6000L);
|
|
}
|
|
static inline void reboot_ctrl_write(uint8_t v) {
|
|
csr_write_simple(v, CSR_BASE + 0x6000L);
|
|
}
|
|
#define CSR_REBOOT_CTRL_IMAGE_OFFSET 0
|
|
#define CSR_REBOOT_CTRL_IMAGE_SIZE 2
|
|
#define CSR_REBOOT_CTRL_KEY_OFFSET 2
|
|
#define CSR_REBOOT_CTRL_KEY_SIZE 6
|
|
#define CSR_REBOOT_ADDR_ADDR (CSR_BASE + 0x6004L)
|
|
#define CSR_REBOOT_ADDR_SIZE 4
|
|
static inline uint32_t reboot_addr_read(void) {
|
|
uint32_t r = csr_read_simple(CSR_BASE + 0x6004L);
|
|
r <<= 8;
|
|
r |= csr_read_simple(CSR_BASE + 0x6008L);
|
|
r <<= 8;
|
|
r |= csr_read_simple(CSR_BASE + 0x600cL);
|
|
r <<= 8;
|
|
r |= csr_read_simple(CSR_BASE + 0x6010L);
|
|
return r;
|
|
}
|
|
static inline void reboot_addr_write(uint32_t v) {
|
|
csr_write_simple(v >> 24, CSR_BASE + 0x6004L);
|
|
csr_write_simple(v >> 16, CSR_BASE + 0x6008L);
|
|
csr_write_simple(v >> 8, CSR_BASE + 0x600cL);
|
|
csr_write_simple(v, CSR_BASE + 0x6010L);
|
|
}
|
|
|
|
/* rgb */
|
|
#define CSR_RGB_BASE (CSR_BASE + 0x6800L)
|
|
#define CSR_RGB_DAT_ADDR (CSR_BASE + 0x6800L)
|
|
#define CSR_RGB_DAT_SIZE 1
|
|
static inline uint8_t rgb_dat_read(void) {
|
|
return csr_read_simple(CSR_BASE + 0x6800L);
|
|
}
|
|
static inline void rgb_dat_write(uint8_t v) {
|
|
csr_write_simple(v, CSR_BASE + 0x6800L);
|
|
}
|
|
#define CSR_RGB_ADDR_ADDR (CSR_BASE + 0x6804L)
|
|
#define CSR_RGB_ADDR_SIZE 1
|
|
static inline uint8_t rgb_addr_read(void) {
|
|
return csr_read_simple(CSR_BASE + 0x6804L);
|
|
}
|
|
static inline void rgb_addr_write(uint8_t v) {
|
|
csr_write_simple(v, CSR_BASE + 0x6804L);
|
|
}
|
|
#define CSR_RGB_CTRL_ADDR (CSR_BASE + 0x6808L)
|
|
#define CSR_RGB_CTRL_SIZE 1
|
|
static inline uint8_t rgb_ctrl_read(void) {
|
|
return csr_read_simple(CSR_BASE + 0x6808L);
|
|
}
|
|
static inline void rgb_ctrl_write(uint8_t v) {
|
|
csr_write_simple(v, CSR_BASE + 0x6808L);
|
|
}
|
|
#define CSR_RGB_CTRL_EXE_OFFSET 0
|
|
#define CSR_RGB_CTRL_EXE_SIZE 1
|
|
#define CSR_RGB_CTRL_CURREN_OFFSET 1
|
|
#define CSR_RGB_CTRL_CURREN_SIZE 1
|
|
#define CSR_RGB_CTRL_RGBLEDEN_OFFSET 2
|
|
#define CSR_RGB_CTRL_RGBLEDEN_SIZE 1
|
|
#define CSR_RGB_CTRL_RRAW_OFFSET 3
|
|
#define CSR_RGB_CTRL_RRAW_SIZE 1
|
|
#define CSR_RGB_CTRL_GRAW_OFFSET 4
|
|
#define CSR_RGB_CTRL_GRAW_SIZE 1
|
|
#define CSR_RGB_CTRL_BRAW_OFFSET 5
|
|
#define CSR_RGB_CTRL_BRAW_SIZE 1
|
|
#define CSR_RGB_RAW_ADDR (CSR_BASE + 0x680cL)
|
|
#define CSR_RGB_RAW_SIZE 1
|
|
static inline uint8_t rgb_raw_read(void) {
|
|
return csr_read_simple(CSR_BASE + 0x680cL);
|
|
}
|
|
static inline void rgb_raw_write(uint8_t v) {
|
|
csr_write_simple(v, CSR_BASE + 0x680cL);
|
|
}
|
|
#define CSR_RGB_RAW_R_OFFSET 0
|
|
#define CSR_RGB_RAW_R_SIZE 1
|
|
#define CSR_RGB_RAW_G_OFFSET 1
|
|
#define CSR_RGB_RAW_G_SIZE 1
|
|
#define CSR_RGB_RAW_B_OFFSET 2
|
|
#define CSR_RGB_RAW_B_SIZE 1
|
|
|
|
/* version */
|
|
#define CSR_VERSION_BASE (CSR_BASE + 0x7000L)
|
|
#define CSR_VERSION_MAJOR_ADDR (CSR_BASE + 0x7000L)
|
|
#define CSR_VERSION_MAJOR_SIZE 1
|
|
static inline uint8_t version_major_read(void) {
|
|
return csr_read_simple(CSR_BASE + 0x7000L);
|
|
}
|
|
#define CSR_VERSION_MINOR_ADDR (CSR_BASE + 0x7004L)
|
|
#define CSR_VERSION_MINOR_SIZE 1
|
|
static inline uint8_t version_minor_read(void) {
|
|
return csr_read_simple(CSR_BASE + 0x7004L);
|
|
}
|
|
#define CSR_VERSION_REVISION_ADDR (CSR_BASE + 0x7008L)
|
|
#define CSR_VERSION_REVISION_SIZE 1
|
|
static inline uint8_t version_revision_read(void) {
|
|
return csr_read_simple(CSR_BASE + 0x7008L);
|
|
}
|
|
#define CSR_VERSION_GITREV_ADDR (CSR_BASE + 0x700cL)
|
|
#define CSR_VERSION_GITREV_SIZE 4
|
|
static inline uint32_t version_gitrev_read(void) {
|
|
uint32_t r = csr_read_simple(CSR_BASE + 0x700cL);
|
|
r <<= 8;
|
|
r |= csr_read_simple(CSR_BASE + 0x7010L);
|
|
r <<= 8;
|
|
r |= csr_read_simple(CSR_BASE + 0x7014L);
|
|
r <<= 8;
|
|
r |= csr_read_simple(CSR_BASE + 0x7018L);
|
|
return r;
|
|
}
|
|
#define CSR_VERSION_GITEXTRA_ADDR (CSR_BASE + 0x701cL)
|
|
#define CSR_VERSION_GITEXTRA_SIZE 2
|
|
static inline uint16_t version_gitextra_read(void) {
|
|
uint16_t r = csr_read_simple(CSR_BASE + 0x701cL);
|
|
r <<= 8;
|
|
r |= csr_read_simple(CSR_BASE + 0x7020L);
|
|
return r;
|
|
}
|
|
#define CSR_VERSION_DIRTY_ADDR (CSR_BASE + 0x7024L)
|
|
#define CSR_VERSION_DIRTY_SIZE 1
|
|
static inline uint8_t version_dirty_read(void) {
|
|
return csr_read_simple(CSR_BASE + 0x7024L);
|
|
}
|
|
#define CSR_VERSION_DIRTY_DIRTY_OFFSET 0
|
|
#define CSR_VERSION_DIRTY_DIRTY_SIZE 1
|
|
#define CSR_VERSION_MODEL_ADDR (CSR_BASE + 0x7028L)
|
|
#define CSR_VERSION_MODEL_SIZE 1
|
|
static inline uint8_t version_model_read(void) {
|
|
return csr_read_simple(CSR_BASE + 0x7028L);
|
|
}
|
|
#define CSR_VERSION_MODEL_MODEL_OFFSET 0
|
|
#define CSR_VERSION_MODEL_MODEL_SIZE 8
|
|
#define CSR_VERSION_SEED_ADDR (CSR_BASE + 0x702cL)
|
|
#define CSR_VERSION_SEED_SIZE 4
|
|
static inline uint32_t version_seed_read(void) {
|
|
uint32_t r = csr_read_simple(CSR_BASE + 0x702cL);
|
|
r <<= 8;
|
|
r |= csr_read_simple(CSR_BASE + 0x7030L);
|
|
r <<= 8;
|
|
r |= csr_read_simple(CSR_BASE + 0x7034L);
|
|
r <<= 8;
|
|
r |= csr_read_simple(CSR_BASE + 0x7038L);
|
|
return r;
|
|
}
|
|
|
|
/* lxspi */
|
|
#define CSR_LXSPI_BASE (CSR_BASE + 0x7800L)
|
|
#define CSR_LXSPI_BITBANG_ADDR (CSR_BASE + 0x7800L)
|
|
#define CSR_LXSPI_BITBANG_SIZE 1
|
|
static inline uint8_t lxspi_bitbang_read(void) {
|
|
return csr_read_simple(CSR_BASE + 0x7800L);
|
|
}
|
|
static inline void lxspi_bitbang_write(uint8_t v) {
|
|
csr_write_simple(v, CSR_BASE + 0x7800L);
|
|
}
|
|
#define CSR_LXSPI_BITBANG_MOSI_OFFSET 0
|
|
#define CSR_LXSPI_BITBANG_MOSI_SIZE 1
|
|
#define CSR_LXSPI_BITBANG_CLK_OFFSET 1
|
|
#define CSR_LXSPI_BITBANG_CLK_SIZE 1
|
|
#define CSR_LXSPI_BITBANG_CS_N_OFFSET 2
|
|
#define CSR_LXSPI_BITBANG_CS_N_SIZE 1
|
|
#define CSR_LXSPI_BITBANG_DIR_OFFSET 3
|
|
#define CSR_LXSPI_BITBANG_DIR_SIZE 1
|
|
#define CSR_LXSPI_MISO_ADDR (CSR_BASE + 0x7804L)
|
|
#define CSR_LXSPI_MISO_SIZE 1
|
|
static inline uint8_t lxspi_miso_read(void) {
|
|
return csr_read_simple(CSR_BASE + 0x7804L);
|
|
}
|
|
#define CSR_LXSPI_BITBANG_EN_ADDR (CSR_BASE + 0x7808L)
|
|
#define CSR_LXSPI_BITBANG_EN_SIZE 1
|
|
static inline uint8_t lxspi_bitbang_en_read(void) {
|
|
return csr_read_simple(CSR_BASE + 0x7808L);
|
|
}
|
|
static inline void lxspi_bitbang_en_write(uint8_t v) {
|
|
csr_write_simple(v, CSR_BASE + 0x7808L);
|
|
}
|
|
|
|
/* messible */
|
|
#define CSR_MESSIBLE_BASE (CSR_BASE + 0x8000L)
|
|
#define CSR_MESSIBLE_IN_ADDR (CSR_BASE + 0x8000L)
|
|
#define CSR_MESSIBLE_IN_SIZE 1
|
|
static inline uint8_t messible_in_read(void) {
|
|
return csr_read_simple(CSR_BASE + 0x8000L);
|
|
}
|
|
static inline void messible_in_write(uint8_t v) {
|
|
csr_write_simple(v, CSR_BASE + 0x8000L);
|
|
}
|
|
#define CSR_MESSIBLE_OUT_ADDR (CSR_BASE + 0x8004L)
|
|
#define CSR_MESSIBLE_OUT_SIZE 1
|
|
static inline uint8_t messible_out_read(void) {
|
|
return csr_read_simple(CSR_BASE + 0x8004L);
|
|
}
|
|
#define CSR_MESSIBLE_STATUS_ADDR (CSR_BASE + 0x8008L)
|
|
#define CSR_MESSIBLE_STATUS_SIZE 1
|
|
static inline uint8_t messible_status_read(void) {
|
|
return csr_read_simple(CSR_BASE + 0x8008L);
|
|
}
|
|
#define CSR_MESSIBLE_STATUS_FULL_OFFSET 0
|
|
#define CSR_MESSIBLE_STATUS_FULL_SIZE 1
|
|
#define CSR_MESSIBLE_STATUS_HAVE_OFFSET 1
|
|
#define CSR_MESSIBLE_STATUS_HAVE_SIZE 1
|
|
|
|
#endif
|