Hi, I'm Fomu! This workshop covers the basics of Fomu in a top-down approach. We'll start out by learning what Fomu is, how to load software into Fomu, and finally how to write software for Fomu.
FPGAs are complex, weird things, so we'll take a gentle approach and start out by treating it like a Python interpreter first, and gradually peel away layers until we're writing our own hardware registers. You can take a break at any time and explore! Stop when you feel the concepts are too unfamiliar, or plough on and dig deep into the world of hardware.
You will need the Workshop files. They are located in the [fomu-workshop](https://github.com/im-tomu/fomu-workshop) Github repository. You can download [master.zip](https://github.com/im-tomu/fomu-workshop/archive/master.zip) or clone it from git:
Fomu requires specialized software. This software is provided for Linux x86/64, macOS, and Windows, via [Fomu Toolchain](https://github.com/im-tomu/fomu-toolchain/releases/latest).
Debian packages are also [available for Raspberry Pi](https://github.com/im-tomu/fomu-raspbian-packages).
For this workshop, you will need a Fomu board. This workshop may be competed with any model of Fomu, though there are some parts that require you to identify which model you have:
1.**Fomu EVT3**: This model of Fomu is about the size of a credit card. It should have the text "Fomu EVT3" written across it in white silkscreen. If you have a different EVT board such as EVT2 or EVT1, they should work also.
1.**Fomu PVT1**: If you ordered a Fomu from Crowd Supply, this is the model you'll receive. It is small, and fits in a USB port. There is no silkscreen on it. This model of Fomu has a large silver crystal oscillator that is the tallest component on the board.
1.**Fomu Hacker**: These are the original design and are easiest to manufacture. If you received one directly from Tim, you probably have one of these. Hacker boards have white silkscreen on the back.
Aside from that, you need a computer with a USB port that can run the toolchain software. You should not need any special drivers, though on Linux you may need sudo access, or special udev rules to grant permission to use the USB device from a non-privileged account.
Field Programmable Gate Arrays (FPGAs) are arrays of gates that are programmable in the field. Unlike most chips you will encounter, which have transistor gates arranged in a fixed order, FPGAs can change their configuration by simply loading new code. Fundamentally, this code programs lookup tables which form the basic building blocks of logic.
These lookup tables (called LUTs) are so important to the design of an FPGA that they usually form part of the name of the part. For example, Fomu uses a UP5K, which has about 5000 LUTs. NeTV used an LX9, which had about 9000 LUTs, and NeTV2 uses a XC7A35T that has about 35000 LUTs.
This is the `SB_LUT4`, which is the basic building block of Fomu. It has four inputs and one output. To program Fomu, we must define what each possible input pattern will create on the output.
For example, to create a LUT that acted as an AND gate, we would define O to be 0 for everything except the last column. To create a NAND gate, we would define O to be 1 for everything except the last column.
FPGA LUTs are almost always _n_-inputs to 1-output. The ICE family of FPGAs from Lattice have 4-input LUTs. Xilinx parts tend to have 5- or 6-input LUTs which generally means they can do more logic in fewer LUTs. Comparing LUT count between FPGAs is a bit like comparing clock speed between different CPUs - not entirely accurate, but certainly a helpful rule of thumb.
Writing lookup tables is hard, so people have come up with abstract Hardware Description Languages (HDLs) we can use to describe them. The two most common languages are Verilog and VHDL. In the open source world, Verilog is more common. However, a modern trend is to embed an HDL inside an existing programming language, such as how Migen is embedded in Python, or SpinalHDL is embedded in Scala.
Here is an example of a Verilog module:
```verilog
module example (output reg [0:5] Q, input C);
reg [0:8] counter;
always @(posedge C)
begin
counter <= counter + 1'b1;
Q = counter[3] ^ counter[5] | counter<<2;
end
endmodule
```
We can run this Verilog module through a synthesizer to turn it into `SB_LUT4` blocks, or we can turn it into a more familiar logic diagram:
If we do decide to synthesize to `SB_LUT4` blocks, we will end up with a pile of LUTs that need to be strung together somehow. This is done by a Place-and-Route tool. This performs the job of assigning physical LUTs to each LUT that gets defined by the synthesizer, and then figuring out how to wire it all up.
Once the place-and-route tool is done, it generates an abstract file that needs to be translated into a format that the hardware can recognize. This is done by a bitstream packing tool. Finally, this bitstream needs to be loaded onto the device somehow, either off of a SPI flash or by manually programming it by toggling wires.
Many FPGAs have what's called block RAM, or BRAM. This is frequently used to store data such as buffers, CPU register files, and large arrays of data. This type of memory is frequently reused as RAM on many FPGAs. The ICE40UP5K is unusual in that it also as 128 kilobytes of Single Ported RAM that can be used as memory for a softcore. That means that, unlike other FPGAs, valuable block ram isn't taken up by system memory.
Additionally, the ICE40 family of devices generally supports "warmboot" capability. This enables us to have multiple designs live on the same FPGA and tell the FPGA to swap between them.
As always, this workshop wouldn't be nearly as easy without the open toolchain that enables us to port it to a lot of different platforms.
Fomu is an ICE40UP5K that fits in your USB port. It contains two megabytes of SPI flash memory, four edge buttons, and a three-color LED. Unlike most other ICE40 projects, Fomu implements its USB in a softcore. That means that the bitstream that runs on the FPGA must also provide the ability to communicate over USB. This uses up a lot of storage on this small FPGA, but it also enables us to have such a tiny form factor, and lets us do some really cool things with it.
There is a default bootloader that runs when you plug in Fomu. It is called `foboot`, and it presents itself as a DFU image. Future versions of Fomu will include a bootloader that shows up as an external drive, however for now we're still using DFU.
Verify the drivers were installed. Plug in your Fomu now and see if you can see it using `dfu-util -l`:
If you get a `permission denied` or `Cannot open DFU device 1209:5bf0` error then see the next two sections.
#### (Windows earlier than 10 Only) Setting udev permissions
If you're running a version of Windows earlier than Windows 10, you may need to install additional drivers.
Download [Zadig](https://zadig.akeo.ie/). Open Zadig. Under Options, select "List All Devices". In the dropdown, select your Fomu and in the field right of the green arrow choose the `WinUSB` driver and hit Upgrade Driver.
In Linux, try running `sudo dfu-util -l` if that no longer get the error message you should add a `udev` rule as to give your user permission to the usb device.
After the image is loaded, Fomu will start the new image. You can load RISC-V code or an ICE40 bitstream.
To restart Fomu, unplug it and plug it back in. This will start the bootloader. To run the program on Fomu without needing to load it again, use the `-e` option:
If you're running a version of Windows earlier than Windows 10, you will need to install a driver for the serial port. Open Zadag again and select `Fomu` from the dropdown list. Install the driver for `USB Serial (CDC)`. You can then use a program such as [Tera Term](https://tera-term.en.lo4d.com/download): In Teraterm hit New Connection and select the "Serial Port"-Radio Button. If it is greyed out you might have to change your USB Port driver for the Fomu. See Working with Fomu, above.
Fomu has a few extended modules that you can use to interact with some of the hardware. For example, the RGB LED has some predefined modes you can access. These are all located under the `fomu` module.
Import the `fomu` module and access the `rgb` block to change the mode to the predefined `error` mode:
```python
>>> import fomu
>>> rgb = fomu.rgb()
>>> rgb.mode("error")
>>>
```
We can also look at some information from the SPI flash, such as the SPI ID. This ID varies between Fomu models, so it can be a good indication of what kind of Fomu your code is running on:
If we look at the generated Fomu header files, we can see many, many memory-mapped registers. For example, the major, minor, and revision numbers all have registers:
```cpp
#define CSR_VERSION_MAJOR_ADDR 0xe0007000
#define CSR_VERSION_MINOR_ADDR 0xe0007004
#define CSR_VERSION_REVISION_ADDR 0xe0007008
#define CSR_VERSION_MODEL_ADDR 0xe0007028
```
These are special areas of memory that don't really exist. Instead, they correspond to hardware. We can read these values using the `machine` class. Read out the major, minor, and revision codes from your Fomu. They may be different from what you see here:
The `CSR_VERSION_MODEL_ADDR` contains a single character that indicates what version of the hardware you have. We can convert this to a character and print it out.
The blinking LED is actually a hardware block from Lattice. It has control registers, and we can modify these registers by writing to memory in Fomu. Some of these registers control things such as the timing of the fade in and fade out pulses, and some control the level of each of the three colors.
There is a wrapper in Python that simplifies the process of writing to these registers. The first argument is the register number, and the second argument is the value to write.
The color should change immediately. More information on these registers can be found in the [iCE40 LED Driver Usage Guide](reference/FPGA-TN-1288-ICE40LEDDriverUsageGuide.pdf).
If you look at the diagram above, you can see that everything in the system is on the Wishbone bus. The CPU is a bus master, and can initiate reads and writes. The system's RAM is on the wishbone bus, and is currently located at address `0x10000000`. The boot ROM is also on the bus, and is located at `0x00000000`. There is also SPI flash which is memory-mapped, so when you load your program onto SPI it shows up on the Wishbone bus at offset `0x20040000`.
The Configuration and Status Registers (CSRs) all show up at offset `0xe0000000`. These are the registers we were accessing from Python. Just like before, these special memory addresses correspond to control values.
You'll notice a "Bridge" in the diagram above. This is an optional feature that we ship by default on Fomu. It bridges the Wishbone bus to another device. In our case, it makes Wishbone available over USB.
This is a special USB packet we can generate to access the Wishbone bus from a host PC. It lets us do two things: Read a 32-bit value from Wishbone, or write a 32-bit value to Wishbone. These two primitives give us complete control over Fomu.
Recall these definitions from earlier:
```cpp
#define CSR_VERSION_MAJOR_ADDR 0xe0007000
#define CSR_VERSION_MINOR_ADDR 0xe0007004
#define CSR_VERSION_REVISION_ADDR 0xe0007008
#define CSR_VERSION_MODEL_ADDR 0xe0007028
```
We can use the `wishbone-tool` program to read these values directly out of Fomu:
```sh
$ wishbone-tool 0xe0007000
Value at e0007000: 00000001
$ wishbone-tool 0xe0007004
Value at e0007004: 00000008
$ wishbone-tool 0xe0007008
Value at e0007008: 00000007
$
```
The three values correspond to the version number of the board at time of writing: v1.8.7.
We can also read and write directly to memory. Recall that memory is mapped to address `0x10000000`. Let's write a test value there and try to read it back.
```sh
$ wishbone-tool 0x10000000
Value at 10000000: 00000005
$ wishbone-tool 0x10000000 0x12345678
$ wishbone-tool 0x10000000
Value at 10000000: 0x12345678
```
We can see that the value got stored in memory, just like we thought it would. The bridge is working, and we have access to Fomu over USB.
Recall the LED block from Python. We used `rgb.write_raw()` to write values to the LED block. Because of how the LED block is implemented, we need to actually make two writes to the Wishbone bus in order to write one value to the LED block. The first write sets the address, and the second write sends the actual data.
The registers for the LED block are defined as:
```cpp
#define CSR_RGB_DAT_ADDR 0xe0006800
#define CSR_RGB_ADDR_ADDR 0xe0006804
```
Let's change the red color to the maximum value. To do that, we'll write a `1` to the address register, and `0xff` to the data register:
```sh
$ wishbone-tool 0xe0006804 1
$ wishbone-tool 0xe0006800 0xff
```
We can see that the LED immediately changed its behavior. Try playing around with various values to see what combinations you can come up with!
You can reset Fomu by writing a special value to the `CSR_REBOOT_CTRL` register at `0xe0006000L`. All writes to this register must start with `0xac`, to ensure random values aren't written. We can reboot Fomu by simply writing this value:
```sh
$ wishbone-tool 0xe0006000 0xac
INFO [wishbone_tool::usb_bridge] opened USB device device 007 on bus 001
INFO [wishbone_tool::usb_bridge] waiting for target device
ERROR [wishbone_tool] server error: BridgeError(USBError(Pipe))
$
```
We can see that `wishbone-tool` has crashed with an error of `USBError(Pipe)`, because the USB device went away as we were talking to it. This is expected behavior. Fomu should be back to its normal color and blink rate now.
Of course, Fomu's softcore is a full CPU, so we can write C code for it. Go to the `riscv-blink/` directory and run `make`. This will generate `riscv-blink.bin`, which we can load onto Fomu.
```sh
$ make
CC ./src/main.c main.o
CC ./src/rgb.c rgb.o
CC ./src/time.c time.o
AS ./src/crt0-vexriscv.S crt0-vexriscv.o
LD riscv-blink.elf
OBJCOPY riscv-blink.bin
IHEX riscv-blink.ihex
$ dfu-util -D riscv-blink.bin
Copyright 2005-2009 Weston Schmidt, Harald Welte and OpenMoko Inc.
Copyright 2010-2014 Tormod Volden and Stefan Schmidt
This program is Free Software and has ABSOLUTELY NO WARRANTY
Please report bugs to dfu-util@lists.gnumonks.org
Match vendor ID from file: 1209
Match product ID from file: 5bf0
Opening DFU capable USB device...
ID 1209:5bf0
Run-time device DFU version 0101
Claiming USB DFU Interface...
Setting Alternate Setting #0 ...
Determining device status: state = dfuIDLE, status = 0
dfuIDLE, continuing
DFU mode device DFU version 0101
Device returned transfer size 1024
Copying data from PC to DFU device
Download [====== ] 24% 804 bytes
$
```
This will load the binary onto Fomu and start it immediately. The LED should be blinking quickly in a rainbow pattern. Congratulations! You've compiled and loaded a RISC-V program onto a softcore.
Let's modify the program by increasing the fade rate so much that it appears solid. First, reboot Fomu by running `wishbone-tool 0xe0006000 0xac`. Next, apply the following patch to `src/main.c`:
What this does is increase the LED blink rate from 250 Hz to a much higher value. Compile this and load it again with `dfu-util -D riscv-blink.bin`. The blink rate should appear solid, because it's blinking too quickly to see.
Because we have `peek` and `poke`, and because the USB bridge is a bus master, we can actually halt (and reset!) the CPU over the USB bridge. We can go even further and attach a full debugger to it!
There is an additional RISC-V demo in the workshop. The `riscv-usb-cdcacm` directory contains a simple USB serial device that simply echoes back any characters that you type, incremented by 1. This is a good way to get started with an interactive terminal program, or logging data via USB serial.
The canonical "Hello, world!" of hardware is to blink an LED. The directory `verilog-blink` contains a Verilog example of a blink project. This takes the 48 MHz clock and divides it down by a large number so you get an on/off pattern. It also exposes some of the signals on the touchpads, making it possible to probe them with an oscilloscope.
You can load `blink.bin` onto Fomu by using the same `dfu-util -D` command we've been using. The LED should begin blinking on and off regularly, indicating your bitstream was successfully loaded.
> When writing HDL, a tool called `yosys` is used to convert the human readable verilog into a netlist representation, this is called synthesis. Once we have the netlist representation a tool called `nextpnr` performs an operation called "place and route" which makes it something that will actually run on the FPGA. This is all done for you using the `Makefile` in the `verilog-blink` directory.
>
> A big feature of `nextpnr` over its predecessor, is the fact that it is timing-driven. This means that a design will be generated with a given clock domain guaranteed to perform fast enough.
>
> When the `make` command runs `nextpnr-ice40` you will see the following included in the output;
> ```
> Max frequency for clock 'clk12': 24.63 MHz (PASS at 12.00 MHz)
> Max frequency for clock 'clk48_1': 60.66 MHz (PASS at 48.00 MHz)
> Max frequency for clock 'clkraw': 228.05 MHz (PASS at 48.00 MHz)
> ```
>
> This output example above shows we could run `clk12` at up to 24.63 MHz and it would still be stable, even though we only requested 12.00 MHz. Note that there is some variation between designs depending on how the placer and router decided to lay things out, so your exact frequency numbers might be different.
FIXME: Add the Migen and LiteX equivalent for the Verilog above.
#### Wishbone Bus
Migen is an HDL embedded in Python, and LiteX provides us with a Wishbone abstraction layer. There really is no reason we need to include a CPU with our design, but we can still reuse the USB Wishbone bridge in order to write HDL code.
We can use `DummyUsb` to respond to USB requests and bridge USB to Wishbone, and rely on LiteX to generate registers and wire them to hardware signals. We can still use `wishbone-tool` to read and write memory, and with a wishbone bridge we can actually have code running on our local system that can read and write memory on Fomu.
Take a look at `build/csr.csv`. This describes the various regions present in our design. You can see `memory_region,sram,0x10000000,131072`, which indicates the RAM is 128 kilobytes long and is located at `0x10000000`, just as when we had a CPU. You can also see the timer, which is a feature that comes as part of LiteX. Let's try reading and writing RAM:
This is the RGB block from the datasheet. It has five inputs: `CURREN`, `RGBLEDEN`, `RGB0PWM`, `RGB1PWM`, and `RGB2PWM`. It has three outputs: `RGB0`, `RGB1`, and `RGB2`. It also has four parameters: `CURRENT_MODE`, `RGB0_CURRENT`, `RGB1_CURRENT`, and `RGB2_CURRENT`.
This block is defined in Verilog, but we can very easily import it as a Module into Migen:
This will instantiate this Verilog block and connect it up. It also creates a `CSRStorage` object that is three bits wide, and assigns it to `output`. By having this derive from `AutoCSR`, the CSRStorage will have CSR bus accessor methods added to it automatically. Finally, it wires the pads up to the outputs of the block.
