2019-06-20 15:37:14 +00:00
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#!/usr/bin/env python3
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# This variable defines all the external programs that this module
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# relies on. lxbuildenv reads this variable in order to ensure
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# the build will finish without exiting due to missing third-party
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# programs.
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2019-08-19 10:19:27 +00:00
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LX_DEPENDENCIES = ["icestorm", "yosys", "nextpnr-ice40"]
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2019-10-22 16:05:09 +00:00
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#LX_CONFIG = "skip-git" # This can be useful for workshops
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2019-06-20 15:37:14 +00:00
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# Import lxbuildenv to integrate the deps/ directory
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2019-08-24 16:31:10 +00:00
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import os,os.path,shutil,sys,subprocess
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2019-06-20 15:37:14 +00:00
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sys.path.insert(0, os.path.dirname(__file__))
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import lxbuildenv
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# Disable pylint's E1101, which breaks completely on migen
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#pylint:disable=E1101
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2019-09-02 10:42:32 +00:00
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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2019-12-30 18:28:45 +00:00
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from litex.soc.integration.soc_core import SoCCore
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2019-06-20 15:37:14 +00:00
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from litex.soc.integration.builder import Builder
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2019-09-02 10:42:32 +00:00
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from litex.soc.interconnect.csr import AutoCSR, CSRStatus, CSRStorage
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2019-06-20 15:37:14 +00:00
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2019-09-02 10:42:32 +00:00
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from litex_boards.partner.targets.fomu import BaseSoC, add_dfu_suffix
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2019-06-20 15:37:14 +00:00
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from valentyusb.usbcore import io as usbio
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from valentyusb.usbcore.cpu import dummyusb
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import argparse
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class FomuRGB(Module, AutoCSR):
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def __init__(self, pads):
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self.output = CSRStorage(3)
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self.specials += Instance("SB_RGBA_DRV",
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i_CURREN = 0b1,
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i_RGBLEDEN = 0b1,
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i_RGB0PWM = self.output.storage[0],
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i_RGB1PWM = self.output.storage[1],
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i_RGB2PWM = self.output.storage[2],
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o_RGB0 = pads.r,
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o_RGB1 = pads.g,
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o_RGB2 = pads.b,
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p_CURRENT_MODE = "0b1",
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p_RGB0_CURRENT = "0b000011",
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p_RGB1_CURRENT = "0b000011",
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p_RGB2_CURRENT = "0b000011",
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)
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def main():
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parser = argparse.ArgumentParser(
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description="Build Fomu Main Gateware")
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parser.add_argument(
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"--seed", default=0, help="seed to use in nextpnr"
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)
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parser.add_argument(
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"--placer", default="heap", choices=["sa", "heap"], help="which placer to use in nextpnr"
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)
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2019-08-20 09:42:53 +00:00
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parser.add_argument(
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"--board", choices=["evt", "pvt", "hacker"], required=True,
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help="build for a particular hardware board"
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)
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2019-06-20 15:37:14 +00:00
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args = parser.parse_args()
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2019-09-02 10:42:32 +00:00
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soc = BaseSoC(args.board, pnr_seed=args.seed, pnr_placer=args.placer, usb_bridge=True)
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# Add the LED driver block. Get the `rgb_led` pins from the definition
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# file, then instantiate the module we defined above.
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led_pads = soc.platform.request("rgb_led")
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soc.submodules.fomu_rgb = FomuRGB(led_pads)
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# Indicate that `fomu_rgb` is a CSR, and should be added to the bus.
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# Otherwise we wouldn't be able to access `fomu_rgb` at all.
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# Note that the value here must match the value above, so if you did
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# `soc.submodules.frgb = FomuRGB(led_pads)` then you would need to
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# change this to `soc.add_csr("frgb")`.
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soc.add_csr("fomu_rgb")
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2019-06-20 15:37:14 +00:00
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builder = Builder(soc,
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2019-09-02 10:42:32 +00:00
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output_dir="build", csr_csv="build/csr.csv",
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2019-06-20 15:37:14 +00:00
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compile_software=False)
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vns = builder.build()
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soc.do_exit(vns)
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2019-08-24 16:31:10 +00:00
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add_dfu_suffix(os.path.join('build', 'gateware', 'top.bin'))
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2019-06-20 15:37:14 +00:00
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2019-08-27 20:31:47 +00:00
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2019-06-20 15:37:14 +00:00
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if __name__ == "__main__":
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main()
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