coelner/fomu-workshop
1
0
Fork 0
mirror of https://github.com/im-tomu/fomu-workshop.git synced 2024-09-20 03:10:12 +00:00
Code Issues Packages Projects Releases Wiki Activity

Merge pull request #283 from tcal-x/fixes

Browse Source 
Don't mix assignment styles in the same Verilog block.
This commit is contained in:
Sean Cross 2020-08-08 13:35:18 +08:00 committed by GitHub
commit 050eea6cf0
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
docs/background.rst
View File

@ -72,7 +72,7 @@ Here is an example of a Verilog module:
always @(posedge C)
begin
counter <= counter + 1'b1;
Q = counter[3] ^ counter[5] | counter<<2;
Q <= counter[3] ^ counter[5] | counter<<2;
end
endmodule