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Merge pull request #283 from tcal-x/fixes
Don't mix assignment styles in the same Verilog block.
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@ -72,7 +72,7 @@ Here is an example of a Verilog module:
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always @(posedge C)
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begin
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counter <= counter + 1'b1;
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Q = counter[3] ^ counter[5] | counter<<2;
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Q <= counter[3] ^ counter[5] | counter<<2;
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end
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endmodule
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