hdl: style

hdl/mixed/blink/Makefile

@@ -1,5 +1,8 @@
 include ../../board.mk
 
+DESIGN = blink
+TOP    = Fomu_Blink
+
 # VHDL top with instantiated Verilog
 VHDL_SYN_FILES    = ../../sb_ice40_components.vhd blink.vhd
 VERILOG_SYN_FILES = clkgen.v
@@ -21,24 +24,24 @@ YOSYSFLAGS += -m $(GHDL_PLUGIN_MODULE)
 endif
 
 # Default target: run all required targets to build the DFU image.
-all: blink.dfu
+all: $(DESIGN).dfu
 	@true
 
 .DEFAULT: all
 
 # Use *Yosys* to generate the synthesized netlist.
 # This is called the **synthesis** and **tech mapping** step.
-blink.json: $(VHDL_SYN_FILES) $(VERILOG_SYN_FILES)
+$(DESIGN).json: $(VHDL_SYN_FILES) $(VERILOG_SYN_FILES)
 	$(YOSYS) $(YOSYSFLAGS) \
 		-p \
 		"$(GHDLSYNTH) $(GHDL_FLAGS) $(VHDL_SYN_FILES) -e; \
 		synth_ice40 \
-		-top Fomu_Blink \
+		-top $(TOP) \
 		-json $@" $(VERILOG_SYN_FILES) 2>&1 | tee yosys-report.txt
 
 # Use **nextpnr** to generate the FPGA configuration.
 # This is called the **place** and **route** step.
-blink.asc: blink.json $(PCF)
+$(DESIGN).asc: $(DESIGN).json $(PCF)
 	$(NEXTPNR) \
 		$(PNRFLAGS) \
 		--pcf $(PCF) \
@@ -47,16 +50,16 @@ blink.asc: blink.json $(PCF)
 
 # Use icepack to convert the FPGA configuration into a "bitstream" loadable onto the FPGA.
 # This is called the bitstream generation step.
-blink.bit: blink.asc
+$(DESIGN).bit: $(DESIGN).asc
 	$(ICEPACK) $< $@
 
 # Use dfu-suffix to generate the DFU image from the FPGA bitstream.
-blink.dfu: blink.bit
+$(DESIGN).dfu: $(DESIGN).bit
 	cp $< $@
 	dfu-suffix -v 1209 -p 70b1 -a $@
 
 # Use df-util to load the DFU image onto the Fomu.
-load: blink.dfu
+load: $(DESIGN).dfu
 	dfu-util -D $<
 
 .PHONY: load

hdl/verilog/blink-expanded/Makefile

@@ -1,5 +1,9 @@
-PACKAGE   ?= blink
-TOP       ?= $(PACKAGE)
+include ../../board.mk
+
+DESIGN = blink
+TOP    = $(DESIGN)
+
+VERILOG_SYN_FILES = blink.v
 
 # Currently GIT_VERSION is unusd and there are no tags, so skip calculating it
 #GIT_VERSION := $(shell git describe --tags)
@@ -27,40 +31,38 @@ RM         = del
 PATH_SEP   = \\
 endif
 
-include ../../board.mk
-
 BUILD_DIR  = build
 VSOURCES   = $(wildcard *.v)
 QUIET      = @
 
 ALL        = all
-TARGET     = $(PACKAGE).bin
+TARGET     = $(DESIGN).bin
 CLEAN      = clean
 
-$(ALL): $(TARGET) $(PACKAGE).dfu
-	$(QUIET) echo "Built '$(PACKAGE)' for Fomu $(FOMU_REV)"
+$(ALL): $(TARGET) $(DESIGN).dfu
+	$(QUIET) echo "Built '$(DESIGN)' for Fomu $(FOMU_REV)"
 
 run: $(TARGET)
 	fomu-flash -f $(TARGET)
 
-run-dfu: $(PACKAGE).dfu
-	dfu-util -D $(PACKAGE).dfu
+run-dfu: $(DESIGN).dfu
+	dfu-util -D $(DESIGN).dfu
 
-$(BUILD_DIR)/$(PACKAGE).json: $(VSOURCES) | $(BUILD_DIR)
+$(BUILD_DIR)/$(DESIGN).json: $(VSOURCES) | $(BUILD_DIR)
 	$(QUIET) echo " SYNTH    $@"
-	$(QUIET) $(YOSYS) $(YOSYSFLAGS) -p 'synth_ice40 -top $(TOP) -json $@' $(PACKAGE).v
+	$(QUIET) $(YOSYS) $(YOSYSFLAGS) -p 'synth_ice40 -top $(TOP) -json $@' $(VERILOG_SYN_FILES)
 
-$(BUILD_DIR)/$(PACKAGE).asc: $(BUILD_DIR)/$(PACKAGE).json $(PCF)
+$(BUILD_DIR)/$(DESIGN).asc: $(BUILD_DIR)/$(DESIGN).json $(PCF)
 	$(QUIET) echo " PNR      $@"
-	$(QUIET) $(NEXTPNR) $(PNRFLAGS) --json $(BUILD_DIR)/$(PACKAGE).json --pcf $(PCF) --asc $@
+	$(QUIET) $(NEXTPNR) $(PNRFLAGS) --json $(BUILD_DIR)/$(DESIGN).json --pcf $(PCF) --asc $@
 
-$(TARGET): $(BUILD_DIR)/$(PACKAGE).asc
+$(TARGET): $(BUILD_DIR)/$(DESIGN).asc
 	$(QUIET) echo " PACK     $@"
-	$(QUIET) $(ICEPACK) $(BUILD_DIR)/$(PACKAGE).asc $@
+	$(QUIET) $(ICEPACK) $(BUILD_DIR)/$(DESIGN).asc $@
 
-$(PACKAGE).dfu: $(TARGET)
+$(DESIGN).dfu: $(TARGET)
 	$(QUIET) echo "  DFU      $@"
-	$(QUIET) $(COPY) $(PACKAGE).bin $@
+	$(QUIET) $(COPY) $(DESIGN).bin $@
 	$(QUIET) dfu-suffix -v 1209 -p 70b1 -a $@
 
 $(BUILD_DIR):
@@ -73,7 +75,7 @@ clean:
 	-$(QUIET) $(RM) $(subst /,$(PATH_SEP),$(wildcard $(BUILD_DIR)/*.json))
 	$(QUIET) echo "  RM      $(subst /,$(PATH_SEP),$(wildcard $(BUILD_DIR)/*.asc))"
 	-$(QUIET) $(RM) $(subst /,$(PATH_SEP),$(wildcard $(BUILD_DIR)/*.asc))
-	$(QUIET) echo "  RM      $(TARGET) $(PACKAGE).bin $(PACKAGE).dfu"
+	$(QUIET) echo "  RM      $(TARGET) $(DESIGN).bin $(DESIGN).dfu"
 	-$(QUIET) $(RM) $(subst /,$(PATH_SEP),abc.history)
 	$(QUIET) echo "  RM      $(TARGET) abc.history"
-	-$(QUIET) $(RM) $(TARGET) $(PACKAGE).bin $(PACKAGE).dfu
+	-$(QUIET) $(RM) $(TARGET) $(DESIGN).bin $(DESIGN).dfu

hdl/verilog/blink/Makefile

@@ -5,49 +5,60 @@
 
 include ../../board.mk
 
+DESIGN = blink
+TOP    = top
+
+VERILOG_SYN_FILES = blink.v
+
+YOSYS     ?= yosys
+NEXTPNR   ?= nextpnr-ice40
+ICEPACK   ?= icepack
+
 # Default target: run all required targets to build the DFU image.
-all: blink.dfu
+all: $(DESIGN).dfu
 	@true
 
 .DEFAULT: all
 
 # Use *Yosys* to generate the synthesized netlist.
 # This is called the **synthesis** and **tech mapping** step.
-blink.json: blink.v
-	yosys \
-		$(YOSYSFLAGS) \
-		-p 'synth_ice40 -top top -json blink.json' blink.v
+$(DESIGN).json: $(VERILOG_SYN_FILES)
+	$(YOSYS) $(YOSYSFLAGS) \
+		-p  \
+		"synth_ice40 \
+		-top $(TOP) \
+		-json $@" $(VERILOG_SYN_FILES) 2>&1 | tee yosys-report.txt
 
 # Use **nextpnr** to generate the FPGA configuration.
 # This is called the **place** and **route** step.
-blink.asc: blink.json $(PCF)
-	nextpnr-ice40 \
+$(DESIGN).asc: $(DESIGN).json $(PCF)
+	$(NEXTPNR) \
 		$(PNRFLAGS) \
 		--pcf $(PCF) \
-		--json blink.json \
-		--asc blink.asc
+		--json  $< \
+		--asc $@
 
 # Use icepack to convert the FPGA configuration into a "bitstream" loadable onto the FPGA.
 # This is called the bitstream generation step.
-blink.bit: blink.asc
-	icepack blink.asc blink.bit
+$(DESIGN).bit: $(DESIGN).asc
+	$(ICEPACK) $< $@
 
 # Use dfu-suffix to generate the DFU image from the FPGA bitstream.
-blink.dfu: blink.bit
-	cp blink.bit blink.dfu
-	dfu-suffix -v 1209 -p 70b1 -a blink.dfu
+$(DESIGN).dfu: $(DESIGN).bit
+	cp $< $@
+	dfu-suffix -v 1209 -p 70b1 -a $@
 
 # Use df-util to load the DFU image onto the Fomu.
-load: blink.dfu
-	dfu-util -D blink.dfu
+load: $(DESIGN).dfu
+	dfu-util -D  $<
 
 .PHONY: load
 
 # Cleanup the generated files.
 clean:
-	-rm -f blink.json 	# Generate netlist
-	-rm -f blink.asc 	# FPGA configuration
-	-rm -f blink.bit 	# FPGA bitstream
-	-rm -f blink.dfu 	# DFU image loadable onto the Fomu
+	-rm -f $(DESIGN).json 	# Generate netlist
+	-rm -f $(DESIGN).asc 	# FPGA configuration
+	-rm -f $(DESIGN).bit 	# FPGA bitstream
+	-rm -f $(DESIGN).dfu 	# DFU image loadable onto the Fomu
 
 .PHONY: clean

hdl/vhdl/blink/Makefile

@@ -1,5 +1,8 @@
 include ../../board.mk
 
+DESIGN = blink
+TOP    = Fomu_Blink
+
 VHDL_SYN_FILES = ../../sb_ice40_components.vhd blink.vhd
 
 GHDL_FLAGS += --std=08
@@ -22,17 +25,17 @@ all: blink.dfu
 
 # Use *Yosys* to generate the synthesized netlist.
 # This is called the **synthesis** and **tech mapping** step.
-blink.json: $(VHDL_SYN_FILES)
+$(DESIGN).json: $(VHDL_SYN_FILES)
 	$(YOSYS) $(YOSYSFLAGS) \
 		-p \
 		"$(GHDLSYNTH) $(GHDL_FLAGS) $^ -e; \
 		synth_ice40 \
-		-top Fomu_Blink \
+		-top $(TOP) \
 		-json $@" 2>&1 | tee yosys-report.txt
 
 # Use **nextpnr** to generate the FPGA configuration.
 # This is called the **place** and **route** step.
-blink.asc: blink.json $(PCF)
+$(DESIGN).asc: $(DESIGN).json $(PCF)
 	$(NEXTPNR) \
 		$(PNRFLAGS) \
 		--pcf $(PCF) \
@@ -41,16 +44,16 @@ blink.asc: blink.json $(PCF)
 
 # Use icepack to convert the FPGA configuration into a "bitstream" loadable onto the FPGA.
 # This is called the bitstream generation step.
-blink.bit: blink.asc
+$(DESIGN).bit: $(DESIGN).asc
 	$(ICEPACK) $< $@
 
 # Use dfu-suffix to generate the DFU image from the FPGA bitstream.
-blink.dfu: blink.bit
+$(DESIGN).dfu: $(DESIGN).bit
 	cp $< $@
 	dfu-suffix -v 1209 -p 70b1 -a $@
 
 # Use df-util to load the DFU image onto the Fomu.
-load: blink.dfu
+load: $(DESIGN).dfu
 	dfu-util -D $<
 
 .PHONY: load