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hdl/verilog: use read_verilog command

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This commit is contained in:
umarcor 2022-01-08 10:21:34 +01:00
parent 64a83d7e87
commit 5ac9781e01
2 changed files with 6 additions and 4 deletions
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5
hdl/verilog/blink-expanded/Makefile
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@ -49,9 +49,10 @@ all: $(DESIGN).dfu
$(DESIGN).json: $(VERILOG_SYN_FILES)
$(QUIET) $(YOSYS) $(YOSYSFLAGS) \
-p \
"synth_ice40 \
"read_verilog $(VERILOG_SYN_FILES); \
synth_ice40 \
-top $(TOP) \
-json $@" $(VERILOG_SYN_FILES) 2>&1 | tee yosys-report.txt
-json $@" 2>&1 | tee yosys-report.txt
include ../../PnR_Prog.mk

5
hdl/verilog/blink/Makefile
View File

@ -30,9 +30,10 @@ all: $(DESIGN).dfu
$(DESIGN).json: $(VERILOG_SYN_FILES)
$(QUIET) $(YOSYS) $(YOSYSFLAGS) \
-p \
"synth_ice40 \
"read_verilog $(VERILOG_SYN_FILES); \
synth_ice40 \
-top $(TOP) \
-json $@" $(VERILOG_SYN_FILES) 2>&1 | tee yosys-report.txt
-json $@" 2>&1 | tee yosys-report.txt
include ../../PnR_Prog.mk