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hdl/verilog: use read_verilog command
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parent
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commit
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@ -49,9 +49,10 @@ all: $(DESIGN).dfu
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$(DESIGN).json: $(VERILOG_SYN_FILES)
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$(DESIGN).json: $(VERILOG_SYN_FILES)
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$(QUIET) $(YOSYS) $(YOSYSFLAGS) \
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$(QUIET) $(YOSYS) $(YOSYSFLAGS) \
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-p \
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-p \
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"synth_ice40 \
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"read_verilog $(VERILOG_SYN_FILES); \
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synth_ice40 \
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-top $(TOP) \
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-top $(TOP) \
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-json $@" $(VERILOG_SYN_FILES) 2>&1 | tee yosys-report.txt
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-json $@" 2>&1 | tee yosys-report.txt
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include ../../PnR_Prog.mk
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include ../../PnR_Prog.mk
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@ -30,9 +30,10 @@ all: $(DESIGN).dfu
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$(DESIGN).json: $(VERILOG_SYN_FILES)
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$(DESIGN).json: $(VERILOG_SYN_FILES)
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$(QUIET) $(YOSYS) $(YOSYSFLAGS) \
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$(QUIET) $(YOSYS) $(YOSYSFLAGS) \
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-p \
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-p \
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"synth_ice40 \
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"read_verilog $(VERILOG_SYN_FILES); \
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synth_ice40 \
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-top $(TOP) \
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-top $(TOP) \
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-json $@" $(VERILOG_SYN_FILES) 2>&1 | tee yosys-report.txt
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-json $@" 2>&1 | tee yosys-report.txt
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include ../../PnR_Prog.mk
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include ../../PnR_Prog.mk
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