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Implement SB_MAC16 DSP
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parent
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commit
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@ -29,4 +29,64 @@ component SB_RGBA_DRV
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);
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);
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end component;
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end component;
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-- SB_MAC16 DSP. Default values according to datasheet
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component SB_MAC16
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generic (
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NEG_TRIGGER : integer := 0;
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A_REG : integer := 0;
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B_REG : integer := 0;
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C_REG : integer := 0;
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D_REG : integer := 0;
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TOP_8x8_MULT_REG : integer := 0;
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BOT_8x8_MULT_REG : integer := 0;
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PIPELINE_16x16_MULT_REG1 : integer := 0;
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PIPELINE_16x16_MULT_REG2 : integer := 0;
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TOPOUTPUT_SELECT : integer := 0;
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TOPADDSUB_LOWERINPUT : integer := 0;
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TOPADDSUB_UPPERINPUT : integer:= 0;
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TOPADDSUB_CARRYSELECT : integer := 0;
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BOTOUTPUT_SELECT : integer := 0;
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BOTADDSUB_LOWERINPUT : integer := 0;
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BOTADDSUB_UPPERINPUT : integer := 0;
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BOTADDSUB_CARRYSELECT : integer := 0;
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MODE_8x8 : integer := 0;
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A_SIGNED : integer := 0;
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B_SIGNED : integer := 0
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);
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port (
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CLK: in std_logic;
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CE: in std_logic := '1';
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A: in std_logic_vector(15 downto 0) := (others => '0');
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B: in std_logic_vector(15 downto 0) := (others => '0');
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C: in std_logic_vector(15 downto 0) := (others => '0');
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D: in std_logic_vector(15 downto 0) := (others => '0');
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AHOLD : in std_logic := '0';
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BHOLD : in std_logic := '0';
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CHOLD : in std_logic := '0';
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DHOLD : in std_logic := '0';
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IRSTTOP : in std_logic := '0';
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ORSTTOP : in std_logic := '0';
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OLOADTOP : in std_logic := '0';
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ADDSUBTOP : in std_logic := '0';
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OHOLDTOP : in std_logic := '0';
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IRSTBOT : in std_logic := '0';
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ORSTBOT : in std_logic := '0';
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OLOADBOT : in std_logic := '0';
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ADDSUBBOT : in std_logic := '0';
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OHOLDBOT : in std_logic := '0';
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O: out std_logic_vector(31 downto 0);
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CI : in std_logic := '0';
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CO : out std_logic
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);
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end component;
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end components;
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end components;
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