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Merge pull request #512 from proppy/mixed-hdl-formatting

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docs/mixed-hdl: fix formatting
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Tim Ansell 2021-07-29 09:16:19 -07:00 committed by GitHub
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docs/mixed-hdl.rst
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@ -74,7 +74,7 @@ However, any of the following cases produce the same result:
- ``blink.vhd`` + ``clkgen.vhdl``
- ``blink.v`` + ``clkgen.v``
You can modify variables `VHDL_SYN_FILES` and ``VERILOG_SYN_FILES`` in the :repo:`Makefile <hdl/mixed/blink/Makefile>`
You can modify variables ``VHDL_SYN_FILES`` and ``VERILOG_SYN_FILES`` in the :repo:`Makefile <hdl/mixed/blink/Makefile>`
for trying other combinations.
For a better understanding, it is suggested to compare these modules with the single file solutions in
:ref:`HDLs:Verilog` and :ref:`HDLs:VHDL`.