Moving the images under the docs/_static directory.

README.md

@@ -1,6 +1,6 @@
 # [Fomu Workshop](https://workshop.fomu.im/)
 
-![Hi, I'm Fomu!](img/logo.png "Fomu logo")
+![Hi, I'm Fomu!](docs/_static/logo.png "Fomu logo")
 
 Hi, I'm Fomu!  [This workshop](https://workshop.fomu.im/) covers the basics of
 Fomu in a top-down approach.  We'll start out by learning what Fomu is, how to

docs/background.rst

@@ -15,7 +15,7 @@ FPGA that they usually form part of the name of the part. For example,
 Fomu uses a UP5K, which has about 5000 LUTs. NeTV used an LX9, which had
 about 9000 LUTs, and NeTV2 uses a XC7A35T that has about 35000 LUTs.
 
-.. image:: ../img/ice40-lut.png
+.. image:: _static/ice40-lut.png
    :width: 100%
    :alt: The ICE40 LUT4 is a basic 4-input 1-output LUT
 
@@ -80,7 +80,7 @@ We can run this Verilog module through a synthesizer to turn it into
 ``SB_LUT4`` blocks, or we can turn it into a more familiar logic
 diagram:
 
-.. image:: ../img/verilog-synthesis.png
+.. image:: _static/verilog-synthesis.png
    :width: 100%
    :alt: A syntheis of the above logic into some gates
 
@@ -138,7 +138,7 @@ the ability to communicate over USB. This uses up a lot of storage on
 this small FPGA, but it also enables us to have such a tiny form factor,
 and lets us do some really cool things with it.
 
-.. image:: ../img/fomu-block-diagram.png
+.. image:: _static/fomu-block-diagram.png
    :width: 100%
    :alt: Block diagram of Fomu
 

docs/index.rst

@@ -2,7 +2,7 @@
 FPGA Tomu Workshop
 ==================
 
-.. image:: ../img/logo.png
+.. image:: _static/logo.png
    :alt: Fomu logo
 
 Hi, I’m Fomu! This workshop covers the basics of Fomu in a top-down

docs/migen.rst

@@ -116,7 +116,7 @@ Aside from that, there’s not much we can *do* with this design. But
 there’s a lot of infrastructure there. So let’s add something (see
 ``workshop_rgb.py`` for full example).
 
-.. image:: ../img/ice40-rgb.jpg
+.. image:: _static/ice40-rgb.jpg
    :width: 100%
    :alt: RGB block
 

docs/python.rst

@@ -167,7 +167,7 @@ memory in Fomu. Some of these registers control things such as the
 timing of the fade in and fade out pulses, and some control the level of
 each of the three colors.
 
-.. image:: ../img/ice40-ledd.png
+.. image:: _static/ice40-ledd.png
    :width: 100%
    :alt: Registers of the ICE40 RGB driver
 

docs/requirements.rst

@@ -248,14 +248,14 @@ Which Fomu do I have?
 
     <span style="background-color: #03b1c4;">cyan / light blue</span>
 
-.. |Hacker Hardware Front without case| image:: ../img/hw-hacker-front-bare-small.jpg
-.. |Production Hardware Front without case| image:: ../img/hw-pvt-front-bare-small.jpg
-.. |Hacker Hardware Back without case| image:: ../img/hw-hacker-back-bare-small.jpg
-.. |Production Hardware Back without case| image:: ../img/hw-pvt-back-bare-small.jpg
-.. |Hacker Hardware Back with case| image:: ../img/hw-hacker-back-case-small.jpg
-.. |Production Hardware Back with case| image:: ../img/hw-pvt-back-case-small.jpg
-.. |Hacker Hardware Annotated Diagram| image:: ../img/hw-hacker-annotated.png
-.. |Production Hardware Annotated Diagram| image:: ../img/hw-pvt-annotated.png
+.. |Hacker Hardware Front without case| image:: _static/hw-hacker-front-bare-small.jpg
+.. |Production Hardware Front without case| image:: _static/hw-pvt-front-bare-small.jpg
+.. |Hacker Hardware Back without case| image:: _static/hw-hacker-back-bare-small.jpg
+.. |Production Hardware Back without case| image:: _static/hw-pvt-back-bare-small.jpg
+.. |Hacker Hardware Back with case| image:: _static/hw-hacker-back-case-small.jpg
+.. |Production Hardware Back with case| image:: _static/hw-pvt-back-case-small.jpg
+.. |Hacker Hardware Annotated Diagram| image:: _static/hw-hacker-annotated.png
+.. |Production Hardware Annotated Diagram| image:: _static/hw-pvt-annotated.png
 
 
 .. note::
@@ -374,6 +374,6 @@ Installing Zadig Drivers
 #. In the dropdown, select your Fomu and in the field right of the green arrow
    choose the `WinUSB` driver and hit Upgrade Driver.
 
-   .. image:: ../img/Zadeg-Setup.PNG
+   .. image:: _static/Zadeg-Setup.PNG
       :alt: Setup of ZADEG for Updating USBport driver on WIN7
 

docs/riscv.rst

@@ -8,7 +8,7 @@ The CPU in Fomu is built on LiteX, which places every device on a
 Wishbone bus. This is a 32-bit internal bus that maps peripherals into
 memory.
 
-.. image:: ../img/litex-design.png
+.. image:: _static/litex-design.png
    :width: 100%
    :alt: Fomu peripherals on the Wishbone bus
 
@@ -29,7 +29,7 @@ You’ll notice a “Bridge” in the diagram above. This is an optional
 feature that we ship by default on Fomu. It bridges the Wishbone bus to
 another device. In our case, it makes Wishbone available over USB.
 
-.. image:: ../img/wishbone-usb-debug-bridge.png
+.. image:: _static/wishbone-usb-debug-bridge.png
    :width: 100%
    :alt: Wishbone USB debug bridge interface