mirror of
https://github.com/im-tomu/fomu-workshop.git
synced 2024-09-20 03:10:12 +00:00
litex: move examples into litex/ directory
Signed-off-by: Sean Cross <sean@xobs.io>
This commit is contained in:
Sean Cross
parent
6862a659f9
commit
ac9e39bdcf
32
.gitmodules
vendored
32
.gitmodules
vendored
@ -1,24 +1,24 @@
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[submodule "deps/migen"]
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path = deps/migen
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[submodule "litex/deps/migen"]
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path = litex/deps/migen
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url = https://github.com/m-labs/migen.git
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[submodule "deps/litex"]
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path = deps/litex
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[submodule "litex/deps/litex"]
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path = litex/deps/litex
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url = https://github.com/enjoy-digital/litex.git
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[submodule "deps/litex_boards"]
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path = deps/litex_boards
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[submodule "litex/deps/litex_boards"]
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path = litex/deps/litex_boards
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url = https://github.com/litex-hub/litex-boards.git
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[submodule "deps/litescope"]
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path = deps/litescope
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[submodule "litex/deps/litescope"]
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path = litex/deps/litescope
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url = https://github.com/enjoy-digital/litescope.git
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[submodule "deps/pyserial"]
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path = deps/pyserial
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[submodule "litex/deps/pyserial"]
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path = litex/deps/pyserial
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url = https://github.com/pyserial/pyserial.git
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[submodule "deps/lxsocsupport"]
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path = deps/lxsocsupport
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[submodule "litex/deps/lxsocsupport"]
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path = litex/deps/lxsocsupport
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url = https://github.com/xobs/lxsocsupport.git
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[submodule "deps/valentyusb"]
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path = deps/valentyusb
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[submodule "litex/deps/valentyusb"]
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path = litex/deps/valentyusb
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url = https://github.com/im-tomu/valentyusb.git
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[submodule "deps/litedram"]
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path = deps/litedram
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[submodule "litex/deps/litedram"]
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path = litex/deps/litedram
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url = https://github.com/enjoy-digital/litedram.git
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108
litex/workshop.py
Normal file
108
litex/workshop.py
Normal file
@ -0,0 +1,108 @@
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#!/usr/bin/env python3
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# This variable defines all the external programs that this module
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# relies on. lxbuildenv reads this variable in order to ensure
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# the build will finish without exiting due to missing third-party
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# programs.
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LX_DEPENDENCIES = ["riscv", "icestorm"]
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# Import lxbuildenv to integrate the deps/ directory
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import lxbuildenv
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# Disable pylint's E1101, which breaks completely on migen
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#pylint:disable=E1101
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from litex_boards.partner.platforms.fomu_evt import Platform
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from litex_boards.partner.targets.fomu import _CRG
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from litex.soc.integration import SoCCore
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from litex.soc.integration.builder import Builder
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from lxsocsupport import up5kspram
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from valentyusb.usbcore import io as usbio
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from valentyusb.usbcore.cpu import dummyusb
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import argparse
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class BaseSoC(SoCCore):
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SoCCore.csr_map = {
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"ctrl": 0, # provided by default (optional)
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"crg": 1, # user
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"uart_phy": 2, # provided by default (optional)
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"uart": 3, # provided by default (optional)
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"identifier_mem": 4, # provided by default (optional)
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"timer0": 5, # provided by default (optional)
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"cpu_or_bridge": 8,
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"usb": 9,
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"picorvspi": 10,
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"touch": 11,
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"reboot": 12,
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"rgb": 13,
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"version": 14,
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}
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def __init__(self, platform, output_dir="build", placer=None, pnr_seed=0, use_pll=True, **kwargs):
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clk_freq = int(12e6)
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self.submodules.crg = _CRG(platform, use_pll=use_pll)
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SoCCore.__init__(self, platform, clk_freq,
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cpu_type=None,
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cpu_variant=None,
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integrated_sram_size=0,
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with_uart=False,
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with_ctrl=False,
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**kwargs)
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# UP5K has single port RAM, which is a dedicated 128 kilobyte block.
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# Use this as CPU RAM.
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spram_size = 128*1024
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self.submodules.spram = up5kspram.Up5kSPRAM(size=spram_size)
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self.register_mem("sram", 0x10000000, self.spram.bus, spram_size)
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# Add USB pads. We use DummyUsb, which simply enumerates as a USB
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# device. Then all interaction is done via the wishbone bridge.
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usb_pads = platform.request("usb")
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usb_iobuf = usbio.IoBuf(usb_pads.d_p, usb_pads.d_n, usb_pads.pullup)
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self.submodules.usb = dummyusb.DummyUsb(usb_iobuf, debug=True)
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self.add_wb_master(self.usb.debug_bridge.wishbone)
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# Add "-relut -dffe_min_ce_use 4" to the synth_ice40 command.
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# "-reult" adds an additional LUT pass to pack more stuff in, and
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# "-dffe_min_ce_use 4" flag prevents Yosys from generating a
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# Clock Enable signal for a LUT that has fewer than 4 flip-flops.
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# This increases density, and lets us use the FPGA more efficiently.
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platform.toolchain.nextpnr_yosys_template[2] += " -relut -dffe_min_ce_use 4"
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# Allow us to set the nextpnr seed, because some values don't meet timing.
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platform.toolchain.nextpnr_build_template[1] += " --seed " + str(pnr_seed)
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# Different placers can improve packing efficiency, however not all placers
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# are enabled on all builds of nextpnr-ice40. Let the user override which
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# placer they want to use.
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if placer is not None:
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platform.toolchain.nextpnr_build_template[1] += " --placer {}".format(placer)
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def main():
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parser = argparse.ArgumentParser(
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description="Build Fomu Main Gateware")
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parser.add_argument(
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"--seed", default=0, help="seed to use in nextpnr"
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)
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parser.add_argument(
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"--placer", choices=["sa", "heap"], help="which placer to use in nextpnr"
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)
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parser.add_argument(
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"--no-pll", help="disable pll -- this is easier to route, but may not work", action="store_true"
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)
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args = parser.parse_args()
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platform = Platform()
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soc = BaseSoC(platform, pnr_seed=args.seed, placer=args.placer, use_pll=not args.no_pll)
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builder = Builder(soc,
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output_dir="build", csr_csv="test/csr.csv",
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compile_software=False)
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vns = builder.build()
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soc.do_exit(vns)
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if __name__ == "__main__":
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main()
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366
workshop.py
366
workshop.py
@ -1,366 +0,0 @@
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#!/usr/bin/env python3
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# This variable defines all the external programs that this module
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# relies on. lxbuildenv reads this variable in order to ensure
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# the build will finish without exiting due to missing third-party
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# programs.
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LX_DEPENDENCIES = ["riscv", "icestorm"]
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# Import lxbuildenv to integrate the deps/ directory
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import lxbuildenv
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# "python.autoComplete.extraPaths": [
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# "deps/litescope",
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# "deps/litex",
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# "deps/litex_boards",
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# "deps/lxsocsupport",
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# "deps/migen",
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# "deps/valentyusb"
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# ]
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# Disable pylint's E1101, which breaks completely on migen
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#pylint:disable=E1101
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from migen import Module, Signal, Instance, ClockDomain, If
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from migen.fhdl.specials import TSTriple
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from migen.fhdl.bitcontainer import bits_for
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from migen.fhdl.structure import ClockSignal, ResetSignal, Replicate, Cat
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from litex_boards.partner.platforms.fomu_pvt import Platform
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from litex.soc.integration import SoCCore
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from litex.soc.integration.builder import Builder
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from litex.soc.integration.soc_core import csr_map_update
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from litex.soc.interconnect import wishbone
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from litex.soc.interconnect.csr import AutoCSR, CSRStatus, CSRStorage
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from lxsocsupport import up5kspram
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from valentyusb import usbcore
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from valentyusb.usbcore import io as usbio
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from valentyusb.usbcore.cpu import dummyusb
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import argparse
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class _CRG(Module):
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def __init__(self, platform, use_pll):
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clk48_raw = platform.request("clk48")
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clk12_raw = Signal()
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clk48 = Signal()
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clk12 = Signal()
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reset_delay = Signal(13, reset=4095)
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self.clock_domains.cd_por = ClockDomain()
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self.reset = Signal()
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_usb_12 = ClockDomain()
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self.clock_domains.cd_usb_48 = ClockDomain()
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platform.add_period_constraint(self.cd_usb_48.clk, 1e9/48e6)
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platform.add_period_constraint(self.cd_sys.clk, 1e9/12e6)
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platform.add_period_constraint(self.cd_usb_12.clk, 1e9/12e6)
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platform.add_period_constraint(clk48, 1e9/48e6)
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platform.add_period_constraint(clk48_raw, 1e9/48e6)
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platform.add_period_constraint(clk12_raw, 1e9/12e6)
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# POR reset logic- POR generated from sys clk, POR logic feeds sys clk
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# reset.
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self.comb += [
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self.cd_por.clk.eq(self.cd_sys.clk),
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self.cd_sys.rst.eq(reset_delay != 0),
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self.cd_usb_12.rst.eq(reset_delay != 0),
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]
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if use_pll:
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# Divide clk48 down to clk12, to ensure they're synchronized.
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# By doing this, we avoid needing clock-domain crossing.
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clk12_counter = Signal(2)
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self.clock_domains.cd_usb_48_raw = ClockDomain()
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platform.add_period_constraint(self.cd_usb_48_raw.clk, 1e9/48e6)
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# POR reset logic- POR generated from sys clk, POR logic feeds sys clk
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# reset.
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self.comb += [
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self.cd_usb_48.rst.eq(reset_delay != 0),
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]
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self.comb += self.cd_usb_48_raw.clk.eq(clk48_raw)
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self.comb += self.cd_usb_48.clk.eq(clk48)
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self.sync.usb_48_raw += clk12_counter.eq(clk12_counter + 1)
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self.comb += clk12_raw.eq(clk12_counter[1])
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self.specials += Instance(
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"SB_GB",
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i_USER_SIGNAL_TO_GLOBAL_BUFFER=clk12_raw,
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o_GLOBAL_BUFFER_OUTPUT=clk12,
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)
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self.specials += Instance(
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"SB_PLL40_CORE",
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# Parameters
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p_DIVR = 0,
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p_DIVF = 3,
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p_DIVQ = 2,
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p_FILTER_RANGE = 1,
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p_FEEDBACK_PATH = "PHASE_AND_DELAY",
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p_DELAY_ADJUSTMENT_MODE_FEEDBACK = "FIXED",
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p_FDA_FEEDBACK = 15,
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p_DELAY_ADJUSTMENT_MODE_RELATIVE = "FIXED",
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p_FDA_RELATIVE = 0,
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p_SHIFTREG_DIV_MODE = 1,
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p_PLLOUT_SELECT = "SHIFTREG_0deg",
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p_ENABLE_ICEGATE = 0,
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# IO
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i_REFERENCECLK = clk12,
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o_PLLOUTGLOBAL = clk48,
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i_BYPASS = 0,
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i_RESETB = 1,
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)
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else:
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self.specials += Instance(
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"SB_GB",
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i_USER_SIGNAL_TO_GLOBAL_BUFFER=clk48_raw,
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o_GLOBAL_BUFFER_OUTPUT=clk48,
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)
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self.comb += self.cd_usb_48.clk.eq(clk48)
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clk12_counter = Signal(2)
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self.sync.usb_48 += clk12_counter.eq(clk12_counter + 1)
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self.comb += clk12_raw.eq(clk12_counter[1])
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self.specials += Instance(
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"SB_GB",
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i_USER_SIGNAL_TO_GLOBAL_BUFFER=clk12_raw,
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o_GLOBAL_BUFFER_OUTPUT=clk12,
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)
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self.comb += self.cd_sys.clk.eq(clk12)
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self.comb += self.cd_usb_12.clk.eq(clk12)
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self.sync.por += \
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If(reset_delay != 0,
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reset_delay.eq(reset_delay - 1)
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)
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self.specials += AsyncResetSynchronizer(self.cd_por, self.reset)
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class PicoRVSpi(Module, AutoCSR):
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def __init__(self, platform, pads, size=2*1024*1024):
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self.size = size
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self.bus = bus = wishbone.Interface()
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self.reset = Signal()
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self.cfg1 = CSRStorage(size=8)
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self.cfg2 = CSRStorage(size=8)
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self.cfg3 = CSRStorage(size=8)
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self.cfg4 = CSRStorage(size=8, reset=0x80)
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self.stat1 = CSRStatus(size=8)
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self.stat2 = CSRStatus(size=8)
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self.stat3 = CSRStatus(size=8)
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self.stat4 = CSRStatus(size=8)
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cfg = Signal(32)
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cfg_we = Signal(4)
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cfg_out = Signal(32)
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self.comb += [
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cfg.eq(Cat(self.cfg1.storage, self.cfg2.storage, self.cfg3.storage, self.cfg4.storage)),
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cfg_we.eq(Cat(self.cfg1.re, self.cfg2.re, self.cfg3.re, self.cfg4.re)),
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self.stat1.status.eq(cfg_out[0:8]),
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self.stat2.status.eq(cfg_out[8:16]),
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self.stat3.status.eq(cfg_out[16:24]),
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self.stat4.status.eq(cfg_out[24:32]),
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]
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mosi_pad = TSTriple()
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miso_pad = TSTriple()
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cs_n_pad = TSTriple()
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clk_pad = TSTriple()
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wp_pad = TSTriple()
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hold_pad = TSTriple()
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self.specials += mosi_pad.get_tristate(pads.mosi)
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self.specials += miso_pad.get_tristate(pads.miso)
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self.specials += cs_n_pad.get_tristate(pads.cs_n)
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self.specials += clk_pad.get_tristate(pads.clk)
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self.specials += wp_pad.get_tristate(pads.wp)
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self.specials += hold_pad.get_tristate(pads.hold)
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reset = Signal()
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self.comb += [
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reset.eq(ResetSignal() | self.reset),
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cs_n_pad.oe.eq(~reset),
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clk_pad.oe.eq(~reset),
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]
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flash_addr = Signal(24)
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mem_bits = bits_for(size)
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self.comb += flash_addr.eq(bus.adr[0:mem_bits-2] << 2),
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read_active = Signal()
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spi_ready = Signal()
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self.sync += [
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If(bus.stb & bus.cyc & ~read_active,
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read_active.eq(1),
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bus.ack.eq(0),
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)
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.Elif(read_active & spi_ready,
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read_active.eq(0),
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bus.ack.eq(1),
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)
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.Else(
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bus.ack.eq(0),
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read_active.eq(0),
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)
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]
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o_rdata = Signal(32)
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self.comb += bus.dat_r.eq(o_rdata)
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self.specials += Instance("spimemio",
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o_flash_io0_oe = mosi_pad.oe,
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o_flash_io1_oe = miso_pad.oe,
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o_flash_io2_oe = wp_pad.oe,
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o_flash_io3_oe = hold_pad.oe,
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o_flash_io0_do = mosi_pad.o,
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o_flash_io1_do = miso_pad.o,
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o_flash_io2_do = wp_pad.o,
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o_flash_io3_do = hold_pad.o,
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o_flash_csb = cs_n_pad.o,
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o_flash_clk = clk_pad.o,
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i_flash_io0_di = mosi_pad.i,
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i_flash_io1_di = miso_pad.i,
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i_flash_io2_di = wp_pad.i,
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i_flash_io3_di = hold_pad.i,
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i_resetn = ~reset,
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i_clk = ClockSignal(),
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i_valid = bus.stb & bus.cyc,
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o_ready = spi_ready,
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i_addr = flash_addr,
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o_rdata = o_rdata,
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i_cfgreg_we = cfg_we,
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i_cfgreg_di = cfg,
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o_cfgreg_do = cfg_out,
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)
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platform.add_source("rtl/spimemio.v")
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class BaseSoC(SoCCore):
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csr_peripherals = [
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"ddrphy",
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# "dna",
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"xadc",
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"cpu_or_bridge",
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]
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SoCCore.csr_map = {
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"ctrl": 0, # provided by default (optional)
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"crg": 1, # user
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"uart_phy": 2, # provided by default (optional)
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"uart": 3, # provided by default (optional)
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"identifier_mem": 4, # provided by default (optional)
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"timer0": 5, # provided by default (optional)
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"cpu_or_bridge": 8,
|
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"usb": 9,
|
||||
"picorvspi": 10,
|
||||
"touch": 11,
|
||||
"reboot": 12,
|
||||
"rgb": 13,
|
||||
"version": 14,
|
||||
}
|
||||
|
||||
mem_map = {
|
||||
"spiflash": 0x20000000, # (default shadow @0xa0000000)
|
||||
}
|
||||
mem_map.update(SoCCore.mem_map)
|
||||
|
||||
def __init__(self, platform, output_dir="build", placer=None, pnr_seed=0, use_pll=True, **kwargs):
|
||||
clk_freq = int(12e6)
|
||||
self.output_dir = output_dir
|
||||
self.submodules.crg = _CRG(platform, use_pll=use_pll)
|
||||
SoCCore.__init__(self, platform, clk_freq,
|
||||
cpu_type=None, cpu_variant=None,
|
||||
integrated_sram_size=0, with_uart=False,
|
||||
**kwargs)
|
||||
|
||||
# SPRAM- UP5K has single port RAM, might as well use it as SRAM to
|
||||
# free up scarce block RAM.
|
||||
spram_size = 128*1024
|
||||
self.submodules.spram = up5kspram.Up5kSPRAM(size=spram_size)
|
||||
self.register_mem("sram", 0x10000000, self.spram.bus, spram_size)
|
||||
|
||||
# Add a simple bit-banged SPI Flash module based on PicoRVSpi
|
||||
spi_pads = platform.request("spiflash")
|
||||
self.submodules.picorvspi = PicoRVSpi(platform, spi_pads)
|
||||
self.register_mem("spiflash", self.mem_map["spiflash"],
|
||||
self.picorvspi.bus, size=self.picorvspi.size)
|
||||
|
||||
usb_pads = platform.request("usb")
|
||||
usb_iobuf = usbio.IoBuf(usb_pads.d_p, usb_pads.d_n, usb_pads.pullup)
|
||||
self.submodules.usb = dummyusb.DummyUsb(usb_iobuf, debug=True)
|
||||
self.add_wb_master(self.usb.debug_bridge.wishbone)
|
||||
|
||||
if hasattr(self, "cpu"):
|
||||
self.cpu.use_external_variant("rtl/2-stage-1024-cache.v")
|
||||
self.copy_memory_file("2-stage-1024-cache.v_toplevel_RegFilePlugin_regFile.bin")
|
||||
bios_size = 0x8000
|
||||
kwargs['cpu_reset_address']=self.mem_map["spiflash"]+platform.gateware_size
|
||||
self.add_memory_region("rom", kwargs['cpu_reset_address'], bios_size)
|
||||
self.add_constant("ROM_DISABLE", 1)
|
||||
self.flash_boot_address = self.mem_map["spiflash"]+platform.gateware_size+bios_size
|
||||
self.add_memory_region("user_flash",
|
||||
self.flash_boot_address,
|
||||
# Leave a grace area- possible one-by-off bug in add_memory_region?
|
||||
# Possible fix: addr < origin + length - 1
|
||||
platform.spiflash_total_size - (self.flash_boot_address - self.mem_map["spiflash"]) - 0x100)
|
||||
|
||||
# Add "-relut -dffe_min_ce_use 4" to the synth_ice40 command.
|
||||
# The "-reult" adds an additional LUT pass to pack more stuff in,
|
||||
# and the "-dffe_min_ce_use 4" flag prevents Yosys from generating a
|
||||
# Clock Enable signal for a LUT that has fewer than 4 flip-flops.
|
||||
# This increases density, and lets us use the FPGA more efficiently.
|
||||
platform.toolchain.nextpnr_yosys_template[2] += " -relut -dffe_min_ce_use 5"
|
||||
|
||||
# Allow us to set the nextpnr seed
|
||||
platform.toolchain.nextpnr_build_template[1] += " --seed " + str(pnr_seed)
|
||||
|
||||
if placer is not None:
|
||||
platform.toolchain.nextpnr_build_template[1] += " --placer {}".format(placer)
|
||||
|
||||
def copy_memory_file(self, src):
|
||||
import os
|
||||
from shutil import copyfile
|
||||
if not os.path.exists(self.output_dir):
|
||||
os.mkdir(self.output_dir)
|
||||
if not os.path.exists(os.path.join(self.output_dir, "gateware")):
|
||||
os.mkdir(os.path.join(self.output_dir, "gateware"))
|
||||
copyfile(os.path.join("rtl", src), os.path.join(self.output_dir, "gateware", src))
|
||||
|
||||
def main():
|
||||
parser = argparse.ArgumentParser(
|
||||
description="Build Fomu Main Gateware")
|
||||
parser.add_argument(
|
||||
"--seed", default=0, help="seed to use in nextpnr"
|
||||
)
|
||||
parser.add_argument(
|
||||
"--placer", choices=["sa", "heap"], help="which placer to use in nextpnr"
|
||||
)
|
||||
args = parser.parse_args()
|
||||
|
||||
platform = Platform()
|
||||
soc = BaseSoC(platform, pnr_seed=args.seed, placer=args.placer)
|
||||
builder = Builder(soc,
|
||||
output_dir="build", csr_csv="test/csr.csv",
|
||||
compile_software=False)
|
||||
vns = builder.build()
|
||||
soc.do_exit(vns)
|
||||
|
||||
if __name__ == "__main__":
|
||||
main()
|
||||
Loading…
Reference in New Issue
Block a user