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17
chisel/blink/.gitignore
vendored
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17
chisel/blink/.gitignore
vendored
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# Verilog/SystemVerilog generated from src/Blink.scala
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/Blink.sv
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/Blink.v
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# Annotations for the firrtl compiler, also generated from src/Blink.scala
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/Blink.anno.json
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# Intermediate representation of the circuit generated from src/Blink.scala
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/Blink.fir
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# IntelliJ IDE folder
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/.idea/
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# Scala build artifacts
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target/
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# same as for the verilog example
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blink.json
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blink.asc
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blink.bit
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blink.dfu
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63
chisel/blink/Makefile
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63
chisel/blink/Makefile
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# Simple Fomu Makefile
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# --------------------
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# This Makefile shows the steps to generate a DFU loadable image onto
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# Fomu hacker board.
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include ../../board.mk
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# Default target: run all required targets to build the DFU image.
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all: blink.dfu
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@true
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.DEFAULT: all
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# Call sbt to generate the Blink.sv from Chisel.
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# Please note that in general, it is a lot faster to
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# start `sbt` once and then to run `run` on the `sbt`
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# command line every time you want to rebuild the verilog.
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# Unfortunately `sbt` start up times are notoriously bad :(
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Blink.sv: src/Blink.scala build.sbt
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sbt "run $(FOMU_REV)"
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# Use *Yosys* to generate the synthesized netlist.
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# This is called the **synthesis** and **tech mapping** step.
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blink.json: Blink.sv
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yosys \
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$(YOSYSFLAGS) \
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-p 'synth_ice40 -top Blink -json blink.json' Blink.sv
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# Use **nextpnr** to generate the FPGA configuration.
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# This is called the **place** and **route** step.
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blink.asc: blink.json
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nextpnr-ice40 \
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$(PNRFLAGS) \
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--json blink.json \
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--asc blink.asc
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# Use icepack to convert the FPGA configuration into a "bitstream" loadable onto the FPGA.
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# This is called the bitstream generation step.
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blink.bit: blink.asc
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icepack blink.asc blink.bit
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# Use dfu-suffix to generate the DFU image from the FPGA bitstream.
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blink.dfu: blink.bit
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cp blink.bit blink.dfu
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dfu-suffix -v 1209 -p 70b1 -a blink.dfu
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# Use df-util to load the DFU image onto the Fomu.
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load: blink.dfu
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dfu-util -D blink.dfu
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.PHONY: load
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# Cleanup the generated files.
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clean:
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-rm -f Blink.fir
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-rm -f Blink.anno.json
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-rm -f Blink.sv
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-rm -f blink.json # Generate netlist
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-rm -f blink.asc # FPGA configuration
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-rm -f blink.bit # FPGA bitstream
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-rm -f blink.dfu # DFU image loadable onto the Fomu
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.PHONY: clean
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6
chisel/blink/build.sbt
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6
chisel/blink/build.sbt
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name := "fomu-blink"
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version := "0.1"
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scalaVersion := "2.12.8"
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libraryDependencies += "edu.berkeley.cs" %% "chisel3" % "3.4.0"
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scalaSource in Compile := baseDirectory.value / "src"
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scalaSource in Test := baseDirectory.value / "test"
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1
chisel/blink/project/build.properties
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1
chisel/blink/project/build.properties
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sbt.version=1.3.13
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83
chisel/blink/src/Blink.scala
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83
chisel/blink/src/Blink.scala
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import chisel3._
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import chisel3.experimental._
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import chisel3.stage.ChiselStage
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import firrtl.annotations.PresetAnnotation
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class Blink(rev: String) extends RawModule {
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val clki = IO(Input(Clock()))
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val rgb0 = IO(Output(Bool()))
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val rgb1 = IO(Output(Bool()))
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val rgb2 = IO(Output(Bool()))
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val usb_dp = IO(Output(Bool()))
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val usb_dn = IO(Output(Bool()))
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val usb_dp_pu = IO(Output(Bool()))
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usb_dp := false.B
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usb_dn := false.B
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usb_dp_pu := false.B
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// initialize registers to their reset value when the bitstream is programmed since there is no reset wire
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val reset = IO(Input(AsyncReset()))
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annotate(new ChiselAnnotation {
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override def toFirrtl = PresetAnnotation(reset.toTarget)
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})
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// clock buffer
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val clk_gb = Module(new SB_GB)
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clk_gb.USER_SIGNAL_TO_GLOBAL_BUFFER := clki
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val clk = clk_gb.GLOBAL_BUFFER_OUTPUT
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// led driver
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val leds = Module(new SB_RGBA_DRV)
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leds.CURREN := true.B
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leds.RGBLEDEN := true.B
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rgb0 := leds.RGB0
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rgb1 := leds.RGB1
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rgb2 := leds.RGB2
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// Now that we have set up the clock and reset, we define a scope
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// in which all registers and modules will automatically use it.
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chisel3.withClockAndReset(clk, reset) {
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val (red, green, blue) = rev.toLowerCase match {
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case "hacker" => (leds.RGB2PWM, leds.RGB1PWM, leds.RGB0PWM)
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case "pvt" => (leds.RGB1PWM, leds.RGB0PWM, leds.RGB2PWM)
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case other => throw new RuntimeException(s"Unsupported device: $other")
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}
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val counter = RegInit(0.U(26.W))
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counter := counter + 1.U
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red := counter(24)
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green := counter(23)
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blue := counter(25)
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}
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}
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class SB_GB extends ExtModule {
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val USER_SIGNAL_TO_GLOBAL_BUFFER = IO(Input(Clock()))
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val GLOBAL_BUFFER_OUTPUT = IO(Output(Clock()))
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}
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class SB_RGBA_DRV extends ExtModule(Map(
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"CURRENT_MODE" -> "0b0",
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"RGB0_CURRENT" -> "0b000011",
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"RGB1_CURRENT" -> "0b000011",
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"RGB2_CURRENT" -> "0b000011",
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)) {
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val CURREN = IO(Input(Bool()))
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val RGBLEDEN = IO(Input(Bool()))
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val RGB0PWM = IO(Input(Bool()))
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val RGB1PWM = IO(Input(Bool()))
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val RGB2PWM = IO(Input(Bool()))
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val RGB0 = IO(Output(Bool()))
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val RGB1 = IO(Output(Bool()))
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val RGB2 = IO(Output(Bool()))
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}
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// This main function reads in the version (pvt or hacker) and generates SystemVerilog from our Chisel design.
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object VerilogGenerator extends App {
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val rev = args.headOption.getOrElse("pvt")
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(new ChiselStage).emitSystemVerilog(new Blink(rev))
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}
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