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mixed-hdl: remove '-q' from yosys call

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Co-authored-by: T. Meissner <programming@goodcleanfun.de>
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umarcor 2020-10-13 21:26:16 +02:00
parent 568fdcc607
commit ed9c146652
1 changed files with 1 additions and 1 deletions
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mixed-hdl/blink/Makefile
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@ -29,7 +29,7 @@ blink.json: $(VHDL_SYN_FILES) $(VERILOG_SYN_FILES)
"$(GHDLSYNTH) $(GHDL_FLAGS) $(VHDL_SYN_FILES) -e; \
synth_ice40 \
-top Fomu_Blink \
-json $@" -q $(VERILOG_SYN_FILES) 2>&1 | tee yosys-report.txt
-json $@" $(VERILOG_SYN_FILES) 2>&1 | tee yosys-report.txt
# Use **nextpnr** to generate the FPGA configuration.
# This is called the **place** and **route** step.