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mixed-hdl: remove '-q' from yosys call
Co-authored-by: T. Meissner <programming@goodcleanfun.de>
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@ -29,7 +29,7 @@ blink.json: $(VHDL_SYN_FILES) $(VERILOG_SYN_FILES)
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"$(GHDLSYNTH) $(GHDL_FLAGS) $(VHDL_SYN_FILES) -e; \
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synth_ice40 \
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-top Fomu_Blink \
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-json $@" -q $(VERILOG_SYN_FILES) 2>&1 | tee yosys-report.txt
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-json $@" $(VERILOG_SYN_FILES) 2>&1 | tee yosys-report.txt
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# Use **nextpnr** to generate the FPGA configuration.
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# This is called the **place** and **route** step.
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