Merge pull request #476 from umarcor/ci/hdl

create subdir 'hdl'

.github/tests.sh

@@ -29,7 +29,7 @@ echo '::endgroup::'
 echo '::group::Verilog Blink example'
 (
 	set -x
-	cd verilog/blink
+	cd hdl/verilog/blink
 	make FOMU_REV=pvt
 	file blink.dfu
 )
@@ -38,7 +38,7 @@ echo '::endgroup::'
 echo '::group::Verilog Blink (expanded) example for Hacker board'
 (
 	set -x
-	cd verilog/blink-expanded
+	cd hdl/verilog/blink-expanded
 	make FOMU_REV=hacker
 	file blink.dfu
 )
@@ -47,7 +47,7 @@ echo '::endgroup::'
 echo '::group::Verilog Blink (expanded) example for PVT board'
 (
 	set -x
-	cd verilog/blink-expanded
+	cd hdl/verilog/blink-expanded
 	make FOMU_REV=pvt
 	file blink.dfu
 )
@@ -55,9 +55,8 @@ echo '::endgroup::'
 
 echo '::group::VHDL Blink example'
 (
-
 	set -x
-	cd vhdl/blink
+	cd hdl/vhdl/blink
 	make FOMU_REV=pvt
 	file blink.dfu
 )
@@ -65,9 +64,8 @@ echo '::endgroup::'
 
 echo '::group::Mixed HDL Blink example'
 (
-
 	set -x
-	cd mixed-hdl/blink
+	cd hdl/mixed/blink
 	make FOMU_REV=pvt
 	file blink.dfu
 )
@@ -93,7 +91,6 @@ echo '::endgroup::'
 
 echo '::group::Migen Blink example for PVT board'
 (
-
 	set -x
 	cd migen
 	FOMU_REV=pvt ./blink.py
@@ -104,7 +101,6 @@ echo '::endgroup::'
 
 echo '::group::Migen Blink (expanded) example for PVT board'
 (
-
 	set -x
 	cd migen
 	FOMU_REV=pvt ./blink-expanded.py

chisel/blink/Makefile

@@ -3,7 +3,7 @@
 # This Makefile shows the steps to generate a DFU loadable image onto
 # Fomu hacker board.
 
-include ../../board.mk
+include ../../hdl/board.mk
 
 # Default target: run all required targets to build the DFU image.
 all: blink.dfu

docs/mixed-hdl.rst

@@ -11,11 +11,11 @@ Mixed HDL on Fomu
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
 The canonical “Hello, world!” of hardware is to blink a LED. The
-directory ``mixedhdl/blink`` contains a VHDL + Verilog example of a blink
+directory ``hdl/mixed/blink`` contains a VHDL + Verilog example of a blink
 project. This takes the 48 MHz clock and divides it down by a large
 number so you get an on/off pattern.
 
-Enter the ``mixedhdl/blink`` directory and build the demo by using ``make``:
+Enter the ``hdl/mixed/blink`` directory and build the demo by using ``make``:
 
 .. session:: shell-session
 
@@ -65,7 +65,7 @@ You can then load ``blink.dfu`` onto Fomu by using ``make load`` or the same
 ``dfu-util -D`` command we’ve been using so far. You should see a blinking pattern of
 varying color on your Fomu, indicating your bitstream was successfully loaded.
 
-If you take a closer look at the sources in ``mixedhdl/blink``, you will find that
+If you take a closer look at the sources in ``hdl/mixed/blink``, you will find that
 modules/components ``blink`` and ``clkgen`` are written both in VHDL and Verilog.
 The Makefile uses ``blink.vhd`` and ``clkgen.v`` by default. However, any of the
 following cases produce the same result:

docs/verilog.rst

@@ -7,11 +7,11 @@ Verilog on Fomu
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
 The canonical “Hello, world!” of hardware is to blink a LED. The
-directory ``verilog/blink`` contains a Verilog example of a blink
+directory ``hdl/verilog/blink`` contains a Verilog example of a blink
 project. This takes the 48 MHz clock and divides it down by a large
 number so you get an on/off pattern.
 
-Enter the ``verilog/blink`` directory and build the demo by using ``make``:
+Enter the ``hdl/verilog/blink`` directory and build the demo by using ``make``:
 
 **Make sure you set the** ``FOMU_REV`` **value to match your hardware!** See :ref:`required-hardware`.
 
@@ -67,7 +67,7 @@ varying color on your Fomu, indicating your bitstream was successfully loaded.
 Reading Input
 ^^^^^^^^^^^^^
 
-There is another small example in ``verilog/blink-expanded`` which shows
+There is another small example in ``hdl/verilog/blink-expanded`` which shows
 how to read out some given pins. Build and flash it like described above
 and see if you can enable the blue and red LED by shorting pins 1+2 or 3+4
 on your Fomu (the pins are the exposed contacts sticking out of the USB port).

docs/vhdl.rst

@@ -12,11 +12,11 @@ VHDL on Fomu
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
 The canonical “Hello, world!” of hardware is to blink a LED. The
-directory ``vhdl/blink`` contains a VHDL example of a blink
+directory ``hdl/vhdl/blink`` contains a VHDL example of a blink
 project. This takes the 48 MHz clock and divides it down by a large
 number so you get an on/off pattern.
 
-Enter the ``vhdl/blink`` directory and build the demo by using ``make``:
+Enter the ``hdl/vhdl/blink`` directory and build the demo by using ``make``:
 
 **Make sure you set the** ``FOMU_REV`` **value to match your hardware!** See :ref:`required-hardware`.
 
@@ -52,7 +52,7 @@ Enter the ``vhdl/blink`` directory and build the demo by using ``make``:
    Info: [ 79081,  79634) |**
    Info: [ 79634,  80187) |***
    22 warnings, 0 errors
-   docker run --rm -v //t/fomu/fomu-workshop/vhdl/blink/../..://src -w //src/vhdl/blink ghdl/synth:icestorm icepack blink.asc blink.bit
+   docker run --rm -v //t/fomu/fomu-workshop/hdl/vhdl/blink/../..://src -w //src/hdl/vhdl/blink ghdl/synth:icestorm icepack blink.asc blink.bit
    cp blink.bit blink.dfu
    dfu-suffix -v 1209 -p 70b1 -a blink.dfu
    dfu-suffix (dfu-util) 0.9

hdl/board.mk

@@ -2,7 +2,7 @@
 # require different configurations for yosys and nextpnr.
 # Configuration is performed by setting the environment variable FOMU_REV accordingly.
 
-PCF_PATH   ?= ../../pcf
+PCF_PATH   ?= ../../../pcf
 
 ifeq ($(FOMU_REV),evt1)
 YOSYSFLAGS ?= -D EVT=1 -D EVT1=1 -D HAVE_PMOD=1

hdl/mixed/blink/Makefile

@@ -1,11 +1,11 @@
 include ../../board.mk
 
 # VHDL top with instantiated Verilog
-VHDL_SYN_FILES = ../../vhdl/sb_ice40_components.vhd blink.vhd
+VHDL_SYN_FILES = ../../sb_ice40_components.vhd blink.vhd
 VERILOG_SYN_FILES = clkgen.v
 
 # Verilog top with instantiated VHDL
-#VHDL_SYN_FILES = ../../vhdl/sb_ice40_components.vhd clkgen.vhd
+#VHDL_SYN_FILES = ../../sb_ice40_components.vhd clkgen.vhd
 #VERILOG_SYN_FILES = blink.v
 
 GHDL_FLAGS += --std=08

hdl/vhdl/blink/Makefile

@@ -1,6 +1,6 @@
 include ../../board.mk
 
-VHDL_SYN_FILES = ../sb_ice40_components.vhd blink.vhd
+VHDL_SYN_FILES = ../../sb_ice40_components.vhd blink.vhd
 
 GHDL_FLAGS += --std=08
 GHDL      ?= ghdl