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661 Commits 7 Branches 2 Tags 28 MiB
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23 Commits

Author SHA1 Message Date
Patrick Huesmann
fa2140eead Set GHDL_PREFIX for VHDL examples 2021-11-29 16:52:07 +01:00
daurnimator
d81b674ec6
Revert "ci: skip RISC-V Zig Example test on macOS (#516)" 
This reverts commit e25109ad97.
 2021-08-01 22:26:21 +10:00
Unai Martinez-Corral
9818174c87
docs/migen: fix binary path (#510) 2021-07-30 17:36:27 +01:00
Johan Euphrosine
54cb453ce4 github/tests.sh: fix litex tests 
- fix filename
- set fatal error flag
- clean up build directory
 2021-07-31 00:12:55 +09:00
Unai Martinez-Corral
e25109ad97
ci: skip RISC-V Zig Example test on macOS (#516) 2021-07-29 23:10:19 +02:00
umarcor
da89f3da6c tests/litex: add workflow_rgb example for PVT 2021-07-05 14:29:13 +02:00
umarcor
8e89c5d825 ci: run hdl tests on all-in-one container 2021-05-19 19:30:04 +02:00
umarcor
4a5caa37b5 create subdir 'hdl' 2021-05-19 16:24:52 +02:00
Kevin Laeufer
7bfdd33891
ci: add Chisel Blink, use Action setup-scala (#384) 2020-11-20 22:03:52 +01:00
umarcor
48ee3ce3ac ci: add Migen examples to tests.sh 2020-10-15 18:30:58 +02:00
umarcor
b2601169f6 add mixed-hdl/blink 2020-10-12 19:58:46 +02:00
umarcor
5df387b987 get-toolchain: use 'nightly' toolchain in CI 2020-10-12 18:48:52 +02:00
umarcor
21bcde2bd3 add vhdl/blink 2020-10-12 18:48:52 +02:00
umarcor
b55ce813b8 test: preserve TOOLCHAIN_PATH, if set 2020-10-10 21:42:19 +02:00
umarcor
bf09e8c646 migrate from Travis CI to GitHub Actions 2020-10-05 15:45:41 +02:00
daurnimator
79baffc5a9
Test riscv-zig-blink from CI 2020-05-10 22:23:49 +10:00
Pascal Mainini
6a72aa9495 fix CI: add FOM_REV for make 2020-01-23 11:34:32 +01:00
Pascal Mainini
7bf2a4560f fix CI 2020-01-23 11:27:50 +01:00
Tim 'mithro' Ansell
86973dc9c0 travis: Fix verilog testing. 2020-01-05 12:01:17 -08:00
Tim 'mithro' Ansell
b4b95511ed travis: Fix path and expanded example. 2020-01-05 12:01:17 -08:00
Tim 'mithro' Ansell
c3ee05a0e8 travis: Quieter output. 2020-01-05 12:01:17 -08:00
Tim 'mithro' Ansell
465f30630b travis: Extract toolchain and set PATH. 2020-01-05 12:01:17 -08:00
Tim 'mithro' Ansell
6b44db1cc9 travis: Build the current examples. 
- RISC-V CPU blink example
 - Basic Verilog Blink example
 - Extended Verilog Blink example for Hacker
 - Extended Verilog Blink example for PVT
 - LiteX example for Hacker
 - LiteX example for PVT
 2020-01-05 12:01:17 -08:00