umarcor
bf09e8c646
migrate from Travis CI to GitHub Actions
2020-10-05 15:45:41 +02:00
daurnimator
79baffc5a9
Test riscv-zig-blink from CI
2020-05-10 22:23:49 +10:00
Pascal Mainini
6a72aa9495
fix CI: add FOM_REV for make
2020-01-23 11:34:32 +01:00
Pascal Mainini
7bf2a4560f
fix CI
2020-01-23 11:27:50 +01:00
Tim 'mithro' Ansell
86973dc9c0
travis: Fix verilog testing.
2020-01-05 12:01:17 -08:00
Tim 'mithro' Ansell
b4b95511ed
travis: Fix path and expanded example.
2020-01-05 12:01:17 -08:00
Tim 'mithro' Ansell
c3ee05a0e8
travis: Quieter output.
2020-01-05 12:01:17 -08:00
Tim 'mithro' Ansell
465f30630b
travis: Extract toolchain and set PATH.
2020-01-05 12:01:17 -08:00
Tim 'mithro' Ansell
6b44db1cc9
travis: Build the current examples.
...
- RISC-V CPU blink example
- Basic Verilog Blink example
- Extended Verilog Blink example for Hacker
- Extended Verilog Blink example for PVT
- LiteX example for Hacker
- LiteX example for PVT
2020-01-05 12:01:17 -08:00