Merge 73cc0ef8d5 into af55dff1ff

docs: install and load sphinxcontrib.jquery and add build section to
readthedocs.yaml

.readthedocs.yml

@@ -5,6 +5,12 @@
 # Required
 version: 2
 
+build:
+  os: ubuntu-lts-latest
+  tools:
+    # Need to use mambaforge as miniconda runs out of memory on rtd.
+    python: mambaforge-latest
+
 # Build documentation in the docs/ directory with Sphinx
 sphinx:
   configuration: docs/conf.py

docs/conf.py

@@ -38,6 +38,7 @@ author = 'Tomu Project Authors'
 # ones.
 extensions = [
 #    'sphinx.ext.intersphinx',
+    'sphinxcontrib.jquery',
     'sphinx.ext.todo',
     'sphinx.ext.githubpages',
     'sphinx.ext.extlinks',

docs/environment.yml

@@ -4,7 +4,7 @@ channels:
 - conda-forge
 - defaults
 dependencies:
-- python=3.7
+- python
 - pip
 - pycairo
 - pango

docs/requirements.txt

@@ -1,5 +1,6 @@
 sphinx>=4.5.0
 sphinx-autobuild
+sphinxcontrib-jquery
 
 # Better looking Sphinx theme
 # sphinx_materialdesign_theme

hdl/sb_ice40_components.vhd

@@ -29,4 +29,64 @@ component  SB_RGBA_DRV
   );
 end component;
 
+-- SB_MAC16 DSP. Default values according to datasheet
+component SB_MAC16
+	generic (
+	NEG_TRIGGER : integer := 0;
+
+	A_REG : integer := 0;
+	B_REG : integer := 0;
+	C_REG : integer := 0;
+	D_REG : integer := 0;
+
+	TOP_8x8_MULT_REG : integer := 0;
+	BOT_8x8_MULT_REG : integer := 0;
+	PIPELINE_16x16_MULT_REG1 : integer := 0;
+	PIPELINE_16x16_MULT_REG2 : integer := 0;
+
+	TOPOUTPUT_SELECT : integer := 0;
+	TOPADDSUB_LOWERINPUT : integer := 0;
+	TOPADDSUB_UPPERINPUT : integer:= 0;
+	TOPADDSUB_CARRYSELECT : integer := 0;
+	BOTOUTPUT_SELECT : integer := 0;
+	BOTADDSUB_LOWERINPUT : integer := 0;
+	BOTADDSUB_UPPERINPUT : integer := 0;
+	BOTADDSUB_CARRYSELECT : integer := 0;
+	MODE_8x8 : integer := 0;
+	A_SIGNED : integer := 0;
+	B_SIGNED : integer := 0
+		);
+	port (
+	CLK: in std_logic;
+	CE: in std_logic := '1';
+
+	A: in std_logic_vector(15 downto 0) := (others => '0');
+	B: in std_logic_vector(15 downto 0) := (others => '0');
+	C: in std_logic_vector(15 downto 0) := (others => '0');
+	D: in std_logic_vector(15 downto 0) := (others => '0');
+
+	AHOLD : in std_logic := '0';
+	BHOLD : in std_logic := '0';
+	CHOLD : in std_logic := '0';
+	DHOLD : in std_logic := '0';
+
+	IRSTTOP : in std_logic := '0';
+	ORSTTOP : in std_logic := '0';
+
+	OLOADTOP : in std_logic := '0';
+	ADDSUBTOP : in std_logic := '0';
+	OHOLDTOP : in std_logic := '0';
+	IRSTBOT : in std_logic := '0';
+	ORSTBOT : in std_logic := '0';
+	OLOADBOT : in std_logic := '0';
+	ADDSUBBOT : in std_logic := '0';
+	OHOLDBOT : in std_logic := '0';
+
+	O: out std_logic_vector(31 downto 0);
+	CI : in std_logic := '0';
+	CO : out std_logic
+
+);
+end component;
+
 end components;