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81 lines
2.9 KiB
ReStructuredText
81 lines
2.9 KiB
ReStructuredText
.. _HDLs:mixed:
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Mixed HDL on Fomu
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-----------------
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.. HINT:: It is strongly suggested to get familiar with :ref:`HDLs:Verilog` and :ref:`HDLs:VHDL` examples before
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tinkering with these mixed language use cases.
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“Hello world!” - Blink a LED
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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The canonical “Hello, world!” of hardware is to blink a LED.
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The directory :repo:`hdl/mixed/blink <hdl/mixed/blink>` contains a VHDL + Verilog example of a blink project.
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This takes the 48 MHz clock and divides it down by a large number so you get an on/off pattern.
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Enter the :repo:`hdl/mixed/blink <hdl/mixed/blink>` directory and build the demo by using ``make``:
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.. session:: shell-session
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$ make FOMU_REV=$FOMU_REV
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...
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Info: Max frequency for clock 'clk_generator.clko': 73.26 MHz (PASS at 12.00 MHz)
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Info: Max delay posedge clk_generator.clko -> <async>: 3.15 ns
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Info: Slack histogram:
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Info: legend: * represents 1 endpoint(s)
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Info: + represents [1,1) endpoint(s)
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Info: [ 69683, 70208) |**
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Info: [ 70208, 70733) |
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Info: [ 70733, 71258) |**
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Info: [ 71258, 71783) |**
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Info: [ 71783, 72308) |**
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Info: [ 72308, 72833) |**
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Info: [ 72833, 73358) |
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Info: [ 73358, 73883) |**
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Info: [ 73883, 74408) |*
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Info: [ 74408, 74933) |**
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Info: [ 74933, 75458) |**
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Info: [ 75458, 75983) |*
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Info: [ 75983, 76508) |*
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Info: [ 76508, 77033) |**
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Info: [ 77033, 77558) |**
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Info: [ 77558, 78083) |*
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Info: [ 78083, 78608) |
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Info: [ 78608, 79133) |*************************
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Info: [ 79133, 79658) |**
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Info: [ 79658, 80183) |***
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22 warnings, 0 errors
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icepack blink.asc blink.bit
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cp blink.bit blink.dfu
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dfu-suffix -v 1209 -p 70b1 -a blink.dfu
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dfu-suffix (dfu-util) 0.9
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Copyright 2011-2012 Stefan Schmidt, 2013-2014 Tormod Volden
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This program is Free Software and has ABSOLUTELY NO WARRANTY
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Please report bugs to http://sourceforge.net/p/dfu-util/tickets/
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Suffix successfully added to file
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$
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You can then load ``blink.dfu`` onto Fomu by using ``make load`` or the same ``dfu-util -D`` command we’ve been using so
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far.
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You should see a blinking pattern of varying color on your Fomu, indicating your bitstream was successfully loaded.
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If you take a closer look at the sources in :repo:`hdl/mixed/blink <hdl/mixed/blink>`, you will find that
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modules/components ``blink`` and ``clkgen`` are written both in VHDL and Verilog.
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The :repo:`Makefile <hdl/mixed/blink/Makefile>` uses ``blink.vhd`` and ``clkgen.v`` by default.
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However, any of the following cases produce the same result:
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- ``blink.vhd`` + ``clkgen.v``
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- ``blink.v`` + ``clkgen.vhdl``
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- ``blink.vhd`` + ``clkgen.vhdl``
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- ``blink.v`` + ``clkgen.v``
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You can modify variables ``VHDL_SYN_FILES`` and ``VERILOG_SYN_FILES`` in the :repo:`Makefile <hdl/mixed/blink/Makefile>`
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for trying other combinations.
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For a better understanding, it is suggested to compare these modules with the single file solutions in
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:ref:`HDLs:Verilog` and :ref:`HDLs:VHDL`.
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