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All these point to 404s on the current workshop docs. Updated to point into hdl/ , except for migen which is top level
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75 lines
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.. _HDLs:
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Hardware Description Languages
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------------------------------
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The two most common **H**\ ardware **D**\ escription **L**\ anguages are Verilog and VHDL.
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As explained in :ref:`background:code-into-gates`, a *synthesis* tool is used for converting
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the human readable HDL into a netlist representation. The synthesis tool used in the Fomu
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toolchain is called ``yosys``. Once we have the netlist representation, a tool called
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``nextpnr`` performs an operation called *place and route* (PnR), which makes it something
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that will actually run on the FPGA. This is all done for you using the ``Makefiles`` in the
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subdirectories of any of the following examples: :repo:`verilog <hdl/verilog>`,
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:repo:`vhdl <hdl/vhdl>`, :repo:`mixed-hdl <hdl/mixed>`, or :repo:`migen <migen>`.
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.. NOTE::
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``nextpnr`` is timing-driven. This means that a design will be generated with a given
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clock domain guaranteed to perform fast enough, but sometimes it won't optimise further.
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When the ``make`` command runs ``nextpnr-ice40`` you will see something similar to the
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following:
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::
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Info: Max frequency for clock 'clk': 73.26 MHz (PASS at 12.00 MHz)
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This output example shows that we could run ``clk`` at up to 73.26
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MHz and it would still be stable (even though we only requested 12.00
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MHz). Note that there is some variation between designs depending on
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how the placer and router decided to lay things out, so your exact
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frequency numbers might be different from the ones shown in the code
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blocks of this documentation.
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.. IMPORTANT::
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As explained in :ref:`background:about-fomu`, Fomu implements its USB in a softcore, and
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the bitstream that runs on the FPGA must provide the ability to communicate over USB.
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That is a tradeoff for achieving such a tiny board size, which unfortunately makes
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it not straightforward to use non-trivial HDL designs. This is because
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I/O is very limited, hence, it is challenging to actually *see* whether the designs are
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behaving as expected. Ideally, a USB-to-UART core would be provided for users to instantiate
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in their HDL designs. Should you be interested in helping achieve it, `let us know! <https://github.com/im-tomu/fomu-workshop/issues/new>`_
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Meanwhile, :ref:`HDLs:migen` examples provide a working SoC that allows interacting
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through USB using a Wishbone Bus.
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.. figure:: _static/ice40-rgb.png
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:align: center
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:width: 600px
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:alt: iCE40 UltraLite and iCE40 UltraPlus RGB Port Level Diagram
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iCE40 UltraLite and iCE40 UltraPlus RGB Port Level Diagram.
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Regardless of the HDL language or higher abstraction programming language used for
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describing the design, all the examples in this workshop do use the *hard* RGB block
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for driving the LED on the board. It is defined as a Verilog module or VHDL component
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named ``SB_RGBA_DRV``.
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As shown in the block diagram from the datasheet, the RGB driver has five inputs
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(``CURREN``, ``RGBLEDEN``, ``RGB0PWM``, ``RGB1PWM``, and ``RGB2PWM``),
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and three outputs (``RGB0``, ``RGB1``, and ``RGB2``). It also has four parameters:
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``CURRENT_MODE``, ``RGB0_CURRENT``, ``RGB1_CURRENT``, and ``RGB2_CURRENT``. As a result,
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it allows driving the LEDs safely, by specifying the current limit for each of them.
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More information on this driver can be found in the `ICE40 LED Driver Usage Guide <_static/reference/FPGA-TN-1288-ICE40LEDDriverUsageGuide.pdf>`_.
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.. ATTENTION::
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Even though it is possible to drive the RGB outputs directly (i.e. without instantiating
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``SB_RGBA_DRV``), it is strongly discouraged, as it might damage the LEDs.
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Languages and generators
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========================
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.. toctree::
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verilog
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vhdl
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mixed-hdl
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migen
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icestudio
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