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https://github.com/im-tomu/fomu-workshop.git
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57 lines
2.5 KiB
ReStructuredText
57 lines
2.5 KiB
ReStructuredText
Fomu on IceStudio *Nightly*
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.. IMPORTANT:: Fomu is currently not supported in the stable releases
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of IceStudio. Development or `nightly <https://github.com/juanmard/icestudio/releases/tag/nightly>`_
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releases need to be used. Moreover, Apio needs to be updated from
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the git repository.
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NOTE: on GNU/Linux, first ``source ~/.icestudio/venv/bin/activate``.
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.. code-block:: shell
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pip install -U git+https://github.com/FPGAwars/apio.git@develop#egg=apio
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“Hello world!” - Blink a LED
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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The canonical “Hello, world!” of hardware is to blink a LED. The
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directory ``icestudio`` contains a Blinky example in ICE format.
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Moreover, ``Blinky_BoardTop.ice`` wraps Blinky, showcasing how
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to use the Design Under Test (DUT) as a black box.
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Open ``Blinky_BoardTop.ice`` from `Icestudio <https://juanmard.github.io/icestudio/>`_
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and use the buttons on the botton:
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.. image:: _static/icestudio/blinky_steps.png
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:width: 600 px
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:align: center
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:target: https://github.com/juanmard/icestudio
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0. Check that the **selected board** is the Fomu.
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- Click on the button with a 'microchip' icon, and a modal window will open.
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- There, select the device (UP5K) in the first dropdown list and the board (Fomu) in the second list.
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1. Click on the **Verify** button for checking the design.
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2. Click on the **Build** button for having the design exported to Verilog, synthesised, placed, routed and, finally, the bitstream generated.
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3. Click on the **Upload** for sending the bitstream to the board.
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4. After each of the steps is executed, the corresponding log can be shown through button **View command output**.
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You should see the rainbow pattern in the Fomu as soon as the *Upload*
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step is finished. However, that's just the beginning of the trip. You
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can navigate the hierarchy of the designs by double-clicking on the main
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block. Go as deep as you want, until you find raw Verilog code. As you
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can observe, ICE modules are fancy wrappers around the Verilog code from
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``verilog/blink``.
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Editing submodules is blocked by default, but you can unlock the feature
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with the red button on the botton left. Do the modifications you wish,
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then save the changes and go back to the top. There is a 'Home' button
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on the bottom left for jumping to the root of the design straightaway.
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From the top, you can verify, build and upload the design again.
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Find more info about features of IceStudio (such as collections or
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plugins) in the `documentation <https://juanmard.github.io/icestudio/index.html>`_.
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