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49 lines
1.7 KiB
ReStructuredText
49 lines
1.7 KiB
ReStructuredText
.. _HDLs:
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Hardware Description Languages
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------------------------------
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The two most common **H**\ ardware **D**\ escription **L**\ anguages are
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Verilog and VHDL.
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.. NOTE:: The pre-built toolchain we are releasing supports Verilog only.
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However, `GHDL <https://github.com/ghdl>`_ can be usable as a VHDL frontend
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for Yosys. See `ghdl-yosys-plugin <https://github.com/ghdl/ghdl-yosys-plugin>`_.
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When writing HDL, a tool called ``yosys`` is used to convert the
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human readable verilog into a netlist representation, this is called
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*synthesis*. Once we have the netlist representation, a tool called
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``nextpnr`` performs an operation called *place and route* (P&R) which
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makes it something that will actually run on the FPGA. This is all
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done for you using the ``Makefiles`` in the subdirectories of ``verilog``
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or ``vhdl``.
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A big feature of ``nextpnr`` over its predecessor, is the fact that
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it is timing-driven. This means that a design will be generated with
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a given clock domain guaranteed to perform fast enough.
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When the ``make`` command runs ``nextpnr-ice40`` you will see something
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similar included in the output:
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::
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Info: Max frequency for clock 'clk': 73.26 MHz (PASS at 12.00 MHz)
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This output example shows that we could run ``clk`` at up to 73.26
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MHz and it would still be stable (even though we only requested 12.00
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MHz). Note that there is some variation between designs depending on
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how the placer and router decided to lay things out, so your exact
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frequency numbers might be different from the ones shown in the code
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blocks of this documentation.
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Languages and generators
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========================
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.. toctree::
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verilog
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vhdl
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mixed-hdl
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migen
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icestudio
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