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https://github.com/im-tomu/fomu-workshop.git
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187 lines
6.5 KiB
ReStructuredText
187 lines
6.5 KiB
ReStructuredText
Migen and LiteX
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---------------
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.. _hello-world---blink-an-led-1:
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“Hello world!” - Blink a LED
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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FIXME: Add the Migen and LiteX equivalent for the Verilog above.
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Wishbone Bus
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^^^^^^^^^^^^
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Migen is an HDL embedded in Python, and LiteX provides us with a
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Wishbone abstraction layer. There really is no reason we need to include
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a CPU with our design, but we can still reuse the USB Wishbone bridge in
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order to write HDL code.
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We can use ``DummyUsb`` to respond to USB requests and bridge USB to
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Wishbone, and rely on LiteX to generate registers and wire them to
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hardware signals. We can still use ``wishbone-tool`` to read and write
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memory, and with a wishbone bridge we can actually have code running on
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our local system that can read and write memory on Fomu.
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Go to the ``litex`` directory and build the design;
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.. session:: shell-session
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$ python3 workshop.py --board $FOMU_REV
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lxbuildenv: v2019.8.19.1 (run .\workshop.py --lx-help for help)
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lxbuildenv: Skipping git configuration because "skip-git" was found in LX_CONFIGURATION
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lxbuildenv: To fetch from git, run .\workshop.py --placer heap --lx-check-git
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Warning: Wire top.basesoc_adr has an unprocessed 'init' attribute.
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Warning: Wire top.basesoc_bus_wishbone_ack has an unprocessed 'init' attribute.
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Warning: Wire top.basesoc_bus_wishbone_dat_r has an unprocessed 'init' attribute.
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...
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Info: Device utilisation:
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Info: ICESTORM_LC: 1483/ 5280 28%
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Info: ICESTORM_RAM: 1/ 30 3%
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Info: SB_IO: 4/ 96 4%
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Info: SB_GB: 8/ 8 100%
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Info: ICESTORM_PLL: 1/ 1 100%
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Info: SB_WARMBOOT: 0/ 1 0%
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Info: ICESTORM_DSP: 0/ 8 0%
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Info: ICESTORM_HFOSC: 0/ 1 0%
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Info: ICESTORM_LFOSC: 0/ 1 0%
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Info: SB_I2C: 0/ 2 0%
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Info: SB_SPI: 0/ 2 0%
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Info: IO_I3C: 0/ 2 0%
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Info: SB_LEDDA_IP: 0/ 1 0%
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Info: SB_RGBA_DRV: 0/ 1 0%
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Info: ICESTORM_SPRAM: 4/ 4 100%
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...
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Info: [ 55530, 59533) |********+
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Info: [ 59533, 63536) |************************************************+
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Info: [ 63536, 67539) |******************************+
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Info: [ 67539, 71542) |*************+
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Info: [ 71542, 75545) |********************+
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Info: [ 75545, 79548) |************************************************************
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5 warnings, 0 errors
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$
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Load it onto Fomu:
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.. session:: shell-session
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$ dfu-util -D build/gateware/top.dfu
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dfu-util 0.8
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Copyright 2005-2009 Weston Schmidt, Harald Welte and OpenMoko Inc.
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Copyright 2010-2014 Tormod Volden and Stefan Schmidt
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This program is Free Software and has ABSOLUTELY NO WARRANTY
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Please report bugs to dfu-util@lists.gnumonks.org
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Opening DFU capable USB device...
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ID 1209:5bf0
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Run-time device DFU version 0101
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Claiming USB DFU Interface...
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Setting Alternate Setting #0 ...
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Determining device status: state = dfuIDLE, status = 0
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dfuIDLE, continuing
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DFU mode device DFU version 0101
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Device returned transfer size 1024
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Copying data from PC to DFU device
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Download [=========================] 100% 104090 bytes
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Download done.
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state(7) = dfuMANIFEST, status(0) = No error condition is present
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state(8) = dfuMANIFEST-WAIT-RESET, status(0) = No error condition is present
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Done!
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$
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If you get an error message about missing modules, check you have all
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submodules cloned and setup with;
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.. session:: shell-session
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$ git submodule update --recursive --init
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$
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Take a look at ``build/csr.csv``. This describes the various regions
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present in our design. You can see
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``memory_region,sram,0x10000000,131072``, which indicates the RAM is 128
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kilobytes long and is located at ``0x10000000``, just as when we had a
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CPU. You can also see the timer, which is a feature that comes as part
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of LiteX. Let’s try reading and writing RAM:
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.. session:: shell-session
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$ wishbone-tool 0x10000000
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Value at 10000000: 0baf801e
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$ wishbone-tool 0x10000000 0x98765432
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$ wishbone-tool 0x10000000
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Value at 10000000: 98765432
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$
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Aside from that, there’s not much we can *do* with this design. But
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there’s a lot of infrastructure there. So let’s add something (see
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``workshop_rgb.py`` for full example).
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.. image:: _static/ice40-rgb.jpg
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:width: 100%
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:alt: RGB block
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This is the RGB block from the datasheet. It has five inputs:
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``CURREN``, ``RGBLEDEN``, ``RGB0PWM``, ``RGB1PWM``, and ``RGB2PWM``. It
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has three outputs: ``RGB0``, ``RGB1``, and ``RGB2``. It also has four
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parameters: ``CURRENT_MODE``, ``RGB0_CURRENT``, ``RGB1_CURRENT``, and
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``RGB2_CURRENT``.
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This block is defined in Verilog, but we can very easily import it as a
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Module into Migen:
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.. code:: python
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class FomuRGB(Module, AutoCSR):
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def __init__(self, pads):
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self.output = CSRStorage(3)
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self.specials += Instance("SB_RGBA_DRV",
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i_CURREN = 0b1,
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i_RGBLEDEN = 0b1,
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i_RGB0PWM = self.output.storage[0],
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i_RGB1PWM = self.output.storage[1],
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i_RGB2PWM = self.output.storage[2],
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o_RGB0 = pads.r,
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o_RGB1 = pads.g,
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o_RGB2 = pads.b,
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p_CURRENT_MODE = "0b1",
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p_RGB0_CURRENT = "0b000011",
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p_RGB1_CURRENT = "0b000011",
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p_RGB2_CURRENT = "0b000011",
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)
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This will instantiate this Verilog block and connect it up. It also
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creates a ``CSRStorage`` object that is three bits wide, and assigns it
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to ``output``. By having this derive from ``AutoCSR``, the CSRStorage
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will have CSR bus accessor methods added to it automatically. Finally,
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it wires the pads up to the outputs of the block.
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We can instantiate this block by simply creating a new object and adding
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it to ``self.specials`` in our design:
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.. code:: python
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...
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# Add the LED driver block
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led_pads = soc.platform.request("rgb_led")
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soc.submodules.fomu_rgb = FomuRGB(led_pads)
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Finally, we need to add it to the ``csr_map``:
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.. code:: python
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...
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soc.add_csr("fomu_rgb")
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Now, when we rebuild this design and check ``build/csr.csv`` we can see
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our new register:
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.. code:: csv
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csr_register,rgb_output,0xe0006800,1,rw
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We can use ``wishbone-tool`` to write values to ``0xe0006800`` and see
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them take effect immediately.
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You can see that it takes very little code to take a Signal from HDL and
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expose it on the Wishbone bus.
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