fomu-workshop/chisel/blink/.gitignore
2020-11-19 21:40:59 -08:00

18 lines
391 B
Plaintext

# Verilog/SystemVerilog generated from src/Blink.scala
/Blink.sv
/Blink.v
# Annotations for the firrtl compiler, also generated from src/Blink.scala
/Blink.anno.json
# Intermediate representation of the circuit generated from src/Blink.scala
/Blink.fir
# IntelliJ IDE folder
/.idea/
# Scala build artifacts
target/
# same as for the verilog example
blink.json
blink.asc
blink.bit
blink.dfu