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64 lines
1.5 KiB
Makefile
64 lines
1.5 KiB
Makefile
include ../../board.mk
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# VHDL top with instantiated Verilog
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VHDL_SYN_FILES = ../../vhdl/sb_ice40_components.vhd blink.vhd
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VERILOG_SYN_FILES = clkgen.v
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# Verilog top with instantiated VHDL
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#VHDL_SYN_FILES = ../../vhdl/sb_ice40_components.vhd clkgen.vhd
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#VERILOG_SYN_FILES = blink.v
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GHDL_FLAGS += --std=08
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GHDL ?= ghdl
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GHDLSYNTH ?= ghdl
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YOSYS ?= yosys
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NEXTPNR ?= nextpnr-ice40
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ICEPACK ?= icepack
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# Default target: run all required targets to build the DFU image.
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all: blink.dfu
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@true
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.DEFAULT: all
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# Use *Yosys* to generate the synthesized netlist.
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# This is called the **synthesis** and **tech mapping** step.
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blink.json: $(VHDL_SYN_FILES) $(VERILOG_SYN_FILES)
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$(YOSYS) $(YOSYSFLAGS) \
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-p \
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"$(GHDLSYNTH) $(GHDL_FLAGS) $(VHDL_SYN_FILES) -e; \
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synth_ice40 \
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-top Fomu_Blink \
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-json $@" $(VERILOG_SYN_FILES) 2>&1 | tee yosys-report.txt
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# Use **nextpnr** to generate the FPGA configuration.
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# This is called the **place** and **route** step.
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blink.asc: blink.json $(PCF)
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$(NEXTPNR) \
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$(PNRFLAGS) \
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--pcf $(PCF) \
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--json $< \
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--asc $@
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# Use icepack to convert the FPGA configuration into a "bitstream" loadable onto the FPGA.
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# This is called the bitstream generation step.
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blink.bit: blink.asc
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$(ICEPACK) $< $@
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# Use dfu-suffix to generate the DFU image from the FPGA bitstream.
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blink.dfu: blink.bit
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cp $< $@
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dfu-suffix -v 1209 -p 70b1 -a $@
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# Use df-util to load the DFU image onto the Fomu.
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load: blink.dfu
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dfu-util -D $<
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.PHONY: load
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# Cleanup the generated files.
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clean:
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rm -fr *.cf *.json *-report.txt *.asc *.bit *.dfu
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.PHONY: clean
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