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22 lines
466 B
Verilog
22 lines
466 B
Verilog
module clkgen (
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input wire clk,
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output wire [2:0] cnt
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);
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// Connect to system clock (with buffering)
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wire clko;
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SB_GB clk_gb (
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.USER_SIGNAL_TO_GLOBAL_BUFFER(clk),
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.GLOBAL_BUFFER_OUTPUT(clko)
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);
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// Use counter logic to divide system clock. The clock is 48 MHz,
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// so we divide it down by 2^28.
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reg [28:0] counter = 0;
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always @(posedge clko) begin
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counter <= counter + 1;
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end
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assign cnt = counter[25:23];
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endmodule
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