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39 lines
761 B
VHDL
39 lines
761 B
VHDL
library ieee;
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context ieee.ieee_std_context;
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use work.components.all;
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entity clkgen is
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port (
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clk : in std_logic;
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cnt : out std_logic_vector(2 downto 0)
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);
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end;
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architecture arch of clkgen is
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signal clko: std_logic;
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signal counter: unsigned(27 downto 0) := (others=>'0');
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begin
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-- Connect to system clock (with buffering)
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clk_gb: SB_GB
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port map (
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USER_SIGNAL_TO_GLOBAL_BUFFER => clk,
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GLOBAL_BUFFER_OUTPUT => clko
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);
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-- Use counter logic to divide system clock. The clock is 48 MHz,
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-- so we divide it down by 2^28.
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process(clko)
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begin
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if rising_edge(clko) then
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counter <= counter + 1;
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end if;
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end process;
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cnt <= std_logic_vector(counter(counter'left downto counter'left-cnt'length+1));
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end;
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