Roy Ragsdale a6e03bc608 doc: Add comment on /dev/ttyACM permissions and dialout group ... Addresses #75. Modeled on the udev section on adding a user to the `plugdev` group. https://workshop.fomu.im/en/latest/requirements/drivers.html#steps-to-set-up-udev-rule		2021-11-09 21:54:02 -05:00
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_static	docs: add favicon	2021-05-20 13:38:32 +02:00
requirements	docs/requirements/software: add subsection about Containers	2021-05-31 19:46:33 +02:00
translations	Make changes analogous to those in verilog.rst.	2020-08-07 16:43:59 -07:00
background.rst	docs/background: fix typos	2021-07-29 17:11:35 +09:00
bootloader.rst	Add session types until autodetect improves.	2019-12-28 00:07:07 +01:00
conf.py	docs: remove unused dependency 'symbolator' (#551)	2021-09-24 02:12:26 +02:00
environment.yml	docs: fix conda env (pypa/pip#10237)	2021-08-07 16:12:29 +02:00
hdl.rst	docs: update references to hdl sources (#508)	2021-07-29 19:03:29 +02:00
help.rst	Adding a help page.	2019-12-28 13:25:27 +01:00
icestudio.rst	doc/icestudio: update section 'Board rules'	2020-11-26 15:48:42 +01:00
index.rst	docs: update index	2020-11-08 00:32:47 +01:00
make.bat	Adding sphinx version.	2019-12-25 21:20:27 +01:00
Makefile	Remove doctrees from gettext Makefile target	2020-07-18 06:30:16 +02:00
migen.rst	docs/migen: fix binary path	2021-07-29 17:31:04 +09:00
mixed-hdl.rst	docs/mixed-hdl: fix formatting	2021-07-29 17:42:58 +09:00
python.rst	doc: Add comment on /dev/ttyACM permissions and dialout group	2021-11-09 21:54:02 -05:00
renode-bridge.rst	docs: Use 'session' instead of 'code' for better copy'n'paste	2020-03-07 11:47:03 +13:00
renode-starting.rst	Splitting into multiple files.	2019-12-26 00:10:01 +01:00
renode-verilator.rst	Splitting into multiple files.	2019-12-26 00:10:01 +01:00
renode-zephyr.rst	Update path to Zephyr	2020-03-13 13:43:42 +01:00
renode.rst	Change to tip from note.	2019-12-27 19:23:06 +01:00
requirements.txt	docs: remove unused dependency 'symbolator' (#551)	2021-09-24 02:12:26 +02:00
riscv.rst	docs/risc-v: fix tinyusb firmware path (#511)	2021-08-24 04:20:02 +02:00
verilog.rst	docs: style	2021-05-31 19:46:33 +02:00
vhdl.rst	docs: style	2021-05-31 19:46:33 +02:00