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For https://github.com/im-tomu/fomu-workshop/issues/144#issuecomment-595993657 mark the session types of examples so that the automagic copynpaste handling knows how to figure out which parts to copy, rather than defaulting to copying everything.
98 lines
3.6 KiB
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98 lines
3.6 KiB
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Verilog on Fomu
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---------------
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“Hello world!” - Blink a LED
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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The canonical “Hello, world!” of hardware is to blink a LED. The
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directory ``verilog/blink-expanded`` contains a Verilog example of a blink
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project. This takes the 48 MHz clock and divides it down by a large
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number so you get an on/off pattern. It also exposes some of the signals
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on the touchpads, making it possible to probe them with an oscilloscope.
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Enter the ``verilog/blink-expanded`` directory and build the demo by using ``make``:
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**Make sure you set the ``FOMU_REV`` value to match your hardware! See
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the Required Hardware section.**
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.. session:: shell-session
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$ make FOMU_REV=$FOMU_REV
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...
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Info: Max frequency for clock 'clk': 73.26 MHz (PASS at 12.00 MHz)
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Info: Max delay posedge clk -> <async>: 3.15 ns
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Info: Slack histogram:
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Info: legend: * represents 1 endpoint(s)
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Info: + represents [1,1) endpoint(s)
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Info: [ 69683, 70208) |**
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Info: [ 70208, 70733) |
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Info: [ 70733, 71258) |**
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Info: [ 71258, 71783) |**
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Info: [ 71783, 72308) |**
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Info: [ 72308, 72833) |**
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Info: [ 72833, 73358) |
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Info: [ 73358, 73883) |**
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Info: [ 73883, 74408) |*
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Info: [ 74408, 74933) |**
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Info: [ 74933, 75458) |**
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Info: [ 75458, 75983) |*
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Info: [ 75983, 76508) |*
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Info: [ 76508, 77033) |**
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Info: [ 77033, 77558) |**
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Info: [ 77558, 78083) |*
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Info: [ 78083, 78608) |
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Info: [ 78608, 79133) |*************************
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Info: [ 79133, 79658) |**
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Info: [ 79658, 80183) |***
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22 warnings, 0 errors
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icepack blink.asc blink.bit
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cp blink.bit blink.dfu
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dfu-suffix -v 1209 -p 70b1 -a blink.dfu
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dfu-suffix (dfu-util) 0.9
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Copyright 2011-2012 Stefan Schmidt, 2013-2014 Tormod Volden
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This program is Free Software and has ABSOLUTELY NO WARRANTY
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Please report bugs to http://sourceforge.net/p/dfu-util/tickets/
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Suffix successfully added to file
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$
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You can then load ``blink.dfu`` onto Fomu by using the same ``dfu-util -D``
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command we’ve been using so far. You should see a blinking pattern of
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varying color on your Fomu, indicating your bitstream was successfully loaded.
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When writing HDL, a tool called ``yosys`` is used to convert the
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human readable verilog into a netlist representation, this is called
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synthesis. Once we have the netlist representation a tool called
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``nextpnr`` performs an operation called “place and route” which
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makes it something that will actually run on the FPGA. This is all
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done for you using the ``Makefile`` in the ``verilog/blink``
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directory.
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A big feature of ``nextpnr`` over its predecessor, is the fact that
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it is timing-driven. This means that a design will be generated with
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a given clock domain guaranteed to perform fast enough.
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When the ``make`` command runs ``nextpnr-ice40`` you will see something
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similar included in the output:
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::
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Info: Max frequency for clock 'clk': 73.26 MHz (PASS at 12.00 MHz)
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This output example shows that we could run ``clk`` at up to 73.26
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MHz and it would still be stable, even though we only requested 12.00
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MHz. Note that there is some variation between designs depending on
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how the placer and router decided to lay things out, so your exact
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frequency numbers might be different.
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Reading Input
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^^^^^^^^^^^^^
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There is another small example in ``verilog/blink-expanded`` which shows
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how to read out some given pins. Build and flash it like described above
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and see if you can enable the blue and red LED by shorting pins 1+2 or 3+4
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on your Fomu (the pins are the exposed contacts sticking out of the USB port).
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