mirror of
https://github.com/im-tomu/fomu-workshop.git
synced 2024-09-20 03:10:12 +00:00
114 lines
4.4 KiB
Python
114 lines
4.4 KiB
Python
#!/usr/bin/env python3
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# This variable defines all the external programs that this module
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# relies on. lxbuildenv reads this variable in order to ensure
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# the build will finish without exiting due to missing third-party
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# programs.
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LX_DEPENDENCIES = ["icestorm", "yosys", "nextpnr-ice40"]
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LX_CONFIG = "skip-git"
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# Import lxbuildenv to integrate the deps/ directory
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import os,sys
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sys.path.insert(0, os.path.dirname(__file__))
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import lxbuildenv
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# Disable pylint's E1101, which breaks completely on migen
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#pylint:disable=E1101
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from litex_boards.partner.platforms.fomu_hacker import Platform
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from litex_boards.partner.targets.fomu import _CRG
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from litex.soc.integration import SoCCore
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from litex.soc.integration.builder import Builder
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from lxsocsupport import up5kspram
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from valentyusb.usbcore import io as usbio
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from valentyusb.usbcore.cpu import dummyusb
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from migen import *
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from litex.soc.interconnect.csr import AutoCSR, CSRStatus, CSRStorage
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import argparse
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class BaseSoC(SoCCore):
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SoCCore.csr_map = {
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"ctrl": 0, # provided by default (optional)
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"crg": 1, # user
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"uart_phy": 2, # provided by default (optional)
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"uart": 3, # provided by default (optional)
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"identifier_mem": 4, # provided by default (optional)
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"timer0": 5, # provided by default (optional)
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"cpu_or_bridge": 8,
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"usb": 9,
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"picorvspi": 10,
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"touch": 11,
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"reboot": 12,
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"rgb": 13,
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"version": 14,
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}
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def __init__(self, platform, output_dir="build", placer=None, pnr_seed=0, use_pll=True, **kwargs):
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clk_freq = int(12e6)
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self.submodules.crg = _CRG(platform, use_pll=use_pll)
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SoCCore.__init__(self, platform, clk_freq,
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cpu_type=None,
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cpu_variant=None,
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integrated_sram_size=0,
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with_uart=False,
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with_ctrl=False,
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**kwargs)
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# UP5K has single port RAM, which is a dedicated 128 kilobyte block.
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# Use this as CPU RAM.
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spram_size = 128*1024
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self.submodules.spram = up5kspram.Up5kSPRAM(size=spram_size)
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self.register_mem("sram", 0x10000000, self.spram.bus, spram_size)
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# Add USB pads. We use DummyUsb, which simply enumerates as a USB
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# device. Then all interaction is done via the wishbone bridge.
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usb_pads = platform.request("usb")
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usb_iobuf = usbio.IoBuf(usb_pads.d_p, usb_pads.d_n, usb_pads.pullup)
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self.submodules.usb = dummyusb.DummyUsb(usb_iobuf, debug=True)
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self.add_wb_master(self.usb.debug_bridge.wishbone)
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# Add "-relut -dffe_min_ce_use 4" to the synth_ice40 command.
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# "-reult" adds an additional LUT pass to pack more stuff in, and
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# "-dffe_min_ce_use 4" flag prevents Yosys from generating a
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# Clock Enable signal for a LUT that has fewer than 4 flip-flops.
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# This increases density, and lets us use the FPGA more efficiently.
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platform.toolchain.nextpnr_yosys_template[2] += " -relut -dffe_min_ce_use 4"
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# Allow us to set the nextpnr seed, because some values don't meet timing.
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platform.toolchain.nextpnr_build_template[1] += " --seed " + str(pnr_seed)
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# Different placers can improve packing efficiency, however not all placers
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# are enabled on all builds of nextpnr-ice40. Let the user override which
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# placer they want to use.
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if placer is not None:
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platform.toolchain.nextpnr_build_template[1] += " --placer {}".format(placer)
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def main():
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parser = argparse.ArgumentParser(
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description="Build Fomu Main Gateware")
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parser.add_argument(
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"--seed", default=0, help="seed to use in nextpnr"
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)
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parser.add_argument(
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"--placer", default="heap", choices=["sa", "heap"], help="which placer to use in nextpnr"
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)
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parser.add_argument(
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"--no-pll", help="disable pll -- this is easier to route, but may not work", action="store_true"
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)
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args = parser.parse_args()
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platform = Platform()
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soc = BaseSoC(platform, pnr_seed=args.seed, placer=args.placer, use_pll=not args.no_pll)
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builder = Builder(soc,
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output_dir="build", csr_csv="test/csr.csv",
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compile_software=False)
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vns = builder.build()
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soc.do_exit(vns)
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if __name__ == "__main__":
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main()
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