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< a href = "nvic_8h.html" > Go to the documentation of this file.< / a > < div class = "fragment" > < pre class = "fragment" > < a name = "l00001" > < / a > 00001 < span class = "comment" > /*< / span >
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< a name = "l00002" > < / a > 00002 < span class = "comment" > ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.< / span >
< a name = "l00003" > < / a > 00003 < span class = "comment" > < / span >
< a name = "l00004" > < / a > 00004 < span class = "comment" > This file is part of ChibiOS/RT.< / span >
< a name = "l00005" > < / a > 00005 < span class = "comment" > < / span >
< a name = "l00006" > < / a > 00006 < span class = "comment" > ChibiOS/RT is free software; you can redistribute it and/or modify< / span >
< a name = "l00007" > < / a > 00007 < span class = "comment" > it under the terms of the GNU General Public License as published by< / span >
< a name = "l00008" > < / a > 00008 < span class = "comment" > the Free Software Foundation; either version 3 of the License, or< / span >
< a name = "l00009" > < / a > 00009 < span class = "comment" > (at your option) any later version.< / span >
< a name = "l00010" > < / a > 00010 < span class = "comment" > < / span >
< a name = "l00011" > < / a > 00011 < span class = "comment" > ChibiOS/RT is distributed in the hope that it will be useful,< / span >
< a name = "l00012" > < / a > 00012 < span class = "comment" > but WITHOUT ANY WARRANTY; without even the implied warranty of< / span >
< a name = "l00013" > < / a > 00013 < span class = "comment" > MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the< / span >
< a name = "l00014" > < / a > 00014 < span class = "comment" > GNU General Public License for more details.< / span >
< a name = "l00015" > < / a > 00015 < span class = "comment" > < / span >
< a name = "l00016" > < / a > 00016 < span class = "comment" > You should have received a copy of the GNU General Public License< / span >
< a name = "l00017" > < / a > 00017 < span class = "comment" > along with this program. If not, see < http://www.gnu.org/licenses/> .< / span >
< a name = "l00018" > < / a > 00018 < span class = "comment" > < / span >
< a name = "l00019" > < / a > 00019 < span class = "comment" > ---< / span >
< a name = "l00020" > < / a > 00020 < span class = "comment" > < / span >
< a name = "l00021" > < / a > 00021 < span class = "comment" > A special exception to the GPL can be applied should you wish to distribute< / span >
< a name = "l00022" > < / a > 00022 < span class = "comment" > a combined work that includes ChibiOS/RT, without being obliged to provide< / span >
< a name = "l00023" > < / a > 00023 < span class = "comment" > the source code for any proprietary components. See the file exception.txt< / span >
< a name = "l00024" > < / a > 00024 < span class = "comment" > for full details of how and when the exception can be applied.< / span >
< a name = "l00025" > < / a > 00025 < span class = "comment" > */< / span >
< a name = "l00026" > < / a > 00026 < span class = "comment" > < / span >
< a name = "l00027" > < / a > 00027 < span class = "comment" > /**< / span >
< a name = "l00028" > < / a > 00028 < span class = "comment" > * @file ARMCMx/nvic.h< / span >
< a name = "l00029" > < / a > 00029 < span class = "comment" > * @brief Cortex-Mx NVIC support macros and structures.< / span >
< a name = "l00030" > < / a > 00030 < span class = "comment" > *< / span >
< a name = "l00031" > < / a > 00031 < span class = "comment" > * @addtogroup ARMCMx_NVIC< / span >
< a name = "l00032" > < / a > 00032 < span class = "comment" > * @{< / span >
< a name = "l00033" > < / a > 00033 < span class = "comment" > */< / span >
< a name = "l00034" > < / a > 00034
< a name = "l00035" > < / a > 00035 < span class = "preprocessor" > #ifndef _NVIC_H_< / span >
< a name = "l00036" > < / a > 00036 < span class = "preprocessor" > < / span > < span class = "preprocessor" > #define _NVIC_H_< / span >
< a name = "l00037" > < / a > 00037 < span class = "preprocessor" > < / span >
< a name = "l00038" > < / a > 00038 < span class = "comment" > /*< / span >
< a name = "l00039" > < / a > 00039 < span class = "comment" > * System vector constants for @p NVICSetSystemHandlerPriority().< / span >
< a name = "l00040" > < / a > 00040 < span class = "comment" > */< / span >
< a name = "l00041" > < / a > < a class = "code" href = "group___a_r_m_c_mx___n_v_i_c.html#gab6ec63854f5a572650a0da800e12974f" > 00041< / a > < span class = "preprocessor" > #define HANDLER_MEM_MANAGE 0 < / span > < span class = "comment" > /**< MEM MANAGE vector id. */< / span >
< a name = "l00042" > < / a > < a class = "code" href = "group___a_r_m_c_mx___n_v_i_c.html#gaea14651f492c92bd57e4625364d69ff2" > 00042< / a > < span class = "preprocessor" > #define HANDLER_BUS_FAULT 1 < / span > < span class = "comment" > /**< BUS FAULT vector id. */< / span >
< a name = "l00043" > < / a > < a class = "code" href = "group___a_r_m_c_mx___n_v_i_c.html#ga5fd129625060d09dd552182cccb99a1d" > 00043< / a > < span class = "preprocessor" > #define HANDLER_USAGE_FAULT 2 < / span > < span class = "comment" > /**< USAGE FAULT vector id. */< / span >
< a name = "l00044" > < / a > 00044 < span class = "preprocessor" > #define HANDLER_RESERVED_3 3< / span >
< a name = "l00045" > < / a > 00045 < span class = "preprocessor" > < / span > < span class = "preprocessor" > #define HANDLER_RESERVED_4 4< / span >
< a name = "l00046" > < / a > 00046 < span class = "preprocessor" > < / span > < span class = "preprocessor" > #define HANDLER_RESERVED_5 5< / span >
< a name = "l00047" > < / a > 00047 < span class = "preprocessor" > < / span > < span class = "preprocessor" > #define HANDLER_RESERVED_6 6< / span >
< a name = "l00048" > < / a > < a class = "code" href = "group___a_r_m_c_mx___n_v_i_c.html#gaf1a1755ab445b421e7213fcab63bced5" > 00048< / a > < span class = "preprocessor" > < / span > < span class = "preprocessor" > #define HANDLER_SVCALL 7 < / span > < span class = "comment" > /**< SVCALL vector id. */< / span >
< a name = "l00049" > < / a > < a class = "code" href = "group___a_r_m_c_mx___n_v_i_c.html#ga916caa231c853049768c4b3e214f796b" > 00049< / a > < span class = "preprocessor" > #define HANDLER_DEBUG_MONITOR 8 < / span > < span class = "comment" > /**< DEBUG MONITOR vector id. */< / span >
< a name = "l00050" > < / a > 00050 < span class = "preprocessor" > #define HANDLER_RESERVED_9 9< / span >
< a name = "l00051" > < / a > < a class = "code" href = "group___a_r_m_c_mx___n_v_i_c.html#ga4a9ffb0f74fc91f6dac8a54422e24c64" > 00051< / a > < span class = "preprocessor" > < / span > < span class = "preprocessor" > #define HANDLER_PENDSV 10 < / span > < span class = "comment" > /**< PENDSV vector id. */< / span >
< a name = "l00052" > < / a > < a class = "code" href = "group___a_r_m_c_mx___n_v_i_c.html#ga9af0796781886f000d84c841b61a77e2" > 00052< / a > < span class = "preprocessor" > #define HANDLER_SYSTICK 11 < / span > < span class = "comment" > /**< SYS TCK vector id. */< / span >
< a name = "l00053" > < / a > 00053
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< a name = "l00054" > < / a > < a class = "code" href = "group___a_r_m_c_mx___n_v_i_c.html#gaa8b1de9f01a8c9bf3363436874058cb2" > 00054< / a > < span class = "keyword" > typedef< / span > < span class = "keyword" > volatile< / span > < a class = "code" href = "group___s_t_m8___c_o_r_e.html#gaba7bc1797add20fe3efdf37ced1182c5" > uint8_t< / a > IOREG8; < span class = "comment" > /**< 8 bits I/O register type. */< / span >
< a name = "l00055" > < / a > < a class = "code" href = "group___a_r_m_c_mx___n_v_i_c.html#gaaf485fff865c489bedf668cb8a478a68" > 00055< / a > < span class = "keyword" > typedef< / span > < span class = "keyword" > volatile< / span > < a class = "code" href = "group___s_t_m8___c_o_r_e.html#ga06896e8c53f721507066c079052171f8" > uint32_t< / a > IOREG32; < span class = "comment" > /**< 32 bits I/O register type. */< / span >
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< a name = "l00056" > < / a > 00056 < span class = "comment" > < / span >
< a name = "l00057" > < / a > 00057 < span class = "comment" > /**< / span >
< a name = "l00058" > < / a > 00058 < span class = "comment" > * @brief NVIC ITCR register.< / span >
< a name = "l00059" > < / a > 00059 < span class = "comment" > */< / span >
< a name = "l00060" > < / a > < a class = "code" href = "group___a_r_m_c_mx___n_v_i_c.html#ga005f75c1323f8573abdf5894e8da7552" > 00060< / a > < span class = "preprocessor" > #define NVIC_ITCR (*((IOREG32 *)0xE000E004))< / span >
< a name = "l00061" > < / a > 00061 < span class = "preprocessor" > < / span > < span class = "comment" > < / span >
< a name = "l00062" > < / a > 00062 < span class = "comment" > /**< / span >
< a name = "l00063" > < / a > 00063 < span class = "comment" > * @brief NVIC STIR register.< / span >
< a name = "l00064" > < / a > 00064 < span class = "comment" > */< / span >
< a name = "l00065" > < / a > < a class = "code" href = "group___a_r_m_c_mx___n_v_i_c.html#gaaa80bc30d455351b9231f252632d481b" > 00065< / a > < span class = "preprocessor" > #define NVIC_STIR (*((IOREG32 *)0xE000EF00))< / span >
< a name = "l00066" > < / a > 00066 < span class = "preprocessor" > < / span > < span class = "comment" > < / span >
< a name = "l00067" > < / a > 00067 < span class = "comment" > /**< / span >
< a name = "l00068" > < / a > 00068 < span class = "comment" > * @brief Structure representing the SYSTICK I/O space.< / span >
< a name = "l00069" > < / a > 00069 < span class = "comment" > */< / span >
< a name = "l00070" > < / a > < a class = "code" href = "struct_c_m3___s_t.html" > 00070< / a > < span class = "keyword" > typedef< / span > < span class = "keyword" > struct < / span > {
< a name = "l00071" > < / a > 00071 < a class = "code" href = "group___a_r_m_c_mx___n_v_i_c.html#gaaf485fff865c489bedf668cb8a478a68" > IOREG32< / a > CSR;
< a name = "l00072" > < / a > 00072 < a class = "code" href = "group___a_r_m_c_mx___n_v_i_c.html#gaaf485fff865c489bedf668cb8a478a68" > IOREG32< / a > RVR;
< a name = "l00073" > < / a > 00073 < a class = "code" href = "group___a_r_m_c_mx___n_v_i_c.html#gaaf485fff865c489bedf668cb8a478a68" > IOREG32< / a > CVR;
< a name = "l00074" > < / a > 00074 < a class = "code" href = "group___a_r_m_c_mx___n_v_i_c.html#gaaf485fff865c489bedf668cb8a478a68" > IOREG32< / a > CBVR;
< a name = "l00075" > < / a > 00075 } < a class = "code" href = "struct_c_m3___s_t.html" title = "Structure representing the SYSTICK I/O space." > CM3_ST< / a > ;
< a name = "l00076" > < / a > 00076 < span class = "comment" > < / span >
< a name = "l00077" > < / a > 00077 < span class = "comment" > /**< / span >
< a name = "l00078" > < / a > 00078 < span class = "comment" > * @brief SYSTICK peripheral base address.< / span >
< a name = "l00079" > < / a > 00079 < span class = "comment" > */< / span >
< a name = "l00080" > < / a > < a class = "code" href = "group___a_r_m_c_mx___n_v_i_c.html#ga53599e3baa092c73f97a33c3f0889fe5" > 00080< / a > < span class = "preprocessor" > #define STBase ((CM3_ST *)0xE000E010)< / span >
< a name = "l00081" > < / a > 00081 < span class = "preprocessor" > < / span > < span class = "preprocessor" > #define ST_CSR (STBase-> CSR)< / span >
< a name = "l00082" > < / a > 00082 < span class = "preprocessor" > < / span > < span class = "preprocessor" > #define ST_RVR (STBase-> RVR)< / span >
< a name = "l00083" > < / a > 00083 < span class = "preprocessor" > < / span > < span class = "preprocessor" > #define ST_CVR (STBase-> CVR)< / span >
< a name = "l00084" > < / a > 00084 < span class = "preprocessor" > < / span > < span class = "preprocessor" > #define ST_CBVR (STBase-> CBVR)< / span >
< a name = "l00085" > < / a > 00085 < span class = "preprocessor" > < / span >
< a name = "l00086" > < / a > 00086 < span class = "preprocessor" > #define CSR_ENABLE_MASK (0x1 < < 0)< / span >
< a name = "l00087" > < / a > 00087 < span class = "preprocessor" > < / span > < span class = "preprocessor" > #define ENABLE_OFF_BITS (0 < < 0)< / span >
< a name = "l00088" > < / a > 00088 < span class = "preprocessor" > < / span > < span class = "preprocessor" > #define ENABLE_ON_BITS (1 < < 0)< / span >
< a name = "l00089" > < / a > 00089 < span class = "preprocessor" > < / span > < span class = "preprocessor" > #define CSR_TICKINT_MASK (0x1 < < 1)< / span >
< a name = "l00090" > < / a > 00090 < span class = "preprocessor" > < / span > < span class = "preprocessor" > #define TICKINT_DISABLED_BITS (0 < < 1)< / span >
< a name = "l00091" > < / a > 00091 < span class = "preprocessor" > < / span > < span class = "preprocessor" > #define TICKINT_ENABLED_BITS (1 < < 1)< / span >
< a name = "l00092" > < / a > 00092 < span class = "preprocessor" > < / span > < span class = "preprocessor" > #define CSR_CLKSOURCE_MASK (0x1 < < 2)< / span >
< a name = "l00093" > < / a > 00093 < span class = "preprocessor" > < / span > < span class = "preprocessor" > #define CLKSOURCE_EXT_BITS (0 < < 2)< / span >
< a name = "l00094" > < / a > 00094 < span class = "preprocessor" > < / span > < span class = "preprocessor" > #define CLKSOURCE_CORE_BITS (1 < < 2)< / span >
< a name = "l00095" > < / a > 00095 < span class = "preprocessor" > < / span > < span class = "preprocessor" > #define CSR_COUNTFLAG_MASK (0x1 < < 16)< / span >
< a name = "l00096" > < / a > 00096 < span class = "preprocessor" > < / span >
< a name = "l00097" > < / a > 00097 < span class = "preprocessor" > #define RVR_RELOAD_MASK (0xFFFFFF < < 0)< / span >
< a name = "l00098" > < / a > 00098 < span class = "preprocessor" > < / span >
< a name = "l00099" > < / a > 00099 < span class = "preprocessor" > #define CVR_CURRENT_MASK (0xFFFFFF < < 0)< / span >
< a name = "l00100" > < / a > 00100 < span class = "preprocessor" > < / span >
< a name = "l00101" > < / a > 00101 < span class = "preprocessor" > #define CBVR_TENMS_MASK (0xFFFFFF < < 0)< / span >
< a name = "l00102" > < / a > 00102 < span class = "preprocessor" > < / span > < span class = "preprocessor" > #define CBVR_SKEW_MASK (0x1 < < 30)< / span >
< a name = "l00103" > < / a > 00103 < span class = "preprocessor" > < / span > < span class = "preprocessor" > #define CBVR_NOREF_MASK (0x1 < < 31)< / span >
< a name = "l00104" > < / a > 00104 < span class = "preprocessor" > < / span > < span class = "comment" > < / span >
< a name = "l00105" > < / a > 00105 < span class = "comment" > /**< / span >
< a name = "l00106" > < / a > 00106 < span class = "comment" > * @brief Structure representing the NVIC I/O space.< / span >
< a name = "l00107" > < / a > 00107 < span class = "comment" > */< / span >
< a name = "l00108" > < / a > < a class = "code" href = "struct_c_m3___n_v_i_c.html" > 00108< / a > < span class = "keyword" > typedef< / span > < span class = "keyword" > struct < / span > {
< a name = "l00109" > < / a > 00109 < a class = "code" href = "group___a_r_m_c_mx___n_v_i_c.html#gaaf485fff865c489bedf668cb8a478a68" > IOREG32< / a > ISER[8];
< a name = "l00110" > < / a > 00110 < a class = "code" href = "group___a_r_m_c_mx___n_v_i_c.html#gaaf485fff865c489bedf668cb8a478a68" > IOREG32< / a > unused1[24];
< a name = "l00111" > < / a > 00111 < a class = "code" href = "group___a_r_m_c_mx___n_v_i_c.html#gaaf485fff865c489bedf668cb8a478a68" > IOREG32< / a > ICER[8];
< a name = "l00112" > < / a > 00112 < a class = "code" href = "group___a_r_m_c_mx___n_v_i_c.html#gaaf485fff865c489bedf668cb8a478a68" > IOREG32< / a > unused2[24];
< a name = "l00113" > < / a > 00113 < a class = "code" href = "group___a_r_m_c_mx___n_v_i_c.html#gaaf485fff865c489bedf668cb8a478a68" > IOREG32< / a > ISPR[8];
< a name = "l00114" > < / a > 00114 < a class = "code" href = "group___a_r_m_c_mx___n_v_i_c.html#gaaf485fff865c489bedf668cb8a478a68" > IOREG32< / a > unused3[24];
< a name = "l00115" > < / a > 00115 < a class = "code" href = "group___a_r_m_c_mx___n_v_i_c.html#gaaf485fff865c489bedf668cb8a478a68" > IOREG32< / a > ICPR[8];
< a name = "l00116" > < / a > 00116 < a class = "code" href = "group___a_r_m_c_mx___n_v_i_c.html#gaaf485fff865c489bedf668cb8a478a68" > IOREG32< / a > unused4[24];
< a name = "l00117" > < / a > 00117 < a class = "code" href = "group___a_r_m_c_mx___n_v_i_c.html#gaaf485fff865c489bedf668cb8a478a68" > IOREG32< / a > IABR[8];
< a name = "l00118" > < / a > 00118 < a class = "code" href = "group___a_r_m_c_mx___n_v_i_c.html#gaaf485fff865c489bedf668cb8a478a68" > IOREG32< / a > unused5[56];
< a name = "l00119" > < / a > 00119 < a class = "code" href = "group___a_r_m_c_mx___n_v_i_c.html#gaaf485fff865c489bedf668cb8a478a68" > IOREG32< / a > IPR[60];
< a name = "l00120" > < / a > 00120 } < a class = "code" href = "struct_c_m3___n_v_i_c.html" title = "Structure representing the NVIC I/O space." > CM3_NVIC< / a > ;
< a name = "l00121" > < / a > 00121 < span class = "comment" > < / span >
< a name = "l00122" > < / a > 00122 < span class = "comment" > /**< / span >
< a name = "l00123" > < / a > 00123 < span class = "comment" > * @brief NVIC peripheral base address.< / span >
< a name = "l00124" > < / a > 00124 < span class = "comment" > */< / span >
< a name = "l00125" > < / a > < a class = "code" href = "group___a_r_m_c_mx___n_v_i_c.html#ga9be85cd1df2d663931254c92e2d822ad" > 00125< / a > < span class = "preprocessor" > #define NVICBase ((CM3_NVIC *)0xE000E100)< / span >
< a name = "l00126" > < / a > 00126 < span class = "preprocessor" > < / span > < span class = "preprocessor" > #define NVIC_ISER(n) (NVICBase-> ISER[n])< / span >
< a name = "l00127" > < / a > 00127 < span class = "preprocessor" > < / span > < span class = "preprocessor" > #define NVIC_ICER(n) (NVICBase-> ICER[n])< / span >
< a name = "l00128" > < / a > 00128 < span class = "preprocessor" > < / span > < span class = "preprocessor" > #define NVIC_ISPR(n) (NVICBase-> ISPR[n])< / span >
< a name = "l00129" > < / a > 00129 < span class = "preprocessor" > < / span > < span class = "preprocessor" > #define NVIC_ICPR(n) (NVICBase-> ICPR[n])< / span >
< a name = "l00130" > < / a > 00130 < span class = "preprocessor" > < / span > < span class = "preprocessor" > #define NVIC_IABR(n) (NVICBase-> IABR[n])< / span >
< a name = "l00131" > < / a > 00131 < span class = "preprocessor" > < / span > < span class = "preprocessor" > #define NVIC_IPR(n) (NVICBase-> IPR[n])< / span >
< a name = "l00132" > < / a > 00132 < span class = "preprocessor" > < / span > < span class = "comment" > < / span >
< a name = "l00133" > < / a > 00133 < span class = "comment" > /**< / span >
< a name = "l00134" > < / a > 00134 < span class = "comment" > * @brief Structure representing the System Control Block I/O space.< / span >
< a name = "l00135" > < / a > 00135 < span class = "comment" > */< / span >
< a name = "l00136" > < / a > < a class = "code" href = "struct_c_m3___s_c_b.html" > 00136< / a > < span class = "keyword" > typedef< / span > < span class = "keyword" > struct < / span > {
< a name = "l00137" > < / a > 00137 < a class = "code" href = "group___a_r_m_c_mx___n_v_i_c.html#gaaf485fff865c489bedf668cb8a478a68" > IOREG32< / a > CPUID;
< a name = "l00138" > < / a > 00138 < a class = "code" href = "group___a_r_m_c_mx___n_v_i_c.html#gaaf485fff865c489bedf668cb8a478a68" > IOREG32< / a > ICSR;
< a name = "l00139" > < / a > 00139 < a class = "code" href = "group___a_r_m_c_mx___n_v_i_c.html#gaaf485fff865c489bedf668cb8a478a68" > IOREG32< / a > VTOR;
< a name = "l00140" > < / a > 00140 < a class = "code" href = "group___a_r_m_c_mx___n_v_i_c.html#gaaf485fff865c489bedf668cb8a478a68" > IOREG32< / a > AIRCR;
< a name = "l00141" > < / a > 00141 < a class = "code" href = "group___a_r_m_c_mx___n_v_i_c.html#gaaf485fff865c489bedf668cb8a478a68" > IOREG32< / a > SCR;
< a name = "l00142" > < / a > 00142 < a class = "code" href = "group___a_r_m_c_mx___n_v_i_c.html#gaaf485fff865c489bedf668cb8a478a68" > IOREG32< / a > CCR;
< a name = "l00143" > < / a > 00143 < a class = "code" href = "group___a_r_m_c_mx___n_v_i_c.html#gaaf485fff865c489bedf668cb8a478a68" > IOREG32< / a > SHPR[3];
< a name = "l00144" > < / a > 00144 < a class = "code" href = "group___a_r_m_c_mx___n_v_i_c.html#gaaf485fff865c489bedf668cb8a478a68" > IOREG32< / a > SHCSR;
< a name = "l00145" > < / a > 00145 < a class = "code" href = "group___a_r_m_c_mx___n_v_i_c.html#gaaf485fff865c489bedf668cb8a478a68" > IOREG32< / a > CFSR;
< a name = "l00146" > < / a > 00146 < a class = "code" href = "group___a_r_m_c_mx___n_v_i_c.html#gaaf485fff865c489bedf668cb8a478a68" > IOREG32< / a > HFSR;
< a name = "l00147" > < / a > 00147 < a class = "code" href = "group___a_r_m_c_mx___n_v_i_c.html#gaaf485fff865c489bedf668cb8a478a68" > IOREG32< / a > DFSR;
< a name = "l00148" > < / a > 00148 < a class = "code" href = "group___a_r_m_c_mx___n_v_i_c.html#gaaf485fff865c489bedf668cb8a478a68" > IOREG32< / a > MMFAR;
< a name = "l00149" > < / a > 00149 < a class = "code" href = "group___a_r_m_c_mx___n_v_i_c.html#gaaf485fff865c489bedf668cb8a478a68" > IOREG32< / a > BFAR;
< a name = "l00150" > < / a > 00150 < a class = "code" href = "group___a_r_m_c_mx___n_v_i_c.html#gaaf485fff865c489bedf668cb8a478a68" > IOREG32< / a > AFSR;
< a name = "l00151" > < / a > 00151 } < a class = "code" href = "struct_c_m3___s_c_b.html" title = "Structure representing the System Control Block I/O space." > CM3_SCB< / a > ;
< a name = "l00152" > < / a > 00152 < span class = "comment" > < / span >
< a name = "l00153" > < / a > 00153 < span class = "comment" > /**< / span >
< a name = "l00154" > < / a > 00154 < span class = "comment" > * @brief SCB peripheral base address.< / span >
< a name = "l00155" > < / a > 00155 < span class = "comment" > */< / span >
< a name = "l00156" > < / a > < a class = "code" href = "group___a_r_m_c_mx___n_v_i_c.html#gae0b689c91aa1605a75ff3c07b1846187" > 00156< / a > < span class = "preprocessor" > #define SCBBase ((CM3_SCB *)0xE000ED00)< / span >
< a name = "l00157" > < / a > 00157 < span class = "preprocessor" > < / span > < span class = "preprocessor" > #define SCB_CPUID (SCBBase-> CPUID)< / span >
< a name = "l00158" > < / a > 00158 < span class = "preprocessor" > < / span > < span class = "preprocessor" > #define SCB_ICSR (SCBBase-> ICSR)< / span >
< a name = "l00159" > < / a > 00159 < span class = "preprocessor" > < / span > < span class = "preprocessor" > #define SCB_VTOR (SCBBase-> VTOR)< / span >
< a name = "l00160" > < / a > 00160 < span class = "preprocessor" > < / span > < span class = "preprocessor" > #define SCB_AIRCR (SCBBase-> AIRCR)< / span >
< a name = "l00161" > < / a > 00161 < span class = "preprocessor" > < / span > < span class = "preprocessor" > #define SCB_SCR (SCBBase-> SCR)< / span >
< a name = "l00162" > < / a > 00162 < span class = "preprocessor" > < / span > < span class = "preprocessor" > #define SCB_CCR (SCBBase-> CCR)< / span >
< a name = "l00163" > < / a > 00163 < span class = "preprocessor" > < / span > < span class = "preprocessor" > #define SCB_SHPR(n) (SCBBase-> SHPR[n])< / span >
< a name = "l00164" > < / a > 00164 < span class = "preprocessor" > < / span > < span class = "preprocessor" > #define SCB_SHCSR (SCBBase-> SHCSR)< / span >
< a name = "l00165" > < / a > 00165 < span class = "preprocessor" > < / span > < span class = "preprocessor" > #define SCB_CFSR (SCBBase-> CFSR)< / span >
< a name = "l00166" > < / a > 00166 < span class = "preprocessor" > < / span > < span class = "preprocessor" > #define SCB_HFSR (SCBBase-> HFSR)< / span >
< a name = "l00167" > < / a > 00167 < span class = "preprocessor" > < / span > < span class = "preprocessor" > #define SCB_DFSR (SCBBase-> DFSR)< / span >
< a name = "l00168" > < / a > 00168 < span class = "preprocessor" > < / span > < span class = "preprocessor" > #define SCB_MMFAR (SCBBase-> MMFAR)< / span >
< a name = "l00169" > < / a > 00169 < span class = "preprocessor" > < / span > < span class = "preprocessor" > #define SCB_BFAR (SCBBase-> BFAR)< / span >
< a name = "l00170" > < / a > 00170 < span class = "preprocessor" > < / span > < span class = "preprocessor" > #define SCB_AFSR (SCBBase-> AFSR)< / span >
< a name = "l00171" > < / a > 00171 < span class = "preprocessor" > < / span >
< a name = "l00172" > < / a > 00172 < span class = "preprocessor" > #define ICSR_VECTACTIVE_MASK (0x1FF < < 0)< / span >
< a name = "l00173" > < / a > 00173 < span class = "preprocessor" > < / span > < span class = "preprocessor" > #define ICSR_RETTOBASE (0x1 < < 11)< / span >
< a name = "l00174" > < / a > 00174 < span class = "preprocessor" > < / span > < span class = "preprocessor" > #define ICSR_VECTPENDING_MASK (0x1FF < < 12)< / span >
< a name = "l00175" > < / a > 00175 < span class = "preprocessor" > < / span > < span class = "preprocessor" > #define ICSR_ISRPENDING (0x1 < < 22)< / span >
< a name = "l00176" > < / a > 00176 < span class = "preprocessor" > < / span > < span class = "preprocessor" > #define ICSR_ISRPREEMPT (0x1 < < 23)< / span >
< a name = "l00177" > < / a > 00177 < span class = "preprocessor" > < / span > < span class = "preprocessor" > #define ICSR_PENDSTCLR (0x1 < < 25)< / span >
< a name = "l00178" > < / a > 00178 < span class = "preprocessor" > < / span > < span class = "preprocessor" > #define ICSR_PENDSTSET (0x1 < < 26)< / span >
< a name = "l00179" > < / a > 00179 < span class = "preprocessor" > < / span > < span class = "preprocessor" > #define ICSR_PENDSVCLR (0x1 < < 27)< / span >
< a name = "l00180" > < / a > 00180 < span class = "preprocessor" > < / span > < span class = "preprocessor" > #define ICSR_PENDSVSET (0x1 < < 28)< / span >
< a name = "l00181" > < / a > 00181 < span class = "preprocessor" > < / span > < span class = "preprocessor" > #define ICSR_NMIPENDSET (0x1 < < 31)< / span >
< a name = "l00182" > < / a > 00182 < span class = "preprocessor" > < / span >
< a name = "l00183" > < / a > 00183 < span class = "preprocessor" > #define AIRCR_VECTKEY 0x05FA0000< / span >
< a name = "l00184" > < / a > 00184 < span class = "preprocessor" > < / span > < span class = "preprocessor" > #define AIRCR_PRIGROUP_MASK (0x7 < < 8)< / span >
< a name = "l00185" > < / a > 00185 < span class = "preprocessor" > < / span > < span class = "preprocessor" > #define AIRCR_PRIGROUP(n) ((n) < < 8)< / span >
< a name = "l00186" > < / a > 00186 < span class = "preprocessor" > < / span >
< a name = "l00187" > < / a > 00187 < span class = "preprocessor" > #ifdef __cplusplus< / span >
< a name = "l00188" > < / a > 00188 < span class = "preprocessor" > < / span > < span class = "keyword" > extern< / span > < span class = "stringliteral" > " C" < / span > {
< a name = "l00189" > < / a > 00189 < span class = "preprocessor" > #endif< / span >
< a name = "l00190" > < / a > 00190 < span class = "preprocessor" > < / span > < span class = "keywordtype" > void< / span > < a class = "code" href = "group___a_r_m_c_mx___n_v_i_c.html#ga607470c0f5d4bd0ee0f7208a9def4986" title = "Sets the priority of an interrupt handler and enables it." > NVICEnableVector< / a > (< a class = "code" href = "group___s_t_m8___c_o_r_e.html#ga06896e8c53f721507066c079052171f8" > uint32_t< / a > n, < a class = "code" href = "group___s_t_m8___c_o_r_e.html#ga06896e8c53f721507066c079052171f8" > uint32_t< / a > prio);
< a name = "l00191" > < / a > 00191 < span class = "keywordtype" > void< / span > < a class = "code" href = "group___a_r_m_c_mx___n_v_i_c.html#ga66f3c540c80ac9d9ea7878671b0bd59e" title = "Disables an interrupt handler." > NVICDisableVector< / a > (< a class = "code" href = "group___s_t_m8___c_o_r_e.html#ga06896e8c53f721507066c079052171f8" > uint32_t< / a > n);
< a name = "l00192" > < / a > 00192 < span class = "keywordtype" > void< / span > < a class = "code" href = "group___a_r_m_c_mx___n_v_i_c.html#ga0e210980bade4563602ebd04325f3cec" title = "Changes the priority of a system handler." > NVICSetSystemHandlerPriority< / a > (< a class = "code" href = "group___s_t_m8___c_o_r_e.html#ga06896e8c53f721507066c079052171f8" > uint32_t< / a > handler, < a class = "code" href = "group___s_t_m8___c_o_r_e.html#ga06896e8c53f721507066c079052171f8" > uint32_t< / a > prio);
< a name = "l00193" > < / a > 00193 < span class = "preprocessor" > #ifdef __cplusplus< / span >
< a name = "l00194" > < / a > 00194 < span class = "preprocessor" > < / span > }
< a name = "l00195" > < / a > 00195 < span class = "preprocessor" > #endif< / span >
< a name = "l00196" > < / a > 00196 < span class = "preprocessor" > < / span >
< a name = "l00197" > < / a > 00197 < span class = "preprocessor" > #endif < / span > < span class = "comment" > /* _NVIC_H_ */< / span >
< a name = "l00198" > < / a > 00198 < span class = "comment" > < / span >
< a name = "l00199" > < / a > 00199 < span class = "comment" > /** @} */< / span >
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Generated on Sun Oct 24 2010 09:40:37 for ChibiOS/RT by < a href = "http://www.doxygen.org/index.html" > < img src = "doxygen.png" alt = "doxygen" align = "middle" border = "0" > < / a > 1.7.1< / small > < / address >
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