<areashape="rect"id="node1"href="group__ports.html"title="Ports"alt=""coords="7,81,52,108"/><areashape="rect"id="node2"href="group___s_p_c563___d_r_i_v_e_r_s.html"title="Device drivers included in the SPC563 support."alt=""coords="237,5,336,32"/><areashape="rect"id="node3"href="group___p_p_c___c_o_n_f.html"title="PowerPC Configuration Options."alt=""coords="224,56,349,83"/><areashape="rect"id="node5"href="group___p_p_c___s_t_a_r_t_u_p.html"title="PPC startup code support."alt=""coords="237,107,336,133"/><areashape="rect"id="node6"href="group___p_p_c___c_o_r_e.html"title="PowerPC specific port code, structures and macros."alt=""coords="217,157,356,184"/></map>
<p>The ChibiOS/RT logical <aclass="el"href="concepts.html#system_states">System States</a> are mapped as follow in the PowerPC port:</p>
<ul>
<li><b>Init</b>. This state is represented by the startup code and the initialization code before <code><aclass="el"href="group__system.html#gafe2c7de6567e98e487e009e81e3be10b"title="ChibiOS/RT initialization.">chSysInit()</a></code> is executed. It has not a special hardware state associated.</li>
<li><b>Normal</b>. This is the state the system has after executing <code><aclass="el"href="group__system.html#gafe2c7de6567e98e487e009e81e3be10b"title="ChibiOS/RT initialization.">chSysInit()</a></code>. Interrupts are enabled.</li>
<li><b>Suspended</b>. Interrupts are disabled.</li>
<li><b>Disabled</b>. Interrupts are disabled. This state is equivalent to the Suspended state because there are no fast interrupts in this architecture.</li>
<li><b>Sleep</b>. This state is entered with the execution of the specific instruction <code><b>wait</b></code>.</li>
<li><b>S-Locked</b>. Interrupts are disabled.</li>
<li><b>I-Locked</b>. This state is equivalent to the SRI state, the <code>chSysLockI()</code> and <code>chSysUnlockI()</code> APIs do nothing (still use them in order to formally change state because this may change).</li>
<li><b>Serving Regular Interrupt</b>. Normal interrupt service code.</li>
<li><b>Serving Fast Interrupt</b>. Not present in this architecture.</li>
<li><b>Serving Non-Maskable Interrupt</b>. The PowerPC has several non maskable interrupt sources that can be associated to this state.</li>
<li><b>Halted</b>. Implemented as an infinite loop with interrupts disabled.</li>
<tr><tdclass="memItemLeft"align="right"valign="top"> </td><tdclass="memItemRight"valign="bottom"><aclass="el"href="group___p_p_c___c_o_r_e.html">Core Port Implementation</a></td></tr>
<p><tr><tdclass="mdescLeft"> </td><tdclass="mdescRight"><p>PowerPC specific port code, structures and macros. </p>
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