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571 lines
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<html><head><meta http-equiv="Content-Type" content="text/html;charset=UTF-8">
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<title>ChibiOS/RT: lpc214x.h Source File</title>
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<td style="width: 80px;"><img alt="ChibiOS/RT Logo" src="logo_small.png"></td>
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<td><big><big>ChibiOS/RT</big></big><br><br>Architecture - Reference Manual - Guides</td>
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<h1>lpc214x.h</h1><a href="lpc214x_8h.html">Go to the documentation of this file.</a><div class="fragment"><pre class="fragment"><a name="l00001"></a>00001 <span class="comment">/*</span>
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<a name="l00002"></a>00002 <span class="comment"> ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.</span>
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<a name="l00003"></a>00003 <span class="comment"></span>
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<a name="l00004"></a>00004 <span class="comment"> This file is part of ChibiOS/RT.</span>
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<a name="l00005"></a>00005 <span class="comment"></span>
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<a name="l00006"></a>00006 <span class="comment"> ChibiOS/RT is free software; you can redistribute it and/or modify</span>
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<a name="l00007"></a>00007 <span class="comment"> it under the terms of the GNU General Public License as published by</span>
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<a name="l00008"></a>00008 <span class="comment"> the Free Software Foundation; either version 3 of the License, or</span>
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<a name="l00009"></a>00009 <span class="comment"> (at your option) any later version.</span>
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<a name="l00010"></a>00010 <span class="comment"></span>
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<a name="l00011"></a>00011 <span class="comment"> ChibiOS/RT is distributed in the hope that it will be useful,</span>
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<a name="l00012"></a>00012 <span class="comment"> but WITHOUT ANY WARRANTY; without even the implied warranty of</span>
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<a name="l00013"></a>00013 <span class="comment"> MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span>
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<a name="l00014"></a>00014 <span class="comment"> GNU General Public License for more details.</span>
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<a name="l00015"></a>00015 <span class="comment"></span>
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<a name="l00016"></a>00016 <span class="comment"> You should have received a copy of the GNU General Public License</span>
|
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<a name="l00017"></a>00017 <span class="comment"> along with this program. If not, see <http://www.gnu.org/licenses/>.</span>
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<a name="l00018"></a>00018 <span class="comment"></span>
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<a name="l00019"></a>00019 <span class="comment"> ---</span>
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<a name="l00020"></a>00020 <span class="comment"></span>
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<a name="l00021"></a>00021 <span class="comment"> A special exception to the GPL can be applied should you wish to distribute</span>
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<a name="l00022"></a>00022 <span class="comment"> a combined work that includes ChibiOS/RT, without being obliged to provide</span>
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<a name="l00023"></a>00023 <span class="comment"> the source code for any proprietary components. See the file exception.txt</span>
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<a name="l00024"></a>00024 <span class="comment"> for full details of how and when the exception can be applied.</span>
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<a name="l00025"></a>00025 <span class="comment">*/</span>
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<a name="l00026"></a>00026 <span class="comment"></span>
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<a name="l00027"></a>00027 <span class="comment">/**</span>
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<a name="l00028"></a>00028 <span class="comment"> * @file lpc214x.h</span>
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<a name="l00029"></a>00029 <span class="comment"> * @brief LPC214x register definitions.</span>
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<a name="l00030"></a>00030 <span class="comment"> */</span>
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<a name="l00031"></a>00031
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<a name="l00032"></a>00032 <span class="preprocessor">#ifndef _LPC214X_H_</span>
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<a name="l00033"></a>00033 <span class="preprocessor"></span><span class="preprocessor">#define _LPC214X_H_</span>
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<a name="l00034"></a>00034 <span class="preprocessor"></span>
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<a name="l00035"></a>00035 <span class="keyword">typedef</span> <span class="keyword">volatile</span> <a class="code" href="group___s_t_m8___c_o_r_e.html#gaba7bc1797add20fe3efdf37ced1182c5">uint8_t</a> <a class="code" href="group___a_r_m_c_mx___n_v_i_c.html#gaa8b1de9f01a8c9bf3363436874058cb2">IOREG8</a>;
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<a name="l00036"></a>00036 <span class="keyword">typedef</span> <span class="keyword">volatile</span> <a class="code" href="group___s_t_m8___c_o_r_e.html#ga1f1825b69244eb3ad2c7165ddc99c956">uint16_t</a> IOREG16;
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<a name="l00037"></a>00037 <span class="keyword">typedef</span> <span class="keyword">volatile</span> <a class="code" href="group___s_t_m8___c_o_r_e.html#ga06896e8c53f721507066c079052171f8">uint32_t</a> <a class="code" href="group___a_r_m_c_mx___n_v_i_c.html#gaaf485fff865c489bedf668cb8a478a68">IOREG32</a>;
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<a name="l00038"></a>00038
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<a name="l00039"></a>00039 <span class="comment">/*</span>
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<a name="l00040"></a>00040 <span class="comment"> * System.</span>
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<a name="l00041"></a>00041 <span class="comment"> */</span>
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<a name="l00042"></a>00042 <span class="preprocessor">#define MEMMAP (*((IOREG32 *)0xE01FC040))</span>
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<a name="l00043"></a>00043 <span class="preprocessor"></span><span class="preprocessor">#define PCON (*((IOREG32 *)0xE01FC0C0))</span>
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<a name="l00044"></a>00044 <span class="preprocessor"></span><span class="preprocessor">#define PCONP (*((IOREG32 *)0xE01FC0C4))</span>
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<a name="l00045"></a>00045 <span class="preprocessor"></span><span class="preprocessor">#define VPBDIV (*((IOREG32 *)0xE01FC100))</span>
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<a name="l00046"></a>00046 <span class="preprocessor"></span><span class="preprocessor">#define EXTINT (*((IOREG32 *)0xE01FC140))</span>
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<a name="l00047"></a>00047 <span class="preprocessor"></span><span class="preprocessor">#define INTWAKE (*((IOREG32 *)0xE01FC144))</span>
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<a name="l00048"></a>00048 <span class="preprocessor"></span><span class="preprocessor">#define EXTMODE (*((IOREG32 *)0xE01FC148))</span>
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<a name="l00049"></a>00049 <span class="preprocessor"></span><span class="preprocessor">#define EXTPOLAR (*((IOREG32 *)0xE01FC14C))</span>
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<a name="l00050"></a>00050 <span class="preprocessor"></span><span class="preprocessor">#define RSID (*((IOREG32 *)0xE01FC180))</span>
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<a name="l00051"></a>00051 <span class="preprocessor"></span><span class="preprocessor">#define CSPR (*((IOREG32 *)0xE01FC184))</span>
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<a name="l00052"></a>00052 <span class="preprocessor"></span><span class="preprocessor">#define SCS (*((IOREG32 *)0xE01FC1A0))</span>
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<a name="l00053"></a>00053 <span class="preprocessor"></span>
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<a name="l00054"></a>00054 <span class="preprocessor">#define VPD_D4 0</span>
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<a name="l00055"></a>00055 <span class="preprocessor"></span><span class="preprocessor">#define VPD_D1 1</span>
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<a name="l00056"></a>00056 <span class="preprocessor"></span><span class="preprocessor">#define VPD_D2 2</span>
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<a name="l00057"></a>00057 <span class="preprocessor"></span><span class="preprocessor">#define VPD_RESERVED 3</span>
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<a name="l00058"></a>00058 <span class="preprocessor"></span>
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<a name="l00059"></a>00059 <span class="preprocessor">#define PCTIM0 (1 << 1)</span>
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<a name="l00060"></a>00060 <span class="preprocessor"></span><span class="preprocessor">#define PCTIM1 (1 << 2)</span>
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<a name="l00061"></a>00061 <span class="preprocessor"></span><span class="preprocessor">#define PCUART0 (1 << 3)</span>
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<a name="l00062"></a>00062 <span class="preprocessor"></span><span class="preprocessor">#define PCUART1 (1 << 4)</span>
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<a name="l00063"></a>00063 <span class="preprocessor"></span><span class="preprocessor">#define PCPWM0 (1 << 5)</span>
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<a name="l00064"></a>00064 <span class="preprocessor"></span><span class="preprocessor">#define PCI2C0 (1 << 7)</span>
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<a name="l00065"></a>00065 <span class="preprocessor"></span><span class="preprocessor">#define PCSPI0 (1 << 8)</span>
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<a name="l00066"></a>00066 <span class="preprocessor"></span><span class="preprocessor">#define PCRTC (1 << 9)</span>
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<a name="l00067"></a>00067 <span class="preprocessor"></span><span class="preprocessor">#define PCSPI1 (1 << 10)</span>
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<a name="l00068"></a>00068 <span class="preprocessor"></span><span class="preprocessor">#define PCAD0 (1 << 12)</span>
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<a name="l00069"></a>00069 <span class="preprocessor"></span><span class="preprocessor">#define PCI2C1 (1 << 19)</span>
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<a name="l00070"></a>00070 <span class="preprocessor"></span><span class="preprocessor">#define PCAD1 (1 << 20)</span>
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<a name="l00071"></a>00071 <span class="preprocessor"></span><span class="preprocessor">#define PCUSB (1 << 31)</span>
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||
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<a name="l00072"></a>00072 <span class="preprocessor"></span><span class="preprocessor">#define PCALL (PCTIM0 | PCTIM1 | PCUART0 | PCUART1 | \</span>
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<a name="l00073"></a>00073 <span class="preprocessor"> PCPWM0 | PCI2C0 | PCSPI0 | PCRTC | PCSPI1 | \</span>
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<a name="l00074"></a>00074 <span class="preprocessor"> PCAD0 | PCI2C1 | PCAD1 | PCUSB)</span>
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<a name="l00075"></a>00075 <span class="preprocessor"></span>
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||
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<a name="l00076"></a>00076 <span class="preprocessor">#define EINT0 1</span>
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||
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<a name="l00077"></a>00077 <span class="preprocessor"></span><span class="preprocessor">#define EINT1 2</span>
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||
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<a name="l00078"></a>00078 <span class="preprocessor"></span><span class="preprocessor">#define EINT2 4</span>
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||
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<a name="l00079"></a>00079 <span class="preprocessor"></span><span class="preprocessor">#define EINT3 8</span>
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||
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<a name="l00080"></a>00080 <span class="preprocessor"></span>
|
||
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<a name="l00081"></a>00081 <span class="preprocessor">#define EXTWAKE0 1</span>
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||
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<a name="l00082"></a>00082 <span class="preprocessor"></span><span class="preprocessor">#define EXTWAKE1 2</span>
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||
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<a name="l00083"></a>00083 <span class="preprocessor"></span><span class="preprocessor">#define EXTWAKE2 4</span>
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||
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<a name="l00084"></a>00084 <span class="preprocessor"></span><span class="preprocessor">#define EXTWAKE3 8</span>
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||
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<a name="l00085"></a>00085 <span class="preprocessor"></span><span class="preprocessor">#define USBWAKE 0x20</span>
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||
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|
<a name="l00086"></a>00086 <span class="preprocessor"></span><span class="preprocessor">#define BODWAKE 0x4000</span>
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||
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<a name="l00087"></a>00087 <span class="preprocessor"></span><span class="preprocessor">#define RTCWAKE 0x8000</span>
|
||
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<a name="l00088"></a>00088 <span class="preprocessor"></span>
|
||
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<a name="l00089"></a>00089 <span class="preprocessor">#define EXTMODE0 1</span>
|
||
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|
<a name="l00090"></a>00090 <span class="preprocessor"></span><span class="preprocessor">#define EXTMODE1 2</span>
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||
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|
<a name="l00091"></a>00091 <span class="preprocessor"></span><span class="preprocessor">#define EXTMODE2 4</span>
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||
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|
<a name="l00092"></a>00092 <span class="preprocessor"></span><span class="preprocessor">#define EXTMODE3 8</span>
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||
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|
<a name="l00093"></a>00093 <span class="preprocessor"></span>
|
||
|
|
<a name="l00094"></a>00094 <span class="preprocessor">#define EXTPOLAR0 1</span>
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||
|
|
<a name="l00095"></a>00095 <span class="preprocessor"></span><span class="preprocessor">#define EXTPOLAR1 2</span>
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||
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<a name="l00096"></a>00096 <span class="preprocessor"></span><span class="preprocessor">#define EXTPOLAR2 4</span>
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||
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<a name="l00097"></a>00097 <span class="preprocessor"></span><span class="preprocessor">#define EXTPOLAR3 8</span>
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||
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<a name="l00098"></a>00098 <span class="preprocessor"></span>
|
||
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<a name="l00099"></a>00099 <span class="keyword">typedef</span> <span class="keyword">struct </span>{
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<a name="l00100"></a>00100 <a class="code" href="group___a_r_m_c_mx___n_v_i_c.html#gaaf485fff865c489bedf668cb8a478a68">IOREG32</a> PLL_CON;
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||
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<a name="l00101"></a>00101 <a class="code" href="group___a_r_m_c_mx___n_v_i_c.html#gaaf485fff865c489bedf668cb8a478a68">IOREG32</a> PLL_CFG;
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||
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<a name="l00102"></a>00102 <a class="code" href="group___a_r_m_c_mx___n_v_i_c.html#gaaf485fff865c489bedf668cb8a478a68">IOREG32</a> PLL_STAT;
|
||
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<a name="l00103"></a>00103 <a class="code" href="group___a_r_m_c_mx___n_v_i_c.html#gaaf485fff865c489bedf668cb8a478a68">IOREG32</a> PLL_FEED;
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<a name="l00104"></a>00104 } PLL;
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<a name="l00105"></a>00105
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<a name="l00106"></a>00106 <span class="preprocessor">#define PLL0Base ((PLL *)0xE01FC080)</span>
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||
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|
<a name="l00107"></a>00107 <span class="preprocessor"></span><span class="preprocessor">#define PLL1Base ((PLL *)0xE01FC0A0)</span>
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||
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|
<a name="l00108"></a>00108 <span class="preprocessor"></span><span class="preprocessor">#define PLL0CON (PLL0Base->PLL_CON)</span>
|
||
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|
<a name="l00109"></a>00109 <span class="preprocessor"></span><span class="preprocessor">#define PLL0CFG (PLL0Base->PLL_CFG)</span>
|
||
|
|
<a name="l00110"></a>00110 <span class="preprocessor"></span><span class="preprocessor">#define PLL0STAT (PLL0Base->PLL_STAT)</span>
|
||
|
|
<a name="l00111"></a>00111 <span class="preprocessor"></span><span class="preprocessor">#define PLL0FEED (PLL0Base->PLL_FEED)</span>
|
||
|
|
<a name="l00112"></a>00112 <span class="preprocessor"></span><span class="preprocessor">#define PLL1CON (PLL1Base->PLL_CON)</span>
|
||
|
|
<a name="l00113"></a>00113 <span class="preprocessor"></span><span class="preprocessor">#define PLL1CFG (PLL1Base->PLL_CFG)</span>
|
||
|
|
<a name="l00114"></a>00114 <span class="preprocessor"></span><span class="preprocessor">#define PLL1STAT (PLL1Base->PLL_STAT)</span>
|
||
|
|
<a name="l00115"></a>00115 <span class="preprocessor"></span><span class="preprocessor">#define PLL1FEED (PLL1Base->PLL_FEED)</span>
|
||
|
|
<a name="l00116"></a>00116 <span class="preprocessor"></span>
|
||
|
|
<a name="l00117"></a>00117 <span class="comment">/*</span>
|
||
|
|
<a name="l00118"></a>00118 <span class="comment"> * Pins.</span>
|
||
|
|
<a name="l00119"></a>00119 <span class="comment"> */</span>
|
||
|
|
<a name="l00120"></a>00120 <span class="keyword">typedef</span> <span class="keyword">struct </span>{
|
||
|
|
<a name="l00121"></a>00121 <a class="code" href="group___a_r_m_c_mx___n_v_i_c.html#gaaf485fff865c489bedf668cb8a478a68">IOREG32</a> PS_SEL0;
|
||
|
|
<a name="l00122"></a>00122 <a class="code" href="group___a_r_m_c_mx___n_v_i_c.html#gaaf485fff865c489bedf668cb8a478a68">IOREG32</a> PS_SEL1;
|
||
|
|
<a name="l00123"></a>00123 <a class="code" href="group___a_r_m_c_mx___n_v_i_c.html#gaaf485fff865c489bedf668cb8a478a68">IOREG32</a> _dummy[3];
|
||
|
|
<a name="l00124"></a>00124 <a class="code" href="group___a_r_m_c_mx___n_v_i_c.html#gaaf485fff865c489bedf668cb8a478a68">IOREG32</a> PS_SEL2;
|
||
|
|
<a name="l00125"></a>00125 } PS;
|
||
|
|
<a name="l00126"></a>00126
|
||
|
|
<a name="l00127"></a>00127 <span class="preprocessor">#define PSBase ((PS *)0xE002C000)</span>
|
||
|
|
<a name="l00128"></a>00128 <span class="preprocessor"></span><span class="preprocessor">#define PINSEL0 (PSBase->PS_SEL0)</span>
|
||
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<a name="l00129"></a>00129 <span class="preprocessor"></span><span class="preprocessor">#define PINSEL1 (PSBase->PS_SEL1)</span>
|
||
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|
<a name="l00130"></a>00130 <span class="preprocessor"></span><span class="preprocessor">#define PINSEL2 (PSBase->PS_SEL2)</span>
|
||
|
|
<a name="l00131"></a>00131 <span class="preprocessor"></span>
|
||
|
|
<a name="l00132"></a>00132 <span class="comment">/*</span>
|
||
|
|
<a name="l00133"></a>00133 <span class="comment"> * VIC</span>
|
||
|
|
<a name="l00134"></a>00134 <span class="comment"> */</span>
|
||
|
|
<a name="l00135"></a>00135 <span class="preprocessor">#define SOURCE_WDT 0</span>
|
||
|
|
<a name="l00136"></a>00136 <span class="preprocessor"></span><span class="preprocessor">#define SOURCE_ARMCore0 2</span>
|
||
|
|
<a name="l00137"></a>00137 <span class="preprocessor"></span><span class="preprocessor">#define SOURCE_ARMCore1 3</span>
|
||
|
|
<a name="l00138"></a>00138 <span class="preprocessor"></span><span class="preprocessor">#define SOURCE_Timer0 4</span>
|
||
|
|
<a name="l00139"></a>00139 <span class="preprocessor"></span><span class="preprocessor">#define SOURCE_Timer1 5</span>
|
||
|
|
<a name="l00140"></a>00140 <span class="preprocessor"></span><span class="preprocessor">#define SOURCE_UART0 6</span>
|
||
|
|
<a name="l00141"></a>00141 <span class="preprocessor"></span><span class="preprocessor">#define SOURCE_UART1 7</span>
|
||
|
|
<a name="l00142"></a>00142 <span class="preprocessor"></span><span class="preprocessor">#define SOURCE_PWM0 8</span>
|
||
|
|
<a name="l00143"></a>00143 <span class="preprocessor"></span><span class="preprocessor">#define SOURCE_I2C0 9</span>
|
||
|
|
<a name="l00144"></a>00144 <span class="preprocessor"></span><span class="preprocessor">#define SOURCE_SPI0 10</span>
|
||
|
|
<a name="l00145"></a>00145 <span class="preprocessor"></span><span class="preprocessor">#define SOURCE_SPI1 11</span>
|
||
|
|
<a name="l00146"></a>00146 <span class="preprocessor"></span><span class="preprocessor">#define SOURCE_PLL 12</span>
|
||
|
|
<a name="l00147"></a>00147 <span class="preprocessor"></span><span class="preprocessor">#define SOURCE_RTC 13</span>
|
||
|
|
<a name="l00148"></a>00148 <span class="preprocessor"></span><span class="preprocessor">#define SOURCE_EINT0 14</span>
|
||
|
|
<a name="l00149"></a>00149 <span class="preprocessor"></span><span class="preprocessor">#define SOURCE_EINT1 15</span>
|
||
|
|
<a name="l00150"></a>00150 <span class="preprocessor"></span><span class="preprocessor">#define SOURCE_EINT2 16</span>
|
||
|
|
<a name="l00151"></a>00151 <span class="preprocessor"></span><span class="preprocessor">#define SOURCE_EINT3 17</span>
|
||
|
|
<a name="l00152"></a>00152 <span class="preprocessor"></span><span class="preprocessor">#define SOURCE_ADC0 18</span>
|
||
|
|
<a name="l00153"></a>00153 <span class="preprocessor"></span><span class="preprocessor">#define SOURCE_I2C1 19</span>
|
||
|
|
<a name="l00154"></a>00154 <span class="preprocessor"></span><span class="preprocessor">#define SOURCE_BOD 20</span>
|
||
|
|
<a name="l00155"></a>00155 <span class="preprocessor"></span><span class="preprocessor">#define SOURCE_ADC1 21</span>
|
||
|
|
<a name="l00156"></a>00156 <span class="preprocessor"></span><span class="preprocessor">#define SOURCE_USB 22</span>
|
||
|
|
<a name="l00157"></a>00157 <span class="preprocessor"></span>
|
||
|
|
<a name="l00158"></a>00158 <span class="preprocessor">#define INTMASK(n) (1 << (n))</span>
|
||
|
|
<a name="l00159"></a>00159 <span class="preprocessor"></span><span class="preprocessor">#define ALLINTMASK (INTMASK(SOURCE_WDT) | INTMASK(SOURCE_ARMCore0) | \</span>
|
||
|
|
<a name="l00160"></a>00160 <span class="preprocessor"> INTMASK(SOURCE_ARMCore1) | INTMASK(SOURCE_Timer0) | \</span>
|
||
|
|
<a name="l00161"></a>00161 <span class="preprocessor"> INTMASK(SOURCE_Timer1) | INTMASK(SOURCE_UART0) | \</span>
|
||
|
|
<a name="l00162"></a>00162 <span class="preprocessor"> INTMASK(SOURCE_UART1) | INTMASK(SOURCE_PWM0) | \</span>
|
||
|
|
<a name="l00163"></a>00163 <span class="preprocessor"> INTMASK(SOURCE_I2C0) | INTMASK(SOURCE_SPI0) | \</span>
|
||
|
|
<a name="l00164"></a>00164 <span class="preprocessor"> INTMASK(SOURCE_SPI1) | INTMASK(SOURCE_PLL) | \</span>
|
||
|
|
<a name="l00165"></a>00165 <span class="preprocessor"> INTMASK(SOURCE_RTC) | INTMASK(SOURCE_EINT0) | \</span>
|
||
|
|
<a name="l00166"></a>00166 <span class="preprocessor"> INTMASK(SOURCE_EINT1) | INTMASK(SOURCE_EINT2) | \</span>
|
||
|
|
<a name="l00167"></a>00167 <span class="preprocessor"> INTMASK(SOURCE_EINT3) | INTMASK(SOURCE_ADC0) | \</span>
|
||
|
|
<a name="l00168"></a>00168 <span class="preprocessor"> INTMASK(SOURCE_I2C1) | INTMASK(SOURCE_BOD) | \</span>
|
||
|
|
<a name="l00169"></a>00169 <span class="preprocessor"> INTMASK(SOURCE_ADC1) | INTMASK(SOURCE_USB))</span>
|
||
|
|
<a name="l00170"></a>00170 <span class="preprocessor"></span>
|
||
|
|
<a name="l00171"></a>00171 <span class="keyword">typedef</span> <span class="keyword">struct </span>{
|
||
|
|
<a name="l00172"></a>00172 <a class="code" href="group___a_r_m_c_mx___n_v_i_c.html#gaaf485fff865c489bedf668cb8a478a68">IOREG32</a> VIC_IRQStatus;
|
||
|
|
<a name="l00173"></a>00173 <a class="code" href="group___a_r_m_c_mx___n_v_i_c.html#gaaf485fff865c489bedf668cb8a478a68">IOREG32</a> VIC_FIQStatus;
|
||
|
|
<a name="l00174"></a>00174 <a class="code" href="group___a_r_m_c_mx___n_v_i_c.html#gaaf485fff865c489bedf668cb8a478a68">IOREG32</a> VIC_RawIntr;
|
||
|
|
<a name="l00175"></a>00175 <a class="code" href="group___a_r_m_c_mx___n_v_i_c.html#gaaf485fff865c489bedf668cb8a478a68">IOREG32</a> VIC_IntSelect;
|
||
|
|
<a name="l00176"></a>00176 <a class="code" href="group___a_r_m_c_mx___n_v_i_c.html#gaaf485fff865c489bedf668cb8a478a68">IOREG32</a> VIC_IntEnable;
|
||
|
|
<a name="l00177"></a>00177 <a class="code" href="group___a_r_m_c_mx___n_v_i_c.html#gaaf485fff865c489bedf668cb8a478a68">IOREG32</a> VIC_IntEnClear;
|
||
|
|
<a name="l00178"></a>00178 <a class="code" href="group___a_r_m_c_mx___n_v_i_c.html#gaaf485fff865c489bedf668cb8a478a68">IOREG32</a> VIC_SoftInt;
|
||
|
|
<a name="l00179"></a>00179 <a class="code" href="group___a_r_m_c_mx___n_v_i_c.html#gaaf485fff865c489bedf668cb8a478a68">IOREG32</a> VIC_SoftIntClear;
|
||
|
|
<a name="l00180"></a>00180 <a class="code" href="group___a_r_m_c_mx___n_v_i_c.html#gaaf485fff865c489bedf668cb8a478a68">IOREG32</a> VIC_Protection;
|
||
|
|
<a name="l00181"></a>00181 <a class="code" href="group___a_r_m_c_mx___n_v_i_c.html#gaaf485fff865c489bedf668cb8a478a68">IOREG32</a> unused1[3];
|
||
|
|
<a name="l00182"></a>00182 <a class="code" href="group___a_r_m_c_mx___n_v_i_c.html#gaaf485fff865c489bedf668cb8a478a68">IOREG32</a> VIC_VectAddr;
|
||
|
|
<a name="l00183"></a>00183 <a class="code" href="group___a_r_m_c_mx___n_v_i_c.html#gaaf485fff865c489bedf668cb8a478a68">IOREG32</a> VIC_DefVectAddr;
|
||
|
|
<a name="l00184"></a>00184 <a class="code" href="group___a_r_m_c_mx___n_v_i_c.html#gaaf485fff865c489bedf668cb8a478a68">IOREG32</a> unused2[50];
|
||
|
|
<a name="l00185"></a>00185 <a class="code" href="group___a_r_m_c_mx___n_v_i_c.html#gaaf485fff865c489bedf668cb8a478a68">IOREG32</a> VIC_VectAddrs[16];
|
||
|
|
<a name="l00186"></a>00186 <a class="code" href="group___a_r_m_c_mx___n_v_i_c.html#gaaf485fff865c489bedf668cb8a478a68">IOREG32</a> unused3[48];
|
||
|
|
<a name="l00187"></a>00187 <a class="code" href="group___a_r_m_c_mx___n_v_i_c.html#gaaf485fff865c489bedf668cb8a478a68">IOREG32</a> VIC_VectCntls[16];
|
||
|
|
<a name="l00188"></a>00188 } VIC;
|
||
|
|
<a name="l00189"></a>00189
|
||
|
|
<a name="l00190"></a>00190 <span class="preprocessor">#define VICBase ((VIC *)0xFFFFF000)</span>
|
||
|
|
<a name="l00191"></a>00191 <span class="preprocessor"></span><span class="preprocessor">#define VICVectorsBase ((IOREG32 *)0xFFFFF100)</span>
|
||
|
|
<a name="l00192"></a>00192 <span class="preprocessor"></span><span class="preprocessor">#define VICControlsBase ((IOREG32 *)0xFFFFF200)</span>
|
||
|
|
<a name="l00193"></a>00193 <span class="preprocessor"></span>
|
||
|
|
<a name="l00194"></a>00194 <span class="preprocessor">#define VICIRQStatus (VICBase->VIC_IRQStatus)</span>
|
||
|
|
<a name="l00195"></a>00195 <span class="preprocessor"></span><span class="preprocessor">#define VICFIQStatus (VICBase->VIC_FIQStatus)</span>
|
||
|
|
<a name="l00196"></a>00196 <span class="preprocessor"></span><span class="preprocessor">#define VICRawIntr (VICBase->VIC_RawIntr)</span>
|
||
|
|
<a name="l00197"></a>00197 <span class="preprocessor"></span><span class="preprocessor">#define VICIntSelect (VICBase->VIC_IntSelect)</span>
|
||
|
|
<a name="l00198"></a>00198 <span class="preprocessor"></span><span class="preprocessor">#define VICIntEnable (VICBase->VIC_IntEnable)</span>
|
||
|
|
<a name="l00199"></a>00199 <span class="preprocessor"></span><span class="preprocessor">#define VICIntEnClear (VICBase->VIC_IntEnClear)</span>
|
||
|
|
<a name="l00200"></a>00200 <span class="preprocessor"></span><span class="preprocessor">#define VICSoftInt (VICBase->VIC_SoftInt)</span>
|
||
|
|
<a name="l00201"></a>00201 <span class="preprocessor"></span><span class="preprocessor">#define VICSoftIntClear (VICBase->VIC_SoftIntClear)</span>
|
||
|
|
<a name="l00202"></a>00202 <span class="preprocessor"></span><span class="preprocessor">#define VICProtection (VICBase->VIC_Protection)</span>
|
||
|
|
<a name="l00203"></a>00203 <span class="preprocessor"></span><span class="preprocessor">#define VICVectAddr (VICBase->VIC_VectAddr)</span>
|
||
|
|
<a name="l00204"></a>00204 <span class="preprocessor"></span><span class="preprocessor">#define VICDefVectAddr (VICBase->VIC_DefVectAddr)</span>
|
||
|
|
<a name="l00205"></a>00205 <span class="preprocessor"></span>
|
||
|
|
<a name="l00206"></a>00206 <span class="preprocessor">#define VICVectAddrs(n) (VICBase->VIC_VectAddrs[n])</span>
|
||
|
|
<a name="l00207"></a>00207 <span class="preprocessor"></span><span class="preprocessor">#define VICVectCntls(n) (VICBase->VIC_VectCntls[n])</span>
|
||
|
|
<a name="l00208"></a>00208 <span class="preprocessor"></span>
|
||
|
|
<a name="l00209"></a>00209 <span class="comment">/*</span>
|
||
|
|
<a name="l00210"></a>00210 <span class="comment"> * MAM.</span>
|
||
|
|
<a name="l00211"></a>00211 <span class="comment"> */</span>
|
||
|
|
<a name="l00212"></a>00212 <span class="keyword">typedef</span> <span class="keyword">struct </span>{
|
||
|
|
<a name="l00213"></a>00213 <a class="code" href="group___a_r_m_c_mx___n_v_i_c.html#gaaf485fff865c489bedf668cb8a478a68">IOREG32</a> MAM_Control;
|
||
|
|
<a name="l00214"></a>00214 <a class="code" href="group___a_r_m_c_mx___n_v_i_c.html#gaaf485fff865c489bedf668cb8a478a68">IOREG32</a> MAM_Timing;
|
||
|
|
<a name="l00215"></a>00215 } MAM;
|
||
|
|
<a name="l00216"></a>00216
|
||
|
|
<a name="l00217"></a>00217 <span class="preprocessor">#define MAMBase ((MAM *)0xE01FC000)</span>
|
||
|
|
<a name="l00218"></a>00218 <span class="preprocessor"></span><span class="preprocessor">#define MAMCR (MAMBase->MAM_Control)</span>
|
||
|
|
<a name="l00219"></a>00219 <span class="preprocessor"></span><span class="preprocessor">#define MAMTIM (MAMBase->MAM_Timing)</span>
|
||
|
|
<a name="l00220"></a>00220 <span class="preprocessor"></span>
|
||
|
|
<a name="l00221"></a>00221 <span class="comment">/*</span>
|
||
|
|
<a name="l00222"></a>00222 <span class="comment"> * GPIO - FIO.</span>
|
||
|
|
<a name="l00223"></a>00223 <span class="comment"> */</span>
|
||
|
|
<a name="l00224"></a>00224 <span class="keyword">typedef</span> <span class="keyword">struct </span>{
|
||
|
|
<a name="l00225"></a>00225 <a class="code" href="group___a_r_m_c_mx___n_v_i_c.html#gaaf485fff865c489bedf668cb8a478a68">IOREG32</a> IO_PIN;
|
||
|
|
<a name="l00226"></a>00226 <a class="code" href="group___a_r_m_c_mx___n_v_i_c.html#gaaf485fff865c489bedf668cb8a478a68">IOREG32</a> IO_SET;
|
||
|
|
<a name="l00227"></a>00227 <a class="code" href="group___a_r_m_c_mx___n_v_i_c.html#gaaf485fff865c489bedf668cb8a478a68">IOREG32</a> IO_DIR;
|
||
|
|
<a name="l00228"></a>00228 <a class="code" href="group___a_r_m_c_mx___n_v_i_c.html#gaaf485fff865c489bedf668cb8a478a68">IOREG32</a> IO_CLR;
|
||
|
|
<a name="l00229"></a>00229 } GPIO;
|
||
|
|
<a name="l00230"></a>00230
|
||
|
|
<a name="l00231"></a>00231 <span class="preprocessor">#define GPIO0Base ((GPIO *)0xE0028000)</span>
|
||
|
|
<a name="l00232"></a>00232 <span class="preprocessor"></span><span class="preprocessor">#define IO0PIN (GPIO0Base->IO_PIN)</span>
|
||
|
|
<a name="l00233"></a>00233 <span class="preprocessor"></span><span class="preprocessor">#define IO0SET (GPIO0Base->IO_SET)</span>
|
||
|
|
<a name="l00234"></a>00234 <span class="preprocessor"></span><span class="preprocessor">#define IO0DIR (GPIO0Base->IO_DIR)</span>
|
||
|
|
<a name="l00235"></a>00235 <span class="preprocessor"></span><span class="preprocessor">#define IO0CLR (GPIO0Base->IO_CLR)</span>
|
||
|
|
<a name="l00236"></a>00236 <span class="preprocessor"></span>
|
||
|
|
<a name="l00237"></a>00237 <span class="preprocessor">#define GPIO1Base ((GPIO *)0xE0028010)</span>
|
||
|
|
<a name="l00238"></a>00238 <span class="preprocessor"></span><span class="preprocessor">#define IO1PIN (GPIO1Base->IO_PIN)</span>
|
||
|
|
<a name="l00239"></a>00239 <span class="preprocessor"></span><span class="preprocessor">#define IO1SET (GPIO1Base->IO_SET)</span>
|
||
|
|
<a name="l00240"></a>00240 <span class="preprocessor"></span><span class="preprocessor">#define IO1DIR (GPIO1Base->IO_DIR)</span>
|
||
|
|
<a name="l00241"></a>00241 <span class="preprocessor"></span><span class="preprocessor">#define IO1CLR (GPIO1Base->IO_CLR)</span>
|
||
|
|
<a name="l00242"></a>00242 <span class="preprocessor"></span>
|
||
|
|
<a name="l00243"></a>00243 <span class="keyword">typedef</span> <span class="keyword">struct </span>{
|
||
|
|
<a name="l00244"></a>00244 <a class="code" href="group___a_r_m_c_mx___n_v_i_c.html#gaaf485fff865c489bedf668cb8a478a68">IOREG32</a> FIO_DIR;
|
||
|
|
<a name="l00245"></a>00245 <a class="code" href="group___a_r_m_c_mx___n_v_i_c.html#gaaf485fff865c489bedf668cb8a478a68">IOREG32</a> unused1;
|
||
|
|
<a name="l00246"></a>00246 <a class="code" href="group___a_r_m_c_mx___n_v_i_c.html#gaaf485fff865c489bedf668cb8a478a68">IOREG32</a> unused2;
|
||
|
|
<a name="l00247"></a>00247 <a class="code" href="group___a_r_m_c_mx___n_v_i_c.html#gaaf485fff865c489bedf668cb8a478a68">IOREG32</a> unused3;
|
||
|
|
<a name="l00248"></a>00248 <a class="code" href="group___a_r_m_c_mx___n_v_i_c.html#gaaf485fff865c489bedf668cb8a478a68">IOREG32</a> FIO_MASK;
|
||
|
|
<a name="l00249"></a>00249 <a class="code" href="group___a_r_m_c_mx___n_v_i_c.html#gaaf485fff865c489bedf668cb8a478a68">IOREG32</a> FIO_PIN;
|
||
|
|
<a name="l00250"></a>00250 <a class="code" href="group___a_r_m_c_mx___n_v_i_c.html#gaaf485fff865c489bedf668cb8a478a68">IOREG32</a> FIO_SET;
|
||
|
|
<a name="l00251"></a>00251 <a class="code" href="group___a_r_m_c_mx___n_v_i_c.html#gaaf485fff865c489bedf668cb8a478a68">IOREG32</a> FIO_CLR;
|
||
|
|
<a name="l00252"></a>00252 } FIO;
|
||
|
|
<a name="l00253"></a>00253
|
||
|
|
<a name="l00254"></a>00254 <span class="preprocessor">#define FIO0Base ((FIO *)0x3FFFC000)</span>
|
||
|
|
<a name="l00255"></a>00255 <span class="preprocessor"></span><span class="preprocessor">#define FIO0DIR (FIO0Base->FIO_DIR)</span>
|
||
|
|
<a name="l00256"></a>00256 <span class="preprocessor"></span><span class="preprocessor">#define FIO0MASK (FIO0Base->FIO_MASK)</span>
|
||
|
|
<a name="l00257"></a>00257 <span class="preprocessor"></span><span class="preprocessor">#define FIO0PIN (FIO0Base->FIO_PIN)</span>
|
||
|
|
<a name="l00258"></a>00258 <span class="preprocessor"></span><span class="preprocessor">#define FIO0SET (FIO0Base->FIO_SET)</span>
|
||
|
|
<a name="l00259"></a>00259 <span class="preprocessor"></span><span class="preprocessor">#define FIO0CLR (FIO0Base->FIO_CLR)</span>
|
||
|
|
<a name="l00260"></a>00260 <span class="preprocessor"></span>
|
||
|
|
<a name="l00261"></a>00261 <span class="preprocessor">#define FIO1Base ((FIO *)0x3FFFC020)</span>
|
||
|
|
<a name="l00262"></a>00262 <span class="preprocessor"></span><span class="preprocessor">#define FIO1DIR (FIO1Base->FIO_DIR)</span>
|
||
|
|
<a name="l00263"></a>00263 <span class="preprocessor"></span><span class="preprocessor">#define FIO1MASK (FIO1Base->FIO_MASK)</span>
|
||
|
|
<a name="l00264"></a>00264 <span class="preprocessor"></span><span class="preprocessor">#define FIO1PIN (FIO1Base->FIO_PIN)</span>
|
||
|
|
<a name="l00265"></a>00265 <span class="preprocessor"></span><span class="preprocessor">#define FIO1SET (FIO1Base->FIO_SET)</span>
|
||
|
|
<a name="l00266"></a>00266 <span class="preprocessor"></span><span class="preprocessor">#define FIO1CLR (FIO1Base->FIO_CLR)</span>
|
||
|
|
<a name="l00267"></a>00267 <span class="preprocessor"></span>
|
||
|
|
<a name="l00268"></a>00268 <span class="comment">/*</span>
|
||
|
|
<a name="l00269"></a>00269 <span class="comment"> * UART.</span>
|
||
|
|
<a name="l00270"></a>00270 <span class="comment"> */</span>
|
||
|
|
<a name="l00271"></a>00271 <span class="keyword">typedef</span> <span class="keyword">struct </span>{
|
||
|
|
<a name="l00272"></a>00272 <span class="keyword">union </span>{
|
||
|
|
<a name="l00273"></a>00273 <a class="code" href="group___a_r_m_c_mx___n_v_i_c.html#gaaf485fff865c489bedf668cb8a478a68">IOREG32</a> UART_RBR;
|
||
|
|
<a name="l00274"></a>00274 <a class="code" href="group___a_r_m_c_mx___n_v_i_c.html#gaaf485fff865c489bedf668cb8a478a68">IOREG32</a> UART_THR;
|
||
|
|
<a name="l00275"></a>00275 <a class="code" href="group___a_r_m_c_mx___n_v_i_c.html#gaaf485fff865c489bedf668cb8a478a68">IOREG32</a> UART_DLL;
|
||
|
|
<a name="l00276"></a>00276 };
|
||
|
|
<a name="l00277"></a>00277 <span class="keyword">union </span>{
|
||
|
|
<a name="l00278"></a>00278 <a class="code" href="group___a_r_m_c_mx___n_v_i_c.html#gaaf485fff865c489bedf668cb8a478a68">IOREG32</a> UART_IER;
|
||
|
|
<a name="l00279"></a>00279 <a class="code" href="group___a_r_m_c_mx___n_v_i_c.html#gaaf485fff865c489bedf668cb8a478a68">IOREG32</a> UART_DLM;
|
||
|
|
<a name="l00280"></a>00280 };
|
||
|
|
<a name="l00281"></a>00281 <span class="keyword">union </span>{
|
||
|
|
<a name="l00282"></a>00282 <a class="code" href="group___a_r_m_c_mx___n_v_i_c.html#gaaf485fff865c489bedf668cb8a478a68">IOREG32</a> UART_IIR;
|
||
|
|
<a name="l00283"></a>00283 <a class="code" href="group___a_r_m_c_mx___n_v_i_c.html#gaaf485fff865c489bedf668cb8a478a68">IOREG32</a> UART_FCR;
|
||
|
|
<a name="l00284"></a>00284 };
|
||
|
|
<a name="l00285"></a>00285 <a class="code" href="group___a_r_m_c_mx___n_v_i_c.html#gaaf485fff865c489bedf668cb8a478a68">IOREG32</a> UART_LCR;
|
||
|
|
<a name="l00286"></a>00286 <a class="code" href="group___a_r_m_c_mx___n_v_i_c.html#gaaf485fff865c489bedf668cb8a478a68">IOREG32</a> UART_MCR; <span class="comment">// UART1 only</span>
|
||
|
|
<a name="l00287"></a>00287 <a class="code" href="group___a_r_m_c_mx___n_v_i_c.html#gaaf485fff865c489bedf668cb8a478a68">IOREG32</a> UART_LSR;
|
||
|
|
<a name="l00288"></a>00288 <a class="code" href="group___a_r_m_c_mx___n_v_i_c.html#gaaf485fff865c489bedf668cb8a478a68">IOREG32</a> unused18;
|
||
|
|
<a name="l00289"></a>00289 <a class="code" href="group___a_r_m_c_mx___n_v_i_c.html#gaaf485fff865c489bedf668cb8a478a68">IOREG32</a> UART_SCR;
|
||
|
|
<a name="l00290"></a>00290 <a class="code" href="group___a_r_m_c_mx___n_v_i_c.html#gaaf485fff865c489bedf668cb8a478a68">IOREG32</a> UART_ACR;
|
||
|
|
<a name="l00291"></a>00291 <a class="code" href="group___a_r_m_c_mx___n_v_i_c.html#gaaf485fff865c489bedf668cb8a478a68">IOREG32</a> unused24;
|
||
|
|
<a name="l00292"></a>00292 <a class="code" href="group___a_r_m_c_mx___n_v_i_c.html#gaaf485fff865c489bedf668cb8a478a68">IOREG32</a> UART_FDR;
|
||
|
|
<a name="l00293"></a>00293 <a class="code" href="group___a_r_m_c_mx___n_v_i_c.html#gaaf485fff865c489bedf668cb8a478a68">IOREG32</a> unused2C;
|
||
|
|
<a name="l00294"></a>00294 <a class="code" href="group___a_r_m_c_mx___n_v_i_c.html#gaaf485fff865c489bedf668cb8a478a68">IOREG32</a> UART_TER;
|
||
|
|
<a name="l00295"></a>00295 } UART;
|
||
|
|
<a name="l00296"></a>00296
|
||
|
|
<a name="l00297"></a>00297 <span class="preprocessor">#define U0Base ((UART *)0xE000C000)</span>
|
||
|
|
<a name="l00298"></a>00298 <span class="preprocessor"></span><span class="preprocessor">#define U0RBR (U0Base->UART_RBR)</span>
|
||
|
|
<a name="l00299"></a>00299 <span class="preprocessor"></span><span class="preprocessor">#define U0THR (U0Base->UART_THR)</span>
|
||
|
|
<a name="l00300"></a>00300 <span class="preprocessor"></span><span class="preprocessor">#define U0DLL (U0Base->UART_DLL)</span>
|
||
|
|
<a name="l00301"></a>00301 <span class="preprocessor"></span><span class="preprocessor">#define U0IER (U0Base->UART_IER)</span>
|
||
|
|
<a name="l00302"></a>00302 <span class="preprocessor"></span><span class="preprocessor">#define U0DLM (U0Base->UART_DLM)</span>
|
||
|
|
<a name="l00303"></a>00303 <span class="preprocessor"></span><span class="preprocessor">#define U0IIR (U0Base->UART_IIR)</span>
|
||
|
|
<a name="l00304"></a>00304 <span class="preprocessor"></span><span class="preprocessor">#define U0FCR (U0Base->UART_FCR)</span>
|
||
|
|
<a name="l00305"></a>00305 <span class="preprocessor"></span><span class="preprocessor">#define U0LCR (U0Base->UART_LCR)</span>
|
||
|
|
<a name="l00306"></a>00306 <span class="preprocessor"></span><span class="preprocessor">#define U0LSR (U0Base->UART_LSR)</span>
|
||
|
|
<a name="l00307"></a>00307 <span class="preprocessor"></span><span class="preprocessor">#define U0SCR (U0Base->UART_SCR)</span>
|
||
|
|
<a name="l00308"></a>00308 <span class="preprocessor"></span><span class="preprocessor">#define U0ACR (U0Base->UART_ACR)</span>
|
||
|
|
<a name="l00309"></a>00309 <span class="preprocessor"></span><span class="preprocessor">#define U0FDR (U0Base->UART_FDR)</span>
|
||
|
|
<a name="l00310"></a>00310 <span class="preprocessor"></span><span class="preprocessor">#define U0TER (U0Base->UART_TER)</span>
|
||
|
|
<a name="l00311"></a>00311 <span class="preprocessor"></span>
|
||
|
|
<a name="l00312"></a>00312 <span class="preprocessor">#define U1Base ((UART *)0xE0010000)</span>
|
||
|
|
<a name="l00313"></a>00313 <span class="preprocessor"></span><span class="preprocessor">#define U1RBR (U1Base->UART_RBR)</span>
|
||
|
|
<a name="l00314"></a>00314 <span class="preprocessor"></span><span class="preprocessor">#define U1THR (U1Base->UART_THR)</span>
|
||
|
|
<a name="l00315"></a>00315 <span class="preprocessor"></span><span class="preprocessor">#define U1DLL (U1Base->UART_DLL)</span>
|
||
|
|
<a name="l00316"></a>00316 <span class="preprocessor"></span><span class="preprocessor">#define U1IER (U1Base->UART_IER)</span>
|
||
|
|
<a name="l00317"></a>00317 <span class="preprocessor"></span><span class="preprocessor">#define U1DLM (U1Base->UART_DLM)</span>
|
||
|
|
<a name="l00318"></a>00318 <span class="preprocessor"></span><span class="preprocessor">#define U1IIR (U1Base->UART_IIR)</span>
|
||
|
|
<a name="l00319"></a>00319 <span class="preprocessor"></span><span class="preprocessor">#define U1FCR (U1Base->UART_FCR)</span>
|
||
|
|
<a name="l00320"></a>00320 <span class="preprocessor"></span><span class="preprocessor">#define U1MCR (U1Base->UART_MCR)</span>
|
||
|
|
<a name="l00321"></a>00321 <span class="preprocessor"></span><span class="preprocessor">#define U1LCR (U1Base->UART_LCR)</span>
|
||
|
|
<a name="l00322"></a>00322 <span class="preprocessor"></span><span class="preprocessor">#define U1LSR (U1Base->UART_LSR)</span>
|
||
|
|
<a name="l00323"></a>00323 <span class="preprocessor"></span><span class="preprocessor">#define U1SCR (U1Base->UART_SCR)</span>
|
||
|
|
<a name="l00324"></a>00324 <span class="preprocessor"></span><span class="preprocessor">#define U1ACR (U1Base->UART_ACR)</span>
|
||
|
|
<a name="l00325"></a>00325 <span class="preprocessor"></span><span class="preprocessor">#define U1FDR (U1Base->UART_FDR)</span>
|
||
|
|
<a name="l00326"></a>00326 <span class="preprocessor"></span><span class="preprocessor">#define U1TER (U1Base->UART_TER)</span>
|
||
|
|
<a name="l00327"></a>00327 <span class="preprocessor"></span>
|
||
|
|
<a name="l00328"></a>00328 <span class="preprocessor">#define IIR_SRC_MASK 0x0F</span>
|
||
|
|
<a name="l00329"></a>00329 <span class="preprocessor"></span><span class="preprocessor">#define IIR_SRC_NONE 0x01</span>
|
||
|
|
<a name="l00330"></a>00330 <span class="preprocessor"></span><span class="preprocessor">#define IIR_SRC_TX 0x02</span>
|
||
|
|
<a name="l00331"></a>00331 <span class="preprocessor"></span><span class="preprocessor">#define IIR_SRC_RX 0x04</span>
|
||
|
|
<a name="l00332"></a>00332 <span class="preprocessor"></span><span class="preprocessor">#define IIR_SRC_ERROR 0x06</span>
|
||
|
|
<a name="l00333"></a>00333 <span class="preprocessor"></span><span class="preprocessor">#define IIR_SRC_TIMEOUT 0x0C</span>
|
||
|
|
<a name="l00334"></a>00334 <span class="preprocessor"></span>
|
||
|
|
<a name="l00335"></a>00335 <span class="preprocessor">#define IER_RBR 1</span>
|
||
|
|
<a name="l00336"></a>00336 <span class="preprocessor"></span><span class="preprocessor">#define IER_THRE 2</span>
|
||
|
|
<a name="l00337"></a>00337 <span class="preprocessor"></span><span class="preprocessor">#define IER_STATUS 4</span>
|
||
|
|
<a name="l00338"></a>00338 <span class="preprocessor"></span>
|
||
|
|
<a name="l00339"></a>00339 <span class="preprocessor">#define IIR_INT_PENDING 1</span>
|
||
|
|
<a name="l00340"></a>00340 <span class="preprocessor"></span>
|
||
|
|
<a name="l00341"></a>00341 <span class="preprocessor">#define LCR_WL5 0</span>
|
||
|
|
<a name="l00342"></a>00342 <span class="preprocessor"></span><span class="preprocessor">#define LCR_WL6 1</span>
|
||
|
|
<a name="l00343"></a>00343 <span class="preprocessor"></span><span class="preprocessor">#define LCR_WL7 2</span>
|
||
|
|
<a name="l00344"></a>00344 <span class="preprocessor"></span><span class="preprocessor">#define LCR_WL8 3</span>
|
||
|
|
<a name="l00345"></a>00345 <span class="preprocessor"></span><span class="preprocessor">#define LCR_STOP1 0</span>
|
||
|
|
<a name="l00346"></a>00346 <span class="preprocessor"></span><span class="preprocessor">#define LCR_STOP2 4</span>
|
||
|
|
<a name="l00347"></a>00347 <span class="preprocessor"></span><span class="preprocessor">#define LCR_NOPARITY 0</span>
|
||
|
|
<a name="l00348"></a>00348 <span class="preprocessor"></span><span class="preprocessor">#define LCR_PARITYODD 0x08</span>
|
||
|
|
<a name="l00349"></a>00349 <span class="preprocessor"></span><span class="preprocessor">#define LCR_PARITYEVEN 0x18</span>
|
||
|
|
<a name="l00350"></a>00350 <span class="preprocessor"></span><span class="preprocessor">#define LCR_PARITYONE 0x28</span>
|
||
|
|
<a name="l00351"></a>00351 <span class="preprocessor"></span><span class="preprocessor">#define LCR_PARITYZERO 0x38</span>
|
||
|
|
<a name="l00352"></a>00352 <span class="preprocessor"></span><span class="preprocessor">#define LCR_BREAK_ON 0x40</span>
|
||
|
|
<a name="l00353"></a>00353 <span class="preprocessor"></span><span class="preprocessor">#define LCR_DLAB 0x80</span>
|
||
|
|
<a name="l00354"></a>00354 <span class="preprocessor"></span>
|
||
|
|
<a name="l00355"></a>00355 <span class="preprocessor">#define FCR_ENABLE 1</span>
|
||
|
|
<a name="l00356"></a>00356 <span class="preprocessor"></span><span class="preprocessor">#define FCR_RXRESET 2</span>
|
||
|
|
<a name="l00357"></a>00357 <span class="preprocessor"></span><span class="preprocessor">#define FCR_TXRESET 4</span>
|
||
|
|
<a name="l00358"></a>00358 <span class="preprocessor"></span><span class="preprocessor">#define FCR_TRIGGER0 0</span>
|
||
|
|
<a name="l00359"></a>00359 <span class="preprocessor"></span><span class="preprocessor">#define FCR_TRIGGER1 0x40</span>
|
||
|
|
<a name="l00360"></a>00360 <span class="preprocessor"></span><span class="preprocessor">#define FCR_TRIGGER2 0x80</span>
|
||
|
|
<a name="l00361"></a>00361 <span class="preprocessor"></span><span class="preprocessor">#define FCR_TRIGGER3 0xC0</span>
|
||
|
|
<a name="l00362"></a>00362 <span class="preprocessor"></span>
|
||
|
|
<a name="l00363"></a>00363 <span class="preprocessor">#define LSR_RBR_FULL 1</span>
|
||
|
|
<a name="l00364"></a>00364 <span class="preprocessor"></span><span class="preprocessor">#define LSR_OVERRUN 2</span>
|
||
|
|
<a name="l00365"></a>00365 <span class="preprocessor"></span><span class="preprocessor">#define LSR_PARITY 4</span>
|
||
|
|
<a name="l00366"></a>00366 <span class="preprocessor"></span><span class="preprocessor">#define LSR_FRAMING 8</span>
|
||
|
|
<a name="l00367"></a>00367 <span class="preprocessor"></span><span class="preprocessor">#define LSR_BREAK 0x10</span>
|
||
|
|
<a name="l00368"></a>00368 <span class="preprocessor"></span><span class="preprocessor">#define LSR_THRE 0x20</span>
|
||
|
|
<a name="l00369"></a>00369 <span class="preprocessor"></span><span class="preprocessor">#define LSR_TEMT 0x40</span>
|
||
|
|
<a name="l00370"></a>00370 <span class="preprocessor"></span><span class="preprocessor">#define LSR_RXFE 0x80</span>
|
||
|
|
<a name="l00371"></a>00371 <span class="preprocessor"></span>
|
||
|
|
<a name="l00372"></a>00372 <span class="preprocessor">#define TER_ENABLE 0x80</span>
|
||
|
|
<a name="l00373"></a>00373 <span class="preprocessor"></span>
|
||
|
|
<a name="l00374"></a>00374 <span class="comment">/*</span>
|
||
|
|
<a name="l00375"></a>00375 <span class="comment"> * SSP.</span>
|
||
|
|
<a name="l00376"></a>00376 <span class="comment"> */</span>
|
||
|
|
<a name="l00377"></a>00377 <span class="keyword">typedef</span> <span class="keyword">struct </span>{
|
||
|
|
<a name="l00378"></a>00378 <a class="code" href="group___a_r_m_c_mx___n_v_i_c.html#gaaf485fff865c489bedf668cb8a478a68">IOREG32</a> SSP_CR0;
|
||
|
|
<a name="l00379"></a>00379 <a class="code" href="group___a_r_m_c_mx___n_v_i_c.html#gaaf485fff865c489bedf668cb8a478a68">IOREG32</a> SSP_CR1;
|
||
|
|
<a name="l00380"></a>00380 <a class="code" href="group___a_r_m_c_mx___n_v_i_c.html#gaaf485fff865c489bedf668cb8a478a68">IOREG32</a> SSP_DR;
|
||
|
|
<a name="l00381"></a>00381 <a class="code" href="group___a_r_m_c_mx___n_v_i_c.html#gaaf485fff865c489bedf668cb8a478a68">IOREG32</a> SSP_SR;
|
||
|
|
<a name="l00382"></a>00382 <a class="code" href="group___a_r_m_c_mx___n_v_i_c.html#gaaf485fff865c489bedf668cb8a478a68">IOREG32</a> SSP_CPSR;
|
||
|
|
<a name="l00383"></a>00383 <a class="code" href="group___a_r_m_c_mx___n_v_i_c.html#gaaf485fff865c489bedf668cb8a478a68">IOREG32</a> SSP_IMSC;
|
||
|
|
<a name="l00384"></a>00384 <a class="code" href="group___a_r_m_c_mx___n_v_i_c.html#gaaf485fff865c489bedf668cb8a478a68">IOREG32</a> SSP_RIS;
|
||
|
|
<a name="l00385"></a>00385 <a class="code" href="group___a_r_m_c_mx___n_v_i_c.html#gaaf485fff865c489bedf668cb8a478a68">IOREG32</a> SSP_MIS;
|
||
|
|
<a name="l00386"></a>00386 <a class="code" href="group___a_r_m_c_mx___n_v_i_c.html#gaaf485fff865c489bedf668cb8a478a68">IOREG32</a> SSP_ICR;
|
||
|
|
<a name="l00387"></a>00387 } SSP;
|
||
|
|
<a name="l00388"></a>00388
|
||
|
|
<a name="l00389"></a>00389 <span class="preprocessor">#define SSPBase ((SSP *)0xE0068000)</span>
|
||
|
|
<a name="l00390"></a>00390 <span class="preprocessor"></span><span class="preprocessor">#define SSPCR0 (SSPBase->SSP_CR0)</span>
|
||
|
|
<a name="l00391"></a>00391 <span class="preprocessor"></span><span class="preprocessor">#define SSPCR1 (SSPBase->SSP_CR1)</span>
|
||
|
|
<a name="l00392"></a>00392 <span class="preprocessor"></span><span class="preprocessor">#define SSPDR (SSPBase->SSP_DR)</span>
|
||
|
|
<a name="l00393"></a>00393 <span class="preprocessor"></span><span class="preprocessor">#define SSPSR (SSPBase->SSP_SR)</span>
|
||
|
|
<a name="l00394"></a>00394 <span class="preprocessor"></span><span class="preprocessor">#define SSPCPSR (SSPBase->SSP_CPSR)</span>
|
||
|
|
<a name="l00395"></a>00395 <span class="preprocessor"></span><span class="preprocessor">#define SSPIMSC (SSPBase->SSP_IMSC)</span>
|
||
|
|
<a name="l00396"></a>00396 <span class="preprocessor"></span><span class="preprocessor">#define SSPRIS (SSPBase->SSP_RIS)</span>
|
||
|
|
<a name="l00397"></a>00397 <span class="preprocessor"></span><span class="preprocessor">#define SSPMIS (SSPBase->SSP_MIS)</span>
|
||
|
|
<a name="l00398"></a>00398 <span class="preprocessor"></span><span class="preprocessor">#define SSPICR (SSPBase->SSP_ICR)</span>
|
||
|
|
<a name="l00399"></a>00399 <span class="preprocessor"></span>
|
||
|
|
<a name="l00400"></a>00400 <span class="preprocessor">#define CR0_DSS4BIT 3</span>
|
||
|
|
<a name="l00401"></a>00401 <span class="preprocessor"></span><span class="preprocessor">#define CR0_DSS5BIT 4</span>
|
||
|
|
<a name="l00402"></a>00402 <span class="preprocessor"></span><span class="preprocessor">#define CR0_DSS6BIT 5</span>
|
||
|
|
<a name="l00403"></a>00403 <span class="preprocessor"></span><span class="preprocessor">#define CR0_DSS7BIT 6</span>
|
||
|
|
<a name="l00404"></a>00404 <span class="preprocessor"></span><span class="preprocessor">#define CR0_DSS8BIT 7</span>
|
||
|
|
<a name="l00405"></a>00405 <span class="preprocessor"></span><span class="preprocessor">#define CR0_DSS9BIT 8</span>
|
||
|
|
<a name="l00406"></a>00406 <span class="preprocessor"></span><span class="preprocessor">#define CR0_DSS10BIT 9</span>
|
||
|
|
<a name="l00407"></a>00407 <span class="preprocessor"></span><span class="preprocessor">#define CR0_DSS11BIT 0xA</span>
|
||
|
|
<a name="l00408"></a>00408 <span class="preprocessor"></span><span class="preprocessor">#define CR0_DSS12BIT 0xB</span>
|
||
|
|
<a name="l00409"></a>00409 <span class="preprocessor"></span><span class="preprocessor">#define CR0_DSS13BIT 0xC</span>
|
||
|
|
<a name="l00410"></a>00410 <span class="preprocessor"></span><span class="preprocessor">#define CR0_DSS14BIT 0xD</span>
|
||
|
|
<a name="l00411"></a>00411 <span class="preprocessor"></span><span class="preprocessor">#define CR0_DSS15BIT 0xE</span>
|
||
|
|
<a name="l00412"></a>00412 <span class="preprocessor"></span><span class="preprocessor">#define CR0_DSS16BIT 0xF</span>
|
||
|
|
<a name="l00413"></a>00413 <span class="preprocessor"></span><span class="preprocessor">#define CR0_FRFSPI 0</span>
|
||
|
|
<a name="l00414"></a>00414 <span class="preprocessor"></span><span class="preprocessor">#define CR0_FRFSSI 0x10</span>
|
||
|
|
<a name="l00415"></a>00415 <span class="preprocessor"></span><span class="preprocessor">#define CR0_FRFMW 0x20</span>
|
||
|
|
<a name="l00416"></a>00416 <span class="preprocessor"></span><span class="preprocessor">#define CR0_CPOL 0x40</span>
|
||
|
|
<a name="l00417"></a>00417 <span class="preprocessor"></span><span class="preprocessor">#define CR0_CPHA 0x80</span>
|
||
|
|
<a name="l00418"></a>00418 <span class="preprocessor"></span><span class="preprocessor">#define CR0_CLOCKRATE(n) ((n) << 8)</span>
|
||
|
|
<a name="l00419"></a>00419 <span class="preprocessor"></span>
|
||
|
|
<a name="l00420"></a>00420 <span class="preprocessor">#define CR1_LBM 1</span>
|
||
|
|
<a name="l00421"></a>00421 <span class="preprocessor"></span><span class="preprocessor">#define CR1_SSE 2</span>
|
||
|
|
<a name="l00422"></a>00422 <span class="preprocessor"></span><span class="preprocessor">#define CR1_MS 4</span>
|
||
|
|
<a name="l00423"></a>00423 <span class="preprocessor"></span><span class="preprocessor">#define CR1_SOD 8</span>
|
||
|
|
<a name="l00424"></a>00424 <span class="preprocessor"></span>
|
||
|
|
<a name="l00425"></a>00425 <span class="preprocessor">#define SR_TFE 1</span>
|
||
|
|
<a name="l00426"></a>00426 <span class="preprocessor"></span><span class="preprocessor">#define SR_TNF 2</span>
|
||
|
|
<a name="l00427"></a>00427 <span class="preprocessor"></span><span class="preprocessor">#define SR_RNE 4</span>
|
||
|
|
<a name="l00428"></a>00428 <span class="preprocessor"></span><span class="preprocessor">#define SR_RFF 8</span>
|
||
|
|
<a name="l00429"></a>00429 <span class="preprocessor"></span><span class="preprocessor">#define SR_BSY 0x10</span>
|
||
|
|
<a name="l00430"></a>00430 <span class="preprocessor"></span>
|
||
|
|
<a name="l00431"></a>00431 <span class="preprocessor">#define IMSC_ROR 1</span>
|
||
|
|
<a name="l00432"></a>00432 <span class="preprocessor"></span><span class="preprocessor">#define IMSC_RT 2</span>
|
||
|
|
<a name="l00433"></a>00433 <span class="preprocessor"></span><span class="preprocessor">#define IMSC_RX 4</span>
|
||
|
|
<a name="l00434"></a>00434 <span class="preprocessor"></span><span class="preprocessor">#define IMSC_TX 8</span>
|
||
|
|
<a name="l00435"></a>00435 <span class="preprocessor"></span>
|
||
|
|
<a name="l00436"></a>00436 <span class="preprocessor">#define RIS_ROR 1</span>
|
||
|
|
<a name="l00437"></a>00437 <span class="preprocessor"></span><span class="preprocessor">#define RIS_RT 2</span>
|
||
|
|
<a name="l00438"></a>00438 <span class="preprocessor"></span><span class="preprocessor">#define RIS_RX 4</span>
|
||
|
|
<a name="l00439"></a>00439 <span class="preprocessor"></span><span class="preprocessor">#define RIS_TX 8</span>
|
||
|
|
<a name="l00440"></a>00440 <span class="preprocessor"></span>
|
||
|
|
<a name="l00441"></a>00441 <span class="preprocessor">#define MIS_ROR 1</span>
|
||
|
|
<a name="l00442"></a>00442 <span class="preprocessor"></span><span class="preprocessor">#define MIS_RT 2</span>
|
||
|
|
<a name="l00443"></a>00443 <span class="preprocessor"></span><span class="preprocessor">#define MIS_RX 4</span>
|
||
|
|
<a name="l00444"></a>00444 <span class="preprocessor"></span><span class="preprocessor">#define MIS_TX 8</span>
|
||
|
|
<a name="l00445"></a>00445 <span class="preprocessor"></span>
|
||
|
|
<a name="l00446"></a>00446 <span class="preprocessor">#define ICR_ROR 1</span>
|
||
|
|
<a name="l00447"></a>00447 <span class="preprocessor"></span><span class="preprocessor">#define ICR_RT 2</span>
|
||
|
|
<a name="l00448"></a>00448 <span class="preprocessor"></span>
|
||
|
|
<a name="l00449"></a>00449 <span class="comment">/*</span>
|
||
|
|
<a name="l00450"></a>00450 <span class="comment"> * Timers/Counters.</span>
|
||
|
|
<a name="l00451"></a>00451 <span class="comment"> */</span>
|
||
|
|
<a name="l00452"></a>00452 <span class="keyword">typedef</span> <span class="keyword">struct </span>{
|
||
|
|
<a name="l00453"></a>00453 <a class="code" href="group___a_r_m_c_mx___n_v_i_c.html#gaaf485fff865c489bedf668cb8a478a68">IOREG32</a> TC_IR;
|
||
|
|
<a name="l00454"></a>00454 <a class="code" href="group___a_r_m_c_mx___n_v_i_c.html#gaaf485fff865c489bedf668cb8a478a68">IOREG32</a> TC_TCR;
|
||
|
|
<a name="l00455"></a>00455 <a class="code" href="group___a_r_m_c_mx___n_v_i_c.html#gaaf485fff865c489bedf668cb8a478a68">IOREG32</a> TC_TC;
|
||
|
|
<a name="l00456"></a>00456 <a class="code" href="group___a_r_m_c_mx___n_v_i_c.html#gaaf485fff865c489bedf668cb8a478a68">IOREG32</a> TC_PR;
|
||
|
|
<a name="l00457"></a>00457 <a class="code" href="group___a_r_m_c_mx___n_v_i_c.html#gaaf485fff865c489bedf668cb8a478a68">IOREG32</a> TC_PC;
|
||
|
|
<a name="l00458"></a>00458 <a class="code" href="group___a_r_m_c_mx___n_v_i_c.html#gaaf485fff865c489bedf668cb8a478a68">IOREG32</a> TC_MCR;
|
||
|
|
<a name="l00459"></a>00459 <a class="code" href="group___a_r_m_c_mx___n_v_i_c.html#gaaf485fff865c489bedf668cb8a478a68">IOREG32</a> TC_MR0;
|
||
|
|
<a name="l00460"></a>00460 <a class="code" href="group___a_r_m_c_mx___n_v_i_c.html#gaaf485fff865c489bedf668cb8a478a68">IOREG32</a> TC_MR1;
|
||
|
|
<a name="l00461"></a>00461 <a class="code" href="group___a_r_m_c_mx___n_v_i_c.html#gaaf485fff865c489bedf668cb8a478a68">IOREG32</a> TC_MR2;
|
||
|
|
<a name="l00462"></a>00462 <a class="code" href="group___a_r_m_c_mx___n_v_i_c.html#gaaf485fff865c489bedf668cb8a478a68">IOREG32</a> TC_MR3;
|
||
|
|
<a name="l00463"></a>00463 <a class="code" href="group___a_r_m_c_mx___n_v_i_c.html#gaaf485fff865c489bedf668cb8a478a68">IOREG32</a> TC_CCR;
|
||
|
|
<a name="l00464"></a>00464 <a class="code" href="group___a_r_m_c_mx___n_v_i_c.html#gaaf485fff865c489bedf668cb8a478a68">IOREG32</a> TC_CR0;
|
||
|
|
<a name="l00465"></a>00465 <a class="code" href="group___a_r_m_c_mx___n_v_i_c.html#gaaf485fff865c489bedf668cb8a478a68">IOREG32</a> TC_CR1;
|
||
|
|
<a name="l00466"></a>00466 <a class="code" href="group___a_r_m_c_mx___n_v_i_c.html#gaaf485fff865c489bedf668cb8a478a68">IOREG32</a> TC_CR2;
|
||
|
|
<a name="l00467"></a>00467 <a class="code" href="group___a_r_m_c_mx___n_v_i_c.html#gaaf485fff865c489bedf668cb8a478a68">IOREG32</a> TC_CR3;
|
||
|
|
<a name="l00468"></a>00468 <a class="code" href="group___a_r_m_c_mx___n_v_i_c.html#gaaf485fff865c489bedf668cb8a478a68">IOREG32</a> TC_EMR;
|
||
|
|
<a name="l00469"></a>00469 <a class="code" href="group___a_r_m_c_mx___n_v_i_c.html#gaaf485fff865c489bedf668cb8a478a68">IOREG32</a> TC_CTCR;
|
||
|
|
<a name="l00470"></a>00470 } TC;
|
||
|
|
<a name="l00471"></a>00471
|
||
|
|
<a name="l00472"></a>00472 <span class="preprocessor">#define T0Base ((TC *)0xE0004000)</span>
|
||
|
|
<a name="l00473"></a>00473 <span class="preprocessor"></span><span class="preprocessor">#define T0IR (T0Base->TC_IR)</span>
|
||
|
|
<a name="l00474"></a>00474 <span class="preprocessor"></span><span class="preprocessor">#define T0TCR (T0Base->TC_TCR)</span>
|
||
|
|
<a name="l00475"></a>00475 <span class="preprocessor"></span><span class="preprocessor">#define T0TC (T0Base->TC_TC)</span>
|
||
|
|
<a name="l00476"></a>00476 <span class="preprocessor"></span><span class="preprocessor">#define T0PR (T0Base->TC_PR)</span>
|
||
|
|
<a name="l00477"></a>00477 <span class="preprocessor"></span><span class="preprocessor">#define T0PC (T0Base->TC_PC)</span>
|
||
|
|
<a name="l00478"></a>00478 <span class="preprocessor"></span><span class="preprocessor">#define T0MCR (T0Base->TC_MCR)</span>
|
||
|
|
<a name="l00479"></a>00479 <span class="preprocessor"></span><span class="preprocessor">#define T0MR0 (T0Base->TC_MR0)</span>
|
||
|
|
<a name="l00480"></a>00480 <span class="preprocessor"></span><span class="preprocessor">#define T0MR1 (T0Base->TC_MR1)</span>
|
||
|
|
<a name="l00481"></a>00481 <span class="preprocessor"></span><span class="preprocessor">#define T0MR2 (T0Base->TC_MR2)</span>
|
||
|
|
<a name="l00482"></a>00482 <span class="preprocessor"></span><span class="preprocessor">#define T0MR3 (T0Base->TC_MR3)</span>
|
||
|
|
<a name="l00483"></a>00483 <span class="preprocessor"></span><span class="preprocessor">#define T0CCR (T0Base->TC_CCR)</span>
|
||
|
|
<a name="l00484"></a>00484 <span class="preprocessor"></span><span class="preprocessor">#define T0CR0 (T0Base->TC_CR0)</span>
|
||
|
|
<a name="l00485"></a>00485 <span class="preprocessor"></span><span class="preprocessor">#define T0CR1 (T0Base->TC_CR1)</span>
|
||
|
|
<a name="l00486"></a>00486 <span class="preprocessor"></span><span class="preprocessor">#define T0CR2 (T0Base->TC_CR2)</span>
|
||
|
|
<a name="l00487"></a>00487 <span class="preprocessor"></span><span class="preprocessor">#define T0CR3 (T0Base->TC_CR3)</span>
|
||
|
|
<a name="l00488"></a>00488 <span class="preprocessor"></span><span class="preprocessor">#define T0EMR (T0Base->TC_EMR)</span>
|
||
|
|
<a name="l00489"></a>00489 <span class="preprocessor"></span><span class="preprocessor">#define T0CTCR (T0Base->TC_CTCR)</span>
|
||
|
|
<a name="l00490"></a>00490 <span class="preprocessor"></span>
|
||
|
|
<a name="l00491"></a>00491 <span class="preprocessor">#define T1Base ((TC *)0xE0008000)</span>
|
||
|
|
<a name="l00492"></a>00492 <span class="preprocessor"></span><span class="preprocessor">#define T1IR (T1Base->TC_IR)</span>
|
||
|
|
<a name="l00493"></a>00493 <span class="preprocessor"></span><span class="preprocessor">#define T1TCR (T1Base->TC_TCR)</span>
|
||
|
|
<a name="l00494"></a>00494 <span class="preprocessor"></span><span class="preprocessor">#define T1TC (T1Base->TC_TC)</span>
|
||
|
|
<a name="l00495"></a>00495 <span class="preprocessor"></span><span class="preprocessor">#define T1PR (T1Base->TC_PR)</span>
|
||
|
|
<a name="l00496"></a>00496 <span class="preprocessor"></span><span class="preprocessor">#define T1PC (T1Base->TC_PC)</span>
|
||
|
|
<a name="l00497"></a>00497 <span class="preprocessor"></span><span class="preprocessor">#define T1MCR (T1Base->TC_MCR)</span>
|
||
|
|
<a name="l00498"></a>00498 <span class="preprocessor"></span><span class="preprocessor">#define T1MR0 (T1Base->TC_MR0)</span>
|
||
|
|
<a name="l00499"></a>00499 <span class="preprocessor"></span><span class="preprocessor">#define T1MR1 (T1Base->TC_MR1)</span>
|
||
|
|
<a name="l00500"></a>00500 <span class="preprocessor"></span><span class="preprocessor">#define T1MR2 (T1Base->TC_MR2)</span>
|
||
|
|
<a name="l00501"></a>00501 <span class="preprocessor"></span><span class="preprocessor">#define T1MR3 (T1Base->TC_MR3)</span>
|
||
|
|
<a name="l00502"></a>00502 <span class="preprocessor"></span><span class="preprocessor">#define T1CCR (T1Base->TC_CCR)</span>
|
||
|
|
<a name="l00503"></a>00503 <span class="preprocessor"></span><span class="preprocessor">#define T1CR0 (T1Base->TC_CR0)</span>
|
||
|
|
<a name="l00504"></a>00504 <span class="preprocessor"></span><span class="preprocessor">#define T1CR1 (T1Base->TC_CR1)</span>
|
||
|
|
<a name="l00505"></a>00505 <span class="preprocessor"></span><span class="preprocessor">#define T1CR2 (T1Base->TC_CR2)</span>
|
||
|
|
<a name="l00506"></a>00506 <span class="preprocessor"></span><span class="preprocessor">#define T1CR3 (T1Base->TC_CR3)</span>
|
||
|
|
<a name="l00507"></a>00507 <span class="preprocessor"></span><span class="preprocessor">#define T1EMR (T1Base->TC_EMR)</span>
|
||
|
|
<a name="l00508"></a>00508 <span class="preprocessor"></span><span class="preprocessor">#define T1CTCR (T1Base->TC_CTCR)</span>
|
||
|
|
<a name="l00509"></a>00509 <span class="preprocessor"></span>
|
||
|
|
<a name="l00510"></a>00510 <span class="comment">/*</span>
|
||
|
|
<a name="l00511"></a>00511 <span class="comment"> * Watchdog.</span>
|
||
|
|
<a name="l00512"></a>00512 <span class="comment"> */</span>
|
||
|
|
<a name="l00513"></a>00513 <span class="keyword">typedef</span> <span class="keyword">struct </span>{
|
||
|
|
<a name="l00514"></a>00514 <a class="code" href="group___a_r_m_c_mx___n_v_i_c.html#gaaf485fff865c489bedf668cb8a478a68">IOREG32</a> WD_MOD;
|
||
|
|
<a name="l00515"></a>00515 <a class="code" href="group___a_r_m_c_mx___n_v_i_c.html#gaaf485fff865c489bedf668cb8a478a68">IOREG32</a> WD_TC;
|
||
|
|
<a name="l00516"></a>00516 <a class="code" href="group___a_r_m_c_mx___n_v_i_c.html#gaaf485fff865c489bedf668cb8a478a68">IOREG32</a> WD_FEED;
|
||
|
|
<a name="l00517"></a>00517 <a class="code" href="group___a_r_m_c_mx___n_v_i_c.html#gaaf485fff865c489bedf668cb8a478a68">IOREG32</a> WD_TV;
|
||
|
|
<a name="l00518"></a>00518 } WD;
|
||
|
|
<a name="l00519"></a>00519
|
||
|
|
<a name="l00520"></a>00520 <span class="preprocessor">#define WDBase ((WD *)0xE0000000)</span>
|
||
|
|
<a name="l00521"></a>00521 <span class="preprocessor"></span><span class="preprocessor">#define WDMOD (WDBase->WD_MOD)</span>
|
||
|
|
<a name="l00522"></a>00522 <span class="preprocessor"></span><span class="preprocessor">#define WDTC (WDBase->WD_TC)</span>
|
||
|
|
<a name="l00523"></a>00523 <span class="preprocessor"></span><span class="preprocessor">#define WDFEED (WDBase->WD_FEED)</span>
|
||
|
|
<a name="l00524"></a>00524 <span class="preprocessor"></span><span class="preprocessor">#define WDTV (WDBase->WD_TV)</span>
|
||
|
|
<a name="l00525"></a>00525 <span class="preprocessor"></span>
|
||
|
|
<a name="l00526"></a>00526 <span class="comment">/*</span>
|
||
|
|
<a name="l00527"></a>00527 <span class="comment"> * DAC.</span>
|
||
|
|
<a name="l00528"></a>00528 <span class="comment"> */</span>
|
||
|
|
<a name="l00529"></a>00529 <span class="preprocessor">#define DACR (*((IOREG32 *)0xE006C000))</span>
|
||
|
|
<a name="l00530"></a>00530 <span class="preprocessor"></span>
|
||
|
|
<a name="l00531"></a>00531 <span class="preprocessor">#endif </span><span class="comment">/* _LPC214X_H_ */</span>
|
||
|
|
<a name="l00532"></a>00532
|
||
|
|
</pre></div></div>
|
||
|
|
<hr size="1"><address style="text-align: right;"><small>
|
||
|
|
Generated on Sun Jul 11 13:13:01 2010 for ChibiOS/RT by <a href="http://www.doxygen.org/index.html"><img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.6.3</small></address>
|
||
|
|
</body>
|
||
|
|
</html>
|