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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
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<html><head><meta http-equiv="Content-Type" content="text/html;charset=UTF-8">
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<title>ChibiOS/RT: nvic.h File Reference</title>
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<td style="width: 80px;"><img alt="ChibiOS/RT Logo" src="logo_small.png"></td>
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<td><big><big>ChibiOS/RT</big></big><br><br>Architecture - Reference Manual - Guides</td>
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<li><a href="annotated.html"><span>Data Structures</span></a></li>
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<div class="contents">
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<h1>nvic.h File Reference</h1>
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<p>Cortex-Mx NVIC support macros and structures.
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<a href="#_details">More...</a></p>
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<p><a href="nvic_8h_source.html">Go to the source code of this file.</a></p>
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<table border="0" cellpadding="0" cellspacing="0">
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<tr><td colspan="2"><h2>Data Structures</h2></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">struct </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_m3___s_t.html">CM3_ST</a></td></tr>
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<tr><td class="mdescLeft"> </td><td class="mdescRight">Structure representing the SYSTICK I/O space. <a href="struct_c_m3___s_t.html#_details">More...</a><br/></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">struct </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_m3___n_v_i_c.html">CM3_NVIC</a></td></tr>
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<tr><td class="mdescLeft"> </td><td class="mdescRight">Structure representing the NVIC I/O space. <a href="struct_c_m3___n_v_i_c.html#_details">More...</a><br/></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">struct </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_m3___s_c_b.html">CM3_SCB</a></td></tr>
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<tr><td class="mdescLeft"> </td><td class="mdescRight">Structure representing the System Control Block I/O space. <a href="struct_c_m3___s_c_b.html#_details">More...</a><br/></td></tr>
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<tr><td colspan="2"><h2>Defines</h2></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___a_r_m_c_mx___n_v_i_c.html#gab6ec63854f5a572650a0da800e12974f">HANDLER_MEM_MANAGE</a> 0</td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___a_r_m_c_mx___n_v_i_c.html#gaea14651f492c92bd57e4625364d69ff2">HANDLER_BUS_FAULT</a> 1</td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___a_r_m_c_mx___n_v_i_c.html#ga5fd129625060d09dd552182cccb99a1d">HANDLER_USAGE_FAULT</a> 2</td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___a_r_m_c_mx___n_v_i_c.html#gaf1a1755ab445b421e7213fcab63bced5">HANDLER_SVCALL</a> 7</td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___a_r_m_c_mx___n_v_i_c.html#ga916caa231c853049768c4b3e214f796b">HANDLER_DEBUG_MONITOR</a> 8</td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___a_r_m_c_mx___n_v_i_c.html#ga4a9ffb0f74fc91f6dac8a54422e24c64">HANDLER_PENDSV</a> 10</td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___a_r_m_c_mx___n_v_i_c.html#ga9af0796781886f000d84c841b61a77e2">HANDLER_SYSTICK</a> 11</td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___a_r_m_c_mx___n_v_i_c.html#ga005f75c1323f8573abdf5894e8da7552">NVIC_ITCR</a> (*((<a class="el" href="group___a_r_m_c_mx___n_v_i_c.html#gaaf485fff865c489bedf668cb8a478a68">IOREG32</a> *)0xE000E004))</td></tr>
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<tr><td class="mdescLeft"> </td><td class="mdescRight">NVIC ITCR register. <a href="group___a_r_m_c_mx___n_v_i_c.html#ga005f75c1323f8573abdf5894e8da7552"></a><br/></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___a_r_m_c_mx___n_v_i_c.html#gaaa80bc30d455351b9231f252632d481b">NVIC_STIR</a> (*((<a class="el" href="group___a_r_m_c_mx___n_v_i_c.html#gaaf485fff865c489bedf668cb8a478a68">IOREG32</a> *)0xE000EF00))</td></tr>
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<tr><td class="mdescLeft"> </td><td class="mdescRight">NVIC STIR register. <a href="group___a_r_m_c_mx___n_v_i_c.html#gaaa80bc30d455351b9231f252632d481b"></a><br/></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___a_r_m_c_mx___n_v_i_c.html#ga53599e3baa092c73f97a33c3f0889fe5">STBase</a> ((<a class="el" href="struct_c_m3___s_t.html">CM3_ST</a> *)0xE000E010)</td></tr>
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<tr><td class="mdescLeft"> </td><td class="mdescRight">SYSTICK peripheral base address. <a href="group___a_r_m_c_mx___n_v_i_c.html#ga53599e3baa092c73f97a33c3f0889fe5"></a><br/></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___a_r_m_c_mx___n_v_i_c.html#ga9be85cd1df2d663931254c92e2d822ad">NVICBase</a> ((<a class="el" href="struct_c_m3___n_v_i_c.html">CM3_NVIC</a> *)0xE000E100)</td></tr>
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<tr><td class="mdescLeft"> </td><td class="mdescRight">NVIC peripheral base address. <a href="group___a_r_m_c_mx___n_v_i_c.html#ga9be85cd1df2d663931254c92e2d822ad"></a><br/></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___a_r_m_c_mx___n_v_i_c.html#gae0b689c91aa1605a75ff3c07b1846187">SCBBase</a> ((<a class="el" href="struct_c_m3___s_c_b.html">CM3_SCB</a> *)0xE000ED00)</td></tr>
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<tr><td class="mdescLeft"> </td><td class="mdescRight">SCB peripheral base address. <a href="group___a_r_m_c_mx___n_v_i_c.html#gae0b689c91aa1605a75ff3c07b1846187"></a><br/></td></tr>
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<tr><td colspan="2"><h2>Typedefs</h2></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">typedef volatile <a class="el" href="group___s_t_m8___c_o_r_e.html#gaba7bc1797add20fe3efdf37ced1182c5">uint8_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="group___a_r_m_c_mx___n_v_i_c.html#gaa8b1de9f01a8c9bf3363436874058cb2">IOREG8</a></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">typedef volatile <a class="el" href="group___s_t_m8___c_o_r_e.html#ga06896e8c53f721507066c079052171f8">uint32_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="group___a_r_m_c_mx___n_v_i_c.html#gaaf485fff865c489bedf668cb8a478a68">IOREG32</a></td></tr>
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<tr><td colspan="2"><h2>Functions</h2></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___a_r_m_c_mx___n_v_i_c.html#ga607470c0f5d4bd0ee0f7208a9def4986">NVICEnableVector</a> (<a class="el" href="group___s_t_m8___c_o_r_e.html#ga06896e8c53f721507066c079052171f8">uint32_t</a> n, <a class="el" href="group___s_t_m8___c_o_r_e.html#ga06896e8c53f721507066c079052171f8">uint32_t</a> prio)</td></tr>
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<tr><td class="mdescLeft"> </td><td class="mdescRight">Sets the priority of an interrupt handler and enables it. <a href="group___a_r_m_c_mx___n_v_i_c.html#ga607470c0f5d4bd0ee0f7208a9def4986"></a><br/></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___a_r_m_c_mx___n_v_i_c.html#ga66f3c540c80ac9d9ea7878671b0bd59e">NVICDisableVector</a> (<a class="el" href="group___s_t_m8___c_o_r_e.html#ga06896e8c53f721507066c079052171f8">uint32_t</a> n)</td></tr>
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<tr><td class="mdescLeft"> </td><td class="mdescRight">Disables an interrupt handler. <a href="group___a_r_m_c_mx___n_v_i_c.html#ga66f3c540c80ac9d9ea7878671b0bd59e"></a><br/></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___a_r_m_c_mx___n_v_i_c.html#ga0e210980bade4563602ebd04325f3cec">NVICSetSystemHandlerPriority</a> (<a class="el" href="group___s_t_m8___c_o_r_e.html#ga06896e8c53f721507066c079052171f8">uint32_t</a> handler, <a class="el" href="group___s_t_m8___c_o_r_e.html#ga06896e8c53f721507066c079052171f8">uint32_t</a> prio)</td></tr>
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<tr><td class="mdescLeft"> </td><td class="mdescRight">Changes the priority of a system handler. <a href="group___a_r_m_c_mx___n_v_i_c.html#ga0e210980bade4563602ebd04325f3cec"></a><br/></td></tr>
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</table>
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<hr/><a name="_details"></a><h2>Detailed Description</h2>
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<p>Cortex-Mx NVIC support macros and structures. </p>
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<p>Definition in file <a class="el" href="nvic_8h_source.html">nvic.h</a>.</p>
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<hr size="1"><address style="text-align: right;"><small>
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Generated on Sun Jul 11 13:13:02 2010 for ChibiOS/RT by <a href="http://www.doxygen.org/index.html"><img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.6.3</small></address>
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